arch/powerpc/cpu/mpc85xx/fdt.c

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/processor.h>
  30 #include <linux/ctype.h>
  31 #include <asm/io.h>
  32 #include <asm/fsl_portals.h>
  33 #ifdef CONFIG_FSL_ESDHC
  34 #include <fsl_esdhc.h>
  35 #endif
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 extern void ft_qe_setup(void *blob);
  40 extern void ft_fixup_num_cores(void *blob);
  41
  42 #ifdef CONFIG_MP
  43 #include "mp.h"
  44
  45 void ft_fixup_cpu(void *blob, u64 memory_limit)
  46 {
  47         int off;
  48         ulong spin_tbl_addr = get_spin_phys_addr();
  49         u32 bootpg = determine_mp_bootpg();
  50         u32 id = get_my_id();
  51
  52         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  53         while (off != -FDT_ERR_NOTFOUND) {
  54                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  55
  56                 if (reg) {
  57                         if (*reg == id) {
  58                                 fdt_setprop_string(blob, off, "status", "okay");
  59                         } else {
  60                                 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
  61                                 val = cpu_to_fdt32(val);
  62                                 fdt_setprop_string(blob, off, "status",
  63                                                                 "disabled");
  64                                 fdt_setprop_string(blob, off, "enable-method",
  65                                                                 "spin-table");
  66                                 fdt_setprop(blob, off, "cpu-release-addr",
  67                                                 &val, sizeof(val));
  68                         }
  69                 } else {
  70                         printf ("cpu NULL\n");
  71                 }
  72                 off = fdt_node_offset_by_prop_value(blob, off,
  73                                 "device_type", "cpu", 4);
  74         }
  75
  76         /* Reserve the boot page so OSes dont use it */
  77         if ((u64)bootpg < memory_limit) {
  78                 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  79                 if (off < 0)
  80                         printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
  81         }
  82 }
  83 #endif
  84
  85 #ifdef CONFIG_SYS_FSL_CPC
  86 static inline void ft_fixup_l3cache(void *blob, int off)
  87 {
  88         u32 line_size, num_ways, size, num_sets;
  89         cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
  90         u32 cfg0 = in_be32(&cpc->cpccfg0);
  91
  92         size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
  93         num_ways = CPC_CFG0_NUM_WAYS(cfg0);
  94         line_size = CPC_CFG0_LINE_SZ(cfg0);
  95         num_sets = size / (line_size * num_ways);
  96
  97         fdt_setprop(blob, off, "cache-unified", NULL, 0);
  98         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  99         fdt_setprop_cell(blob, off, "cache-size", size);
 100         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 101         fdt_setprop_cell(blob, off, "cache-level", 3);
 102 #ifdef CONFIG_SYS_CACHE_STASHING
 103         fdt_setprop_cell(blob, off, "cache-stash-id", 1);
 104 #endif
 105 }
 106 #else
 107 #define ft_fixup_l3cache(x, y)
 108 #endif
 109
 110 #if defined(CONFIG_L2_CACHE)
 111 /* return size in kilobytes */
 112 static inline u32 l2cache_size(void)
 113 {
 114         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 115         volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
 116         u32 ver = SVR_SOC_VER(get_svr());
 117
 118         switch (l2siz_field) {
 119         case 0x0:
 120                 break;
 121         case 0x1:
 122                 if (ver == SVR_8540 || ver == SVR_8560   ||
 123                     ver == SVR_8541 || ver == SVR_8541_E ||
 124                     ver == SVR_8555 || ver == SVR_8555_E)
 125                         return 128;
 126                 else
 127                         return 256;
 128                 break;
 129         case 0x2:
 130                 if (ver == SVR_8540 || ver == SVR_8560   ||
 131                     ver == SVR_8541 || ver == SVR_8541_E ||
 132                     ver == SVR_8555 || ver == SVR_8555_E)
 133                         return 256;
 134                 else
 135                         return 512;
 136                 break;
 137         case 0x3:
 138                 return 1024;
 139                 break;
 140         }
 141
 142         return 0;
 143 }
 144
 145 static inline void ft_fixup_l2cache(void *blob)
 146 {
 147         int len, off;
 148         u32 *ph;
 149         struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 150         char compat_buf[38];
 151
 152         const u32 line_size = 32;
 153         const u32 num_ways = 8;
 154         const u32 size = l2cache_size() * 1024;
 155         const u32 num_sets = size / (line_size * num_ways);
 156
 157         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 158         if (off < 0) {
 159                 debug("no cpu node fount\n");
 160                 return;
 161         }
 162
 163         ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 164
 165         if (ph == NULL) {
 166                 debug("no next-level-cache property\n");
 167                 return ;
 168         }
 169
 170         off = fdt_node_offset_by_phandle(blob, *ph);
 171         if (off < 0) {
 172                 printf("%s: %s\n", __func__, fdt_strerror(off));
 173                 return ;
 174         }
 175
 176         if (cpu) {
 177                 if (isdigit(cpu->name[0]))
 178                         len = sprintf(compat_buf,
 179                                 "fsl,mpc%s-l2-cache-controller", cpu->name);
 180                 else
 181                         len = sprintf(compat_buf,
 182                                 "fsl,%c%s-l2-cache-controller",
 183                                 tolower(cpu->name[0]), cpu->name + 1);
 184
 185                 sprintf(&compat_buf[len + 1], "cache");
 186         }
 187         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 188         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 189         fdt_setprop_cell(blob, off, "cache-size", size);
 190         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 191         fdt_setprop_cell(blob, off, "cache-level", 2);
 192         fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
 193
 194         /* we dont bother w/L3 since no platform of this type has one */
 195 }
 196 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 197 static inline void ft_fixup_l2cache(void *blob)
 198 {
 199         int off, l2_off, l3_off = -1;
 200         u32 *ph;
 201         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 202         u32 size, line_size, num_ways, num_sets;
 203
 204         size = (l2cfg0 & 0x3fff) * 64 * 1024;
 205         num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
 206         line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
 207         num_sets = size / (line_size * num_ways);
 208
 209         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 210
 211         while (off != -FDT_ERR_NOTFOUND) {
 212                 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 213
 214                 if (ph == NULL) {
 215                         debug("no next-level-cache property\n");
 216                         goto next;
 217                 }
 218
 219                 l2_off = fdt_node_offset_by_phandle(blob, *ph);
 220                 if (l2_off < 0) {
 221                         printf("%s: %s\n", __func__, fdt_strerror(off));
 222                         goto next;
 223                 }
 224
 225 #ifdef CONFIG_SYS_CACHE_STASHING
 226                 {
 227                         u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 228                         if (reg)
 229                                 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 230                                          (*reg * 2) + 32 + 1);
 231                 }
 232 #endif
 233
 234                 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
 235                 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
 236                 fdt_setprop_cell(blob, l2_off, "cache-size", size);
 237                 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
 238                 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
 239                 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
 240
 241                 if (l3_off < 0) {
 242                         ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
 243
 244                         if (ph == NULL) {
 245                                 debug("no next-level-cache property\n");
 246                                 goto next;
 247                         }
 248                         l3_off = *ph;
 249                 }
 250 next:
 251                 off = fdt_node_offset_by_prop_value(blob, off,
 252                                 "device_type", "cpu", 4);
 253         }
 254         if (l3_off > 0) {
 255                 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
 256                 if (l3_off < 0) {
 257                         printf("%s: %s\n", __func__, fdt_strerror(off));
 258                         return ;
 259                 }
 260                 ft_fixup_l3cache(blob, l3_off);
 261         }
 262 }
 263 #else
 264 #define ft_fixup_l2cache(x)
 265 #endif
 266
 267 static inline void ft_fixup_cache(void *blob)
 268 {
 269         int off;
 270
 271         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 272
 273         while (off != -FDT_ERR_NOTFOUND) {
 274                 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 275                 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 276                 u32 isize, iline_size, inum_sets, inum_ways;
 277                 u32 dsize, dline_size, dnum_sets, dnum_ways;
 278
 279                 /* d-side config */
 280                 dsize = (l1cfg0 & 0x7ff) * 1024;
 281                 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 282                 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 283                 dnum_sets = dsize / (dline_size * dnum_ways);
 284
 285                 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 286                 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 287                 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 288
 289 #ifdef CONFIG_SYS_CACHE_STASHING
 290                 {
 291                         u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 292                         if (reg)
 293                                 fdt_setprop_cell(blob, off, "cache-stash-id",
 294                                          (*reg * 2) + 32 + 0);
 295                 }
 296 #endif
 297
 298                 /* i-side config */
 299                 isize = (l1cfg1 & 0x7ff) * 1024;
 300                 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 301                 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 302                 inum_sets = isize / (iline_size * inum_ways);
 303
 304                 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 305                 fdt_setprop_cell(blob, off, "i-cache-size", isize);
 306                 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 307
 308                 off = fdt_node_offset_by_prop_value(blob, off,
 309                                 "device_type", "cpu", 4);
 310         }
 311
 312         ft_fixup_l2cache(blob);
 313 }
 314
 315
 316 void fdt_add_enet_stashing(void *fdt)
 317 {
 318         do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
 319
 320         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 321
 322         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 323 }
 324
 325 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
 326 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
 327                           unsigned long freq)
 328 {
 329         phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
 330         int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
 331
 332         if (off >= 0) {
 333                 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
 334                 if (off > 0)
 335                         printf("WARNING enable to set clock-frequency "
 336                                 "for %s: %s\n", compat, fdt_strerror(off));
 337         }
 338 }
 339
 340 static void ft_fixup_dpaa_clks(void *blob)
 341 {
 342         sys_info_t sysinfo;
 343
 344         get_sys_info(&sysinfo);
 345         ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
 346                         sysinfo.freqFMan[0]);
 347
 348 #if (CONFIG_SYS_NUM_FMAN == 2)
 349         ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
 350                         sysinfo.freqFMan[1]);
 351 #endif
 352
 353 #ifdef CONFIG_SYS_DPAA_PME
 354         do_fixup_by_compat_u32(blob, "fsl,pme",
 355                 "clock-frequency", sysinfo.freqPME, 1);
 356 #endif
 357 }
 358 #else
 359 #define ft_fixup_dpaa_clks(x)
 360 #endif
 361
 362 #ifdef CONFIG_QE
 363 static void ft_fixup_qe_snum(void *blob)
 364 {
 365         unsigned int svr;
 366
 367         svr = mfspr(SPRN_SVR);
 368         if (SVR_SOC_VER(svr) == SVR_8569_E) {
 369                 if(IS_SVR_REV(svr, 1, 0))
 370                         do_fixup_by_compat_u32(blob, "fsl,qe",
 371                                 "fsl,qe-num-snums", 46, 1);
 372                 else
 373                         do_fixup_by_compat_u32(blob, "fsl,qe",
 374                                 "fsl,qe-num-snums", 76, 1);
 375         }
 376 }
 377 #endif
 378
 379 void ft_cpu_setup(void *blob, bd_t *bd)
 380 {
 381         int off;
 382         int val;
 383         sys_info_t sysinfo;
 384
 385         /* delete crypto node if not on an E-processor */
 386         if (!IS_E_PROCESSOR(get_svr()))
 387                 fdt_fixup_crypto_node(blob, 0);
 388
 389         fdt_fixup_ethernet(blob);
 390
 391         fdt_add_enet_stashing(blob);
 392
 393         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 394                 "timebase-frequency", get_tbclk(), 1);
 395         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 396                 "bus-frequency", bd->bi_busfreq, 1);
 397         get_sys_info(&sysinfo);
 398         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 399         while (off != -FDT_ERR_NOTFOUND) {
 400                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 401                 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
 402                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 403                 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 404                                                         "cpu", 4);
 405         }
 406         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 407                 "bus-frequency", bd->bi_busfreq, 1);
 408
 409         do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
 410                 "bus-frequency", gd->lbc_clk, 1);
 411         do_fixup_by_compat_u32(blob, "fsl,elbc",
 412                 "bus-frequency", gd->lbc_clk, 1);
 413 #ifdef CONFIG_QE
 414         ft_qe_setup(blob);
 415         ft_fixup_qe_snum(blob);
 416 #endif
 417
 418 #ifdef CONFIG_SYS_NS16550
 419         do_fixup_by_compat_u32(blob, "ns16550",
 420                 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 421 #endif
 422
 423 #ifdef CONFIG_CPM2
 424         do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 425                 "current-speed", bd->bi_baudrate, 1);
 426
 427         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 428                 "clock-frequency", bd->bi_brgfreq, 1);
 429 #endif
 430
 431 #ifdef CONFIG_FSL_CORENET
 432         do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
 433                 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 434 #endif
 435
 436         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 437
 438 #ifdef CONFIG_MP
 439         ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 440         ft_fixup_num_cores(blob);
 441 #endif
 442
 443         ft_fixup_cache(blob);
 444
 445 #if defined(CONFIG_FSL_ESDHC)
 446         fdt_fixup_esdhc(blob, bd);
 447 #endif
 448
 449         ft_fixup_dpaa_clks(blob);
 450
 451 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
 452         fdt_portal(blob, "fsl,bman-portal", "bman-portals",
 453                         (u64)CONFIG_SYS_BMAN_MEM_PHYS,
 454                         CONFIG_SYS_BMAN_MEM_SIZE);
 455 #endif
 456
 457 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
 458         fdt_portal(blob, "fsl,qman-portal", "qman-portals",
 459                         (u64)CONFIG_SYS_QMAN_MEM_PHYS,
 460                         CONFIG_SYS_QMAN_MEM_SIZE);
 461
 462         fdt_fixup_qportals(blob);
 463 #endif
 464 }