2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <fdt_support.h>
13 #include <asm/processor.h>
14 #include <linux/ctype.h>
16 #include <asm/fsl_fdt.h>
17 #include <asm/fsl_portals.h>
19 #ifdef CONFIG_FSL_ESDHC
20 #include <fsl_esdhc.h>
22 #ifdef CONFIG_SYS_DPAA_FMAN
26 DECLARE_GLOBAL_DATA_PTR
;
28 extern void ft_qe_setup(void *blob
);
29 extern void ft_fixup_num_cores(void *blob
);
30 extern void ft_srio_setup(void *blob
);
35 void ft_fixup_cpu(void *blob
, u64 memory_limit
)
38 phys_addr_t spin_tbl_addr
= get_spin_phys_addr();
39 u32 bootpg
= determine_mp_bootpg(NULL
);
41 const char *enable_method
;
42 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
44 int tdm_hwconfig_enabled
= 0;
45 char buffer
[HWCONFIG_BUFFER_SIZE
] = {0};
48 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
49 while (off
!= -FDT_ERR_NOTFOUND
) {
50 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
53 u32 phys_cpu_id
= thread_to_core(*reg
);
54 u64 val
= phys_cpu_id
* SIZE_BOOT_ENTRY
+ spin_tbl_addr
;
55 val
= cpu_to_fdt64(val
);
57 fdt_setprop_string(blob
, off
, "status",
60 fdt_setprop_string(blob
, off
, "status",
64 if (hold_cores_in_reset(0)) {
65 #ifdef CONFIG_FSL_CORENET
66 /* Cores held in reset, use BRR to release */
67 enable_method
= "fsl,brr-holdoff";
69 /* Cores held in reset, use EEBPCR to release */
70 enable_method
= "fsl,eebpcr-holdoff";
73 /* Cores out of reset and in a spin-loop */
74 enable_method
= "spin-table";
76 fdt_setprop(blob
, off
, "cpu-release-addr",
80 fdt_setprop_string(blob
, off
, "enable-method",
83 printf ("cpu NULL\n");
85 off
= fdt_node_offset_by_prop_value(blob
, off
,
86 "device_type", "cpu", 4);
89 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
90 #define CONFIG_MEM_HOLE_16M 0x1000000
92 * Extract hwconfig from environment.
93 * Search for tdm entry in hwconfig.
95 ret
= getenv_f("hwconfig", buffer
, sizeof(buffer
));
97 tdm_hwconfig_enabled
= hwconfig_f("tdm", buffer
);
99 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
100 if (tdm_hwconfig_enabled
) {
101 off
= fdt_add_mem_rsv(blob
, T1040_TDM_QUIRK_CCSR_BASE
,
102 CONFIG_MEM_HOLE_16M
);
104 printf("Failed to reserve memory for tdm: %s\n",
109 /* Reserve the boot page so OSes dont use it */
110 if ((u64
)bootpg
< memory_limit
) {
111 off
= fdt_add_mem_rsv(blob
, bootpg
, (u64
)4096);
113 printf("Failed to reserve memory for bootpg: %s\n",
117 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
119 * Reserve the default boot page so OSes dont use it.
120 * The default boot page is always mapped to bootpg above using
121 * boot page translation.
123 if (0xfffff000ull
< memory_limit
) {
124 off
= fdt_add_mem_rsv(blob
, 0xfffff000ull
, (u64
)4096);
126 printf("Failed to reserve memory for 0xfffff000: %s\n",
132 /* Reserve spin table page */
133 if (spin_tbl_addr
< memory_limit
) {
134 off
= fdt_add_mem_rsv(blob
,
135 (spin_tbl_addr
& ~0xffful
), 4096);
137 printf("Failed to reserve memory for spin table: %s\n",
140 #ifdef CONFIG_DEEP_SLEEP
141 #ifdef CONFIG_SPL_MMC_BOOT
142 off
= fdt_add_mem_rsv(blob
, CONFIG_SYS_MMC_U_BOOT_START
,
143 CONFIG_SYS_MMC_U_BOOT_SIZE
);
145 printf("Failed to reserve memory for SD deep sleep: %s\n",
147 #elif defined(CONFIG_SPL_SPI_BOOT)
148 off
= fdt_add_mem_rsv(blob
, CONFIG_SYS_SPI_FLASH_U_BOOT_START
,
149 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE
);
151 printf("Failed to reserve memory for SPI deep sleep: %s\n",
158 #ifdef CONFIG_SYS_FSL_CPC
159 static inline void ft_fixup_l3cache(void *blob
, int off
)
161 u32 line_size
, num_ways
, size
, num_sets
;
162 cpc_corenet_t
*cpc
= (void *)CONFIG_SYS_FSL_CPC_ADDR
;
163 u32 cfg0
= in_be32(&cpc
->cpccfg0
);
165 size
= CPC_CFG0_SZ_K(cfg0
) * 1024 * CONFIG_SYS_NUM_CPC
;
166 num_ways
= CPC_CFG0_NUM_WAYS(cfg0
);
167 line_size
= CPC_CFG0_LINE_SZ(cfg0
);
168 num_sets
= size
/ (line_size
* num_ways
);
170 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
171 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
172 fdt_setprop_cell(blob
, off
, "cache-size", size
);
173 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
174 fdt_setprop_cell(blob
, off
, "cache-level", 3);
175 #ifdef CONFIG_SYS_CACHE_STASHING
176 fdt_setprop_cell(blob
, off
, "cache-stash-id", 1);
180 #define ft_fixup_l3cache(x, y)
183 #if defined(CONFIG_L2_CACHE) || \
184 defined(CONFIG_BACKSIDE_L2_CACHE) || \
185 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
186 static inline void ft_fixup_l2cache_compatible(void *blob
, int off
)
189 struct cpu_type
*cpu
= identify_cpu(SVR_SOC_VER(get_svr()));
194 if (isdigit(cpu
->name
[0])) {
195 /* MPCxxxx, where xxxx == 4-digit number */
196 len
= sprintf(buf
, "fsl,mpc%s-l2-cache-controller",
199 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
200 len
= sprintf(buf
, "fsl,%c%s-l2-cache-controller",
201 tolower(cpu
->name
[0]), cpu
->name
+ 1) + 1;
205 * append "cache" after the NULL character that the previous
206 * sprintf wrote. This is how a device tree stores multiple
207 * strings in a property.
209 len
+= sprintf(buf
+ len
, "cache") + 1;
211 fdt_setprop(blob
, off
, "compatible", buf
, len
);
216 #if defined(CONFIG_L2_CACHE)
217 /* return size in kilobytes */
218 static inline u32
l2cache_size(void)
220 volatile ccsr_l2cache_t
*l2cache
= (void *)CONFIG_SYS_MPC85xx_L2_ADDR
;
221 volatile u32 l2siz_field
= (l2cache
->l2ctl
>> 28) & 0x3;
222 u32 ver
= SVR_SOC_VER(get_svr());
224 switch (l2siz_field
) {
228 if (ver
== SVR_8540
|| ver
== SVR_8560
||
229 ver
== SVR_8541
|| ver
== SVR_8555
)
235 if (ver
== SVR_8540
|| ver
== SVR_8560
||
236 ver
== SVR_8541
|| ver
== SVR_8555
)
249 static inline void ft_fixup_l2cache(void *blob
)
254 const u32 line_size
= 32;
255 const u32 num_ways
= 8;
256 const u32 size
= l2cache_size() * 1024;
257 const u32 num_sets
= size
/ (line_size
* num_ways
);
259 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
261 debug("no cpu node fount\n");
265 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
268 debug("no next-level-cache property\n");
272 off
= fdt_node_offset_by_phandle(blob
, *ph
);
274 printf("%s: %s\n", __func__
, fdt_strerror(off
));
278 ft_fixup_l2cache_compatible(blob
, off
);
279 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
280 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
281 fdt_setprop_cell(blob
, off
, "cache-size", size
);
282 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
283 fdt_setprop_cell(blob
, off
, "cache-level", 2);
285 /* we dont bother w/L3 since no platform of this type has one */
287 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
288 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
289 static inline void ft_fixup_l2cache(void *blob
)
291 int off
, l2_off
, l3_off
= -1;
293 #ifdef CONFIG_BACKSIDE_L2_CACHE
294 u32 l2cfg0
= mfspr(SPRN_L2CFG0
);
296 struct ccsr_cluster_l2
*l2cache
=
297 (struct ccsr_cluster_l2 __iomem
*)(CONFIG_SYS_FSL_CLUSTER_1_L2
);
298 u32 l2cfg0
= in_be32(&l2cache
->l2cfg0
);
300 u32 size
, line_size
, num_ways
, num_sets
;
303 /* P2040/P2040E has no L2, so dont set any L2 props */
304 if (SVR_SOC_VER(get_svr()) == SVR_P2040
)
307 size
= (l2cfg0
& 0x3fff) * 64 * 1024;
308 num_ways
= ((l2cfg0
>> 14) & 0x1f) + 1;
309 line_size
= (((l2cfg0
>> 23) & 0x3) + 1) * 32;
310 num_sets
= size
/ (line_size
* num_ways
);
312 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
314 while (off
!= -FDT_ERR_NOTFOUND
) {
315 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
318 debug("no next-level-cache property\n");
322 l2_off
= fdt_node_offset_by_phandle(blob
, *ph
);
324 printf("%s: %s\n", __func__
, fdt_strerror(off
));
329 #ifdef CONFIG_SYS_CACHE_STASHING
330 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
331 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
332 /* Only initialize every eighth thread */
333 if (reg
&& !((*reg
) % 8)) {
334 fdt_setprop_cell(blob
, l2_off
, "cache-stash-id",
335 (*reg
/ 4) + 32 + 1);
339 fdt_setprop_cell(blob
, l2_off
, "cache-stash-id",
340 (*reg
* 2) + 32 + 1);
345 fdt_setprop(blob
, l2_off
, "cache-unified", NULL
, 0);
346 fdt_setprop_cell(blob
, l2_off
, "cache-block-size",
348 fdt_setprop_cell(blob
, l2_off
, "cache-size", size
);
349 fdt_setprop_cell(blob
, l2_off
, "cache-sets", num_sets
);
350 fdt_setprop_cell(blob
, l2_off
, "cache-level", 2);
351 ft_fixup_l2cache_compatible(blob
, l2_off
);
355 ph
= (u32
*)fdt_getprop(blob
, l2_off
, "next-level-cache", 0);
358 debug("no next-level-cache property\n");
364 off
= fdt_node_offset_by_prop_value(blob
, off
,
365 "device_type", "cpu", 4);
368 l3_off
= fdt_node_offset_by_phandle(blob
, l3_off
);
370 printf("%s: %s\n", __func__
, fdt_strerror(off
));
373 ft_fixup_l3cache(blob
, l3_off
);
377 #define ft_fixup_l2cache(x)
380 static inline void ft_fixup_cache(void *blob
)
384 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
386 while (off
!= -FDT_ERR_NOTFOUND
) {
387 u32 l1cfg0
= mfspr(SPRN_L1CFG0
);
388 u32 l1cfg1
= mfspr(SPRN_L1CFG1
);
389 u32 isize
, iline_size
, inum_sets
, inum_ways
;
390 u32 dsize
, dline_size
, dnum_sets
, dnum_ways
;
393 dsize
= (l1cfg0
& 0x7ff) * 1024;
394 dnum_ways
= ((l1cfg0
>> 11) & 0xff) + 1;
395 dline_size
= (((l1cfg0
>> 23) & 0x3) + 1) * 32;
396 dnum_sets
= dsize
/ (dline_size
* dnum_ways
);
398 fdt_setprop_cell(blob
, off
, "d-cache-block-size", dline_size
);
399 fdt_setprop_cell(blob
, off
, "d-cache-size", dsize
);
400 fdt_setprop_cell(blob
, off
, "d-cache-sets", dnum_sets
);
402 #ifdef CONFIG_SYS_CACHE_STASHING
404 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
406 fdt_setprop_cell(blob
, off
, "cache-stash-id",
407 (*reg
* 2) + 32 + 0);
412 isize
= (l1cfg1
& 0x7ff) * 1024;
413 inum_ways
= ((l1cfg1
>> 11) & 0xff) + 1;
414 iline_size
= (((l1cfg1
>> 23) & 0x3) + 1) * 32;
415 inum_sets
= isize
/ (iline_size
* inum_ways
);
417 fdt_setprop_cell(blob
, off
, "i-cache-block-size", iline_size
);
418 fdt_setprop_cell(blob
, off
, "i-cache-size", isize
);
419 fdt_setprop_cell(blob
, off
, "i-cache-sets", inum_sets
);
421 off
= fdt_node_offset_by_prop_value(blob
, off
,
422 "device_type", "cpu", 4);
425 ft_fixup_l2cache(blob
);
429 void fdt_add_enet_stashing(void *fdt
)
431 do_fixup_by_compat(fdt
, "gianfar", "bd-stash", NULL
, 0, 1);
433 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-len", 96, 1);
435 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-idx", 0, 1);
436 do_fixup_by_compat(fdt
, "fsl,etsec2", "bd-stash", NULL
, 0, 1);
437 do_fixup_by_compat_u32(fdt
, "fsl,etsec2", "rx-stash-len", 96, 1);
438 do_fixup_by_compat_u32(fdt
, "fsl,etsec2", "rx-stash-idx", 0, 1);
441 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
442 #ifdef CONFIG_SYS_DPAA_FMAN
443 static void ft_fixup_clks(void *blob
, const char *compat
, u32 offset
,
446 phys_addr_t phys
= offset
+ CONFIG_SYS_CCSRBAR_PHYS
;
447 int off
= fdt_node_offset_by_compat_reg(blob
, compat
, phys
);
450 off
= fdt_setprop_cell(blob
, off
, "clock-frequency", freq
);
452 printf("WARNING enable to set clock-frequency "
453 "for %s: %s\n", compat
, fdt_strerror(off
));
458 static void ft_fixup_dpaa_clks(void *blob
)
462 get_sys_info(&sysinfo
);
463 #ifdef CONFIG_SYS_DPAA_FMAN
464 ft_fixup_clks(blob
, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET
,
465 sysinfo
.freq_fman
[0]);
467 #if (CONFIG_SYS_NUM_FMAN == 2)
468 ft_fixup_clks(blob
, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET
,
469 sysinfo
.freq_fman
[1]);
473 #ifdef CONFIG_SYS_DPAA_QBMAN
474 do_fixup_by_compat_u32(blob
, "fsl,qman",
475 "clock-frequency", sysinfo
.freq_qman
, 1);
478 #ifdef CONFIG_SYS_DPAA_PME
479 do_fixup_by_compat_u32(blob
, "fsl,pme",
480 "clock-frequency", sysinfo
.freq_pme
, 1);
484 #define ft_fixup_dpaa_clks(x)
488 static void ft_fixup_qe_snum(void *blob
)
492 svr
= mfspr(SPRN_SVR
);
493 if (SVR_SOC_VER(svr
) == SVR_8569
) {
494 if(IS_SVR_REV(svr
, 1, 0))
495 do_fixup_by_compat_u32(blob
, "fsl,qe",
496 "fsl,qe-num-snums", 46, 1);
498 do_fixup_by_compat_u32(blob
, "fsl,qe",
499 "fsl,qe-num-snums", 76, 1);
504 #if defined(CONFIG_ARCH_P4080)
505 static void fdt_fixup_usb(void *fdt
)
507 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
508 u32 rcwsr11
= in_be32(&gur
->rcwsr
[11]);
511 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,mpc85xx-usb2-mph");
512 if ((rcwsr11
& FSL_CORENET_RCWSR11_EC1
) !=
513 FSL_CORENET_RCWSR11_EC1_FM1_USB1
)
514 fdt_status_disabled(fdt
, off
);
516 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,mpc85xx-usb2-dr");
517 if ((rcwsr11
& FSL_CORENET_RCWSR11_EC2
) !=
518 FSL_CORENET_RCWSR11_EC2_USB2
)
519 fdt_status_disabled(fdt
, off
);
522 #define fdt_fixup_usb(x)
525 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
526 defined(CONFIG_ARCH_T4160)
527 void fdt_fixup_dma3(void *blob
)
529 /* the 3rd DMA is not functional if SRIO2 is chosen */
531 ccsr_gur_t __iomem
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
533 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
534 #if defined(CONFIG_ARCH_T2080)
535 u32 srds_prtcl_s2
= in_be32(&gur
->rcwsr
[4]) &
536 FSL_CORENET2_RCWSR4_SRDS2_PRTCL
;
537 srds_prtcl_s2
>>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT
;
539 switch (srds_prtcl_s2
) {
543 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
544 u32 srds_prtcl_s4
= in_be32(&gur
->rcwsr
[4]) &
545 FSL_CORENET2_RCWSR4_SRDS4_PRTCL
;
546 srds_prtcl_s4
>>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT
;
548 switch (srds_prtcl_s4
) {
554 nodeoff
= fdt_node_offset_by_compat_reg(blob
, "fsl,elo3-dma",
555 CONFIG_SYS_ELO3_DMA3
);
557 fdt_status_disabled(blob
, nodeoff
);
559 printf("WARNING: unable to disable dma3\n");
566 #define fdt_fixup_dma3(x)
569 #if defined(CONFIG_ARCH_T1040)
570 static void fdt_fixup_l2_switch(void *blob
)
575 /* The l2switch node from device-tree has
576 * compatible string "vitesse-9953" */
577 node
= fdt_node_offset_by_compatible(blob
, -1, "vitesse-9953");
578 if (node
== -FDT_ERR_NOTFOUND
)
579 /* no l2switch node has been found */
582 /* Get MAC address for the l2switch from "l2switchaddr"*/
583 if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr
)) {
584 printf("Warning: MAC address for l2switch not found\n");
585 memset(l2swaddr
, 0, sizeof(l2swaddr
));
588 /* Add MAC address to l2switch node */
589 fdt_setprop(blob
, node
, "local-mac-address", l2swaddr
,
593 #define fdt_fixup_l2_switch(x)
596 void ft_cpu_setup(void *blob
, bd_t
*bd
)
603 /* delete crypto node if not on an E-processor */
604 if (!IS_E_PROCESSOR(get_svr()))
605 fdt_fixup_crypto_node(blob
, 0);
606 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
608 ccsr_sec_t __iomem
*sec
;
610 sec
= (void __iomem
*)CONFIG_SYS_FSL_SEC_ADDR
;
611 fdt_fixup_crypto_node(blob
, sec_in32(&sec
->secvid_ms
));
615 fdt_add_enet_stashing(blob
);
617 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
618 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
620 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
621 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV
,
623 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
624 "bus-frequency", bd
->bi_busfreq
, 1);
625 get_sys_info(&sysinfo
);
626 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
627 while (off
!= -FDT_ERR_NOTFOUND
) {
628 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", &len
);
629 val
= cpu_to_fdt32(sysinfo
.freq_processor
[(*reg
) / (len
/ 4)]);
630 fdt_setprop(blob
, off
, "clock-frequency", &val
, 4);
631 off
= fdt_node_offset_by_prop_value(blob
, off
, "device_type",
634 do_fixup_by_prop_u32(blob
, "device_type", "soc", 4,
635 "bus-frequency", bd
->bi_busfreq
, 1);
639 ft_fixup_qe_snum(blob
);
642 #ifdef CONFIG_SYS_DPAA_FMAN
643 fdt_fixup_fman_firmware(blob
);
646 #ifdef CONFIG_SYS_NS16550
647 do_fixup_by_compat_u32(blob
, "ns16550",
648 "clock-frequency", CONFIG_SYS_NS16550_CLK
, 1);
652 do_fixup_by_compat_u32(blob
, "fsl,cpm2-scc-uart",
653 "current-speed", gd
->baudrate
, 1);
655 do_fixup_by_compat_u32(blob
, "fsl,cpm2-brg",
656 "clock-frequency", bd
->bi_brgfreq
, 1);
659 #ifdef CONFIG_FSL_CORENET
660 do_fixup_by_compat_u32(blob
, "fsl,qoriq-clockgen-1.0",
661 "clock-frequency", CONFIG_SYS_CLK_FREQ
, 1);
662 do_fixup_by_compat_u32(blob
, "fsl,qoriq-clockgen-2.0",
663 "clock-frequency", CONFIG_SYS_CLK_FREQ
, 1);
664 do_fixup_by_compat_u32(blob
, "fsl,mpic",
665 "clock-frequency", get_bus_freq(0)/2, 1);
667 do_fixup_by_compat_u32(blob
, "fsl,mpic",
668 "clock-frequency", get_bus_freq(0), 1);
671 fdt_fixup_memory(blob
, (u64
)bd
->bi_memstart
, (u64
)bd
->bi_memsize
);
674 ft_fixup_cpu(blob
, (u64
)bd
->bi_memstart
+ (u64
)bd
->bi_memsize
);
675 ft_fixup_num_cores(blob
);
678 ft_fixup_cache(blob
);
680 #if defined(CONFIG_FSL_ESDHC)
681 fdt_fixup_esdhc(blob
, bd
);
684 ft_fixup_dpaa_clks(blob
);
686 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
687 fdt_portal(blob
, "fsl,bman-portal", "bman-portals",
688 (u64
)CONFIG_SYS_BMAN_MEM_PHYS
,
689 CONFIG_SYS_BMAN_MEM_SIZE
);
690 fdt_fixup_bportals(blob
);
693 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
694 fdt_portal(blob
, "fsl,qman-portal", "qman-portals",
695 (u64
)CONFIG_SYS_QMAN_MEM_PHYS
,
696 CONFIG_SYS_QMAN_MEM_SIZE
);
698 fdt_fixup_qportals(blob
);
701 #ifdef CONFIG_SYS_SRIO
706 * system-clock = CCB clock/2
707 * Here gd->bus_clk = CCB clock
708 * We are using the system clock as 1588 Timer reference
709 * clock source select
711 do_fixup_by_compat_u32(blob
, "fsl,gianfar-ptp-timer",
712 "timer-frequency", gd
->bus_clk
/2, 1);
715 * clock-freq should change to clock-frequency and
716 * flexcan-v1.0 should change to p1010-flexcan respectively
719 do_fixup_by_compat_u32(blob
, "fsl,flexcan-v1.0",
720 "clock_freq", gd
->bus_clk
/2, 1);
722 do_fixup_by_compat_u32(blob
, "fsl,flexcan-v1.0",
723 "clock-frequency", gd
->bus_clk
/2, 1);
725 do_fixup_by_compat_u32(blob
, "fsl,p1010-flexcan",
726 "clock-frequency", gd
->bus_clk
/2, 1);
730 fdt_fixup_l2_switch(blob
);
732 fdt_fixup_dma3(blob
);
736 * For some CCSR devices, we only have the virtual address, not the physical
737 * address. This is because we map CCSR as a whole, so we typically don't need
738 * a macro for the physical address of any device within CCSR. In this case,
739 * we calculate the physical address of that device using it's the difference
740 * between the virtual address of the device and the virtual address of the
743 #define CCSR_VIRT_TO_PHYS(x) \
744 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
746 static void msg(const char *name
, uint64_t uaddr
, uint64_t daddr
)
748 printf("Warning: U-Boot configured %s at address %llx,\n"
749 "but the device tree has it at %llx\n", name
, uaddr
, daddr
);
753 * Verify the device tree
755 * This function compares several CONFIG_xxx macros that contain physical
756 * addresses with the corresponding nodes in the device tree, to see if
757 * the physical addresses are all correct. For example, if
758 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
759 * of the first UART. We convert this to a physical address and compare
760 * that with the physical address of the first ns16550-compatible node
761 * in the device tree. If they don't match, then we display a warning.
763 * Returns 1 on success, 0 on failure
765 int ft_verify_fdt(void *fdt
)
771 /* First check the CCSR base address */
772 off
= fdt_node_offset_by_prop_value(fdt
, -1, "device_type", "soc", 4);
774 addr
= fdt_get_base_address(fdt
, off
);
777 printf("Warning: could not determine base CCSR address in "
779 /* No point in checking anything else */
783 if (addr
!= CONFIG_SYS_CCSRBAR_PHYS
) {
784 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS
, addr
);
785 /* No point in checking anything else */
790 * Check some nodes via aliases. We assume that U-Boot and the device
791 * tree enumerate the devices equally. E.g. the first serial port in
792 * U-Boot is the same as "serial0" in the device tree.
794 aliases
= fdt_path_offset(fdt
, "/aliases");
796 #ifdef CONFIG_SYS_NS16550_COM1
797 if (!fdt_verify_alias_address(fdt
, aliases
, "serial0",
798 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1
)))
802 #ifdef CONFIG_SYS_NS16550_COM2
803 if (!fdt_verify_alias_address(fdt
, aliases
, "serial1",
804 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2
)))
810 * The localbus node is typically a root node, even though the lbc
811 * controller is part of CCSR. If we were to put the lbc node under
812 * the SOC node, then the 'ranges' property in the lbc node would
813 * translate through the 'ranges' property of the parent SOC node, and
814 * we don't want that. Since it's a separate node, it's possible for
815 * the 'reg' property to be wrong, so check it here. For now, we
816 * only check for "fsl,elbc" nodes.
818 #ifdef CONFIG_SYS_LBC_ADDR
819 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,elbc");
821 const fdt32_t
*reg
= fdt_getprop(fdt
, off
, "reg", NULL
);
823 uint64_t uaddr
= CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR
);
825 addr
= fdt_translate_address(fdt
, off
, reg
);
827 msg("the localbus", uaddr
, addr
);
837 void fdt_del_diu(void *blob
)
841 while ((nodeoff
= fdt_node_offset_by_compatible(blob
, 0,
843 fdt_del_node(blob
, nodeoff
);