2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
11 #include <asm/fsl_serdes.h>
12 #include <asm/immap_85xx.h>
14 #include <asm/processor.h>
15 #include <asm/fsl_law.h>
16 #include <linux/errno.h>
17 #include "fsl_corenet_serdes.h"
20 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
21 * The code is already very complicated as it is, and separating the two
22 * completely would just make things worse. We try to keep them as separate
23 * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
25 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
26 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
27 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
31 static u32 serdes_prtcl_map
;
34 static const char *serdes_prtcl_str
[] = {
44 [SGMII_FM1_DTSEC1
] = "SGMII_FM1_DTSEC1",
45 [SGMII_FM1_DTSEC2
] = "SGMII_FM1_DTSEC2",
46 [SGMII_FM1_DTSEC3
] = "SGMII_FM1_DTSEC3",
47 [SGMII_FM1_DTSEC4
] = "SGMII_FM1_DTSEC4",
48 [SGMII_FM1_DTSEC5
] = "SGMII_FM1_DTSEC5",
49 [SGMII_FM2_DTSEC1
] = "SGMII_FM2_DTSEC1",
50 [SGMII_FM2_DTSEC2
] = "SGMII_FM2_DTSEC2",
51 [SGMII_FM2_DTSEC3
] = "SGMII_FM2_DTSEC3",
52 [SGMII_FM2_DTSEC4
] = "SGMII_FM2_DTSEC4",
53 [SGMII_FM2_DTSEC5
] = "SGMII_FM2_DTSEC5",
54 [XAUI_FM1
] = "XAUI_FM1",
55 [XAUI_FM2
] = "XAUI_FM2",
62 unsigned int lpd
; /* RCW lane powerdown bit */
64 } lanes
[SRDS_MAX_LANES
] = {
65 { 0, 152, FSL_SRDS_BANK_1
},
66 { 1, 153, FSL_SRDS_BANK_1
},
67 { 2, 154, FSL_SRDS_BANK_1
},
68 { 3, 155, FSL_SRDS_BANK_1
},
69 { 4, 156, FSL_SRDS_BANK_1
},
70 { 5, 157, FSL_SRDS_BANK_1
},
71 { 6, 158, FSL_SRDS_BANK_1
},
72 { 7, 159, FSL_SRDS_BANK_1
},
73 { 8, 160, FSL_SRDS_BANK_1
},
74 { 9, 161, FSL_SRDS_BANK_1
},
75 { 16, 162, FSL_SRDS_BANK_2
},
76 { 17, 163, FSL_SRDS_BANK_2
},
77 { 18, 164, FSL_SRDS_BANK_2
},
78 { 19, 165, FSL_SRDS_BANK_2
},
79 #ifdef CONFIG_ARCH_P4080
80 { 20, 170, FSL_SRDS_BANK_3
},
81 { 21, 171, FSL_SRDS_BANK_3
},
82 { 22, 172, FSL_SRDS_BANK_3
},
83 { 23, 173, FSL_SRDS_BANK_3
},
85 { 20, 166, FSL_SRDS_BANK_3
},
86 { 21, 167, FSL_SRDS_BANK_3
},
87 { 22, 168, FSL_SRDS_BANK_3
},
88 { 23, 169, FSL_SRDS_BANK_3
},
91 { 24, 175, FSL_SRDS_BANK_4
},
92 { 25, 176, FSL_SRDS_BANK_4
},
96 int serdes_get_lane_idx(int lane
)
98 return lanes
[lane
].idx
;
101 int serdes_get_bank_by_lane(int lane
)
103 return lanes
[lane
].bank
;
106 int serdes_lane_enabled(int lane
)
108 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
109 serdes_corenet_t
*regs
= (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
111 int bank
= lanes
[lane
].bank
;
112 int word
= lanes
[lane
].lpd
/ 32;
113 int bit
= lanes
[lane
].lpd
% 32;
115 if (in_be32(®s
->bank
[bank
].rstctl
) & SRDS_RSTCTL_SDPD
)
118 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
120 * For banks two and three, use the srds_lpd_b[] array instead of the
121 * RCW, because this array contains the real values of SRDS_LPD_B2 and
125 return !(srds_lpd_b
[bank
] & (8 >> (lane
- (6 + 4 * bank
))));
128 return !(in_be32(&gur
->rcwsr
[word
]) & (0x80000000 >> bit
));
131 int is_serdes_configured(enum srds_prtcl device
)
133 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
135 /* Is serdes enabled at all? */
136 if (!(in_be32(&gur
->rcwsr
[5]) & FSL_CORENET_RCWSR5_SRDS_EN
))
139 if (!(serdes_prtcl_map
& (1 << NONE
)))
142 return (1 << device
) & serdes_prtcl_map
;
145 static int __serdes_get_first_lane(uint32_t prtcl
, enum srds_prtcl device
)
149 for (i
= 0; i
< SRDS_MAX_LANES
; i
++) {
150 if (serdes_get_prtcl(prtcl
, i
) == device
)
158 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
159 * device. This depends on the current SERDES protocol, as defined in the RCW.
161 * Returns a negative error code if SERDES is disabled or the given device is
162 * not supported in the current SERDES protocol.
164 int serdes_get_first_lane(enum srds_prtcl device
)
167 const ccsr_gur_t
*gur
;
169 gur
= (typeof(gur
))CONFIG_SYS_MPC85xx_GUTS_ADDR
;
171 /* Is serdes enabled at all? */
172 if (unlikely((in_be32(&gur
->rcwsr
[5]) & 0x2000) == 0))
175 prtcl
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
177 return __serdes_get_first_lane(prtcl
, device
);
180 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
182 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
185 * Returns a negative error code if the given device is not supported for the
186 * given SERDES protocol.
188 static int serdes_get_bank_by_device(uint32_t prtcl
, enum srds_prtcl device
)
192 lane
= __serdes_get_first_lane(prtcl
, device
);
193 if (unlikely(lane
< 0))
196 return serdes_get_bank_by_lane(lane
);
199 static uint32_t __serdes_get_lane_count(uint32_t prtcl
, enum srds_prtcl device
,
204 for (lane
= first
; lane
< SRDS_MAX_LANES
; lane
++) {
205 if (serdes_get_prtcl(prtcl
, lane
) != device
)
212 static void __serdes_reset_rx(serdes_corenet_t
*regs
,
214 enum srds_prtcl device
)
216 int lane
, idx
, first
, last
;
218 lane
= __serdes_get_first_lane(prtcl
, device
);
219 if (unlikely(lane
< 0))
221 first
= serdes_get_lane_idx(lane
);
222 last
= first
+ __serdes_get_lane_count(prtcl
, device
, lane
);
225 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
226 * selected as XAUI to place the lane into reset.
228 for (idx
= first
; idx
< last
; idx
++)
229 clrbits_be32(®s
->lane
[idx
].gcr0
, SRDS_GCR0_RRST
);
231 /* Wait at least 250 ns */
235 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
236 * selected as XAUI to bring the lane out of reset.
238 for (idx
= first
; idx
< last
; idx
++)
239 setbits_be32(®s
->lane
[idx
].gcr0
, SRDS_GCR0_RRST
);
242 void serdes_reset_rx(enum srds_prtcl device
)
245 const ccsr_gur_t
*gur
;
246 serdes_corenet_t
*regs
;
248 if (unlikely(device
== NONE
))
251 gur
= (typeof(gur
))CONFIG_SYS_MPC85xx_GUTS_ADDR
;
253 /* Is serdes enabled at all? */
254 if (unlikely((in_be32(&gur
->rcwsr
[5]) & 0x2000) == 0))
257 regs
= (typeof(regs
))CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
258 prtcl
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
260 __serdes_reset_rx(regs
, prtcl
, device
);
264 #ifndef CONFIG_SYS_DCSRBAR_PHYS
265 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
266 #define CONFIG_SYS_DCSRBAR 0x80000000
267 #define __DCSR_NOT_DEFINED_BY_CONFIG
270 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
272 * Enable a SERDES bank that was disabled via the RCW
274 * We only call this function for SERDES8 and SERDES-A001 in cases we really
275 * want to enable the bank, whether we actually want to use the lanes or not,
276 * so make sure at least one lane is enabled. We're only enabling this one
277 * lane to satisfy errata requirements that the bank be enabled.
279 * We use a local variable instead of srds_lpd_b[] because we want drivers to
280 * think that the lanes actually are disabled.
282 static void enable_bank(ccsr_gur_t
*gur
, int bank
)
285 u32 temp_lpd_b
= srds_lpd_b
[bank
];
288 * If we're asked to disable all lanes, just pretend we're doing
291 if (temp_lpd_b
== 0xF)
295 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
296 * CCSR, and read/write in DSCR.
298 rcw5
= in_be32(gur
->rcwsr
+ 5);
299 if (bank
== FSL_SRDS_BANK_2
) {
300 rcw5
&= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2
;
301 rcw5
|= temp_lpd_b
<< 26;
302 } else if (bank
== FSL_SRDS_BANK_3
) {
303 rcw5
&= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3
;
304 rcw5
|= temp_lpd_b
<< 18;
306 printf("SERDES: enable_bank: bad bank %d\n", bank
+ 1);
310 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
311 * of the DCSR mapping.
314 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
315 struct law_entry law
= find_law(CONFIG_SYS_DCSRBAR_PHYS
);
318 law_index
= set_next_law(CONFIG_SYS_DCSRBAR_PHYS
,
319 LAW_SIZE_1M
, LAW_TRGT_IF_DCSR
);
321 set_law(law
.index
, CONFIG_SYS_DCSRBAR_PHYS
, LAW_SIZE_1M
,
324 u32
*p
= (void *)CONFIG_SYS_DCSRBAR
+ 0x20114;
326 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
328 disable_law(law_index
);
330 set_law(law
.index
, law
.addr
, law
.size
, law
.trgt_id
);
336 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
337 * bank 3 to clock banks 2 and 3, as well as a limited selection of
338 * protocol configurations. This requires that banks 2 and 3's lanes be
339 * disabled in the RCW, and enabled with some fixup here to re-enable
340 * them, and to configure bank 2's clock parameters in bank 3's pll in
341 * cases where they differ.
343 static void p4080_erratum_serdes8(serdes_corenet_t
*regs
, ccsr_gur_t
*gur
,
344 u32 devdisr
, u32 devdisr2
, int cfg
)
350 * The disabled lanes of bank 2 will cause the associated
351 * logic blocks to be disabled in DEVDISR. We reverse that here.
353 * Note that normally it is not permitted to clear DEVDISR bits
354 * once the device has been disabled, but the hardware people
355 * say that this special case is OK.
357 clrbits_be32(&gur
->devdisr
, devdisr
);
358 clrbits_be32(&gur
->devdisr2
, devdisr2
);
361 * Some protocols require special handling. There are a few
362 * additional protocol configurations that can be used, which are
363 * not listed here. See app note 4065 for supported protocol
369 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
370 * SGMII on bank 3 should still be usable.
372 setbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr1
,
373 SRDS_PLLCR1_PLL_BWSEL
);
379 * Banks 2 (XAUI) and 3 (SGMII) have different clocking
380 * requirements in these configurations. Bank 3 cannot
381 * be used and should have its lanes (but not the bank
382 * itself) disabled in the RCW. We set up bank 3's pll
383 * for bank 2's needs here.
385 srds_ratio_b2
= (in_be32(&gur
->rcwsr
[4]) >> 13) & 7;
387 /* Determine refclock from XAUI ratio */
388 switch (srds_ratio_b2
) {
390 rfck_sel
= SRDS_PLLCR0_RFCK_SEL_156_25
;
393 rfck_sel
= SRDS_PLLCR0_RFCK_SEL_125
;
396 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
401 clrsetbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr0
,
402 SRDS_PLLCR0_RFCK_SEL_MASK
, rfck_sel
);
404 clrsetbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr0
,
405 SRDS_PLLCR0_FRATE_SEL_MASK
,
406 SRDS_PLLCR0_FRATE_SEL_6_25
);
410 enable_bank(gur
, FSL_SRDS_BANK_3
);
414 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
416 * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
417 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
419 static void p4080_erratum_serdes_a005(serdes_corenet_t
*regs
, unsigned int cfg
)
421 enum srds_prtcl device
;
427 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
430 clrbits_be32(®s
->bank
[FSL_SRDS_BANK_1
].pllcr1
,
431 SRDS_PLLCR1_PLL_BWSEL
);
435 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
436 * SRDSB3PLLCR1[PLLBW_SEL] to 1.
438 clrbits_be32(®s
->bank
[FSL_SRDS_BANK_1
].pllcr1
,
439 SRDS_PLLCR1_PLL_BWSEL
);
440 setbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr1
,
441 SRDS_PLLCR1_PLL_BWSEL
);
446 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
447 * before XAUI is initialized.
449 for (device
= XAUI_FM1
; device
<= XAUI_FM2
; device
++) {
450 if (is_serdes_configured(device
)) {
451 int bank
= serdes_get_bank_by_device(cfg
, device
);
453 clrbits_be32(®s
->bank
[bank
].pllcr1
,
454 SRDS_PLLCR1_PLL_BWSEL
);
461 * Wait for the RSTDONE bit to get set, or a one-second timeout.
463 static void wait_for_rstdone(unsigned int bank
)
465 serdes_corenet_t
*srds_regs
=
466 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
467 unsigned long long end_tick
;
470 /* wait for reset complete or 1-second timeout */
471 end_tick
= usec2ticks(1000000) + get_ticks();
473 rstctl
= in_be32(&srds_regs
->bank
[bank
].rstctl
);
474 if (rstctl
& SRDS_RSTCTL_RSTDONE
)
476 } while (end_tick
> get_ticks());
478 if (!(rstctl
& SRDS_RSTCTL_RSTDONE
))
479 printf("SERDES: timeout resetting bank %u\n", bank
+ 1);
483 static void __soc_serdes_init(void)
485 /* Allow for SoC-specific initialization in <SOC>_serdes.c */
487 void soc_serdes_init(void) __attribute__((weak
, alias("__soc_serdes_init")));
489 void fsl_serdes_init(void)
491 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
493 serdes_corenet_t
*srds_regs
;
494 #ifdef CONFIG_PPC_P5040
495 serdes_corenet_t
*srds2_regs
;
498 int have_bank
[SRDS_MAX_BANK
] = {};
499 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
500 u32 serdes8_devdisr
= 0;
501 u32 serdes8_devdisr2
= 0;
502 char srds_lpd_opt
[16];
503 const char *srds_lpd_arg
;
506 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
507 int need_serdes_a001
; /* true == need work-around for SERDES A001 */
509 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
510 char buffer
[HWCONFIG_BUFFER_SIZE
];
514 * Extract hwconfig from environment since we have not properly setup
515 * the environment but need it for ddr config params
517 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
520 if (serdes_prtcl_map
& (1 << NONE
))
523 /* Is serdes enabled at all? */
524 if (!(in_be32(&gur
->rcwsr
[5]) & FSL_CORENET_RCWSR5_SRDS_EN
))
527 srds_regs
= (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR
);
528 cfg
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
529 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg
);
531 if (!is_serdes_prtcl_valid(cfg
)) {
532 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg
);
536 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
538 * Display a warning if banks two and three are not disabled in the RCW,
539 * since our work-around for SERDES8 depends on these banks being
540 * disabled at power-on.
542 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
543 if ((in_be32(&gur
->rcwsr
[5]) & B2_B3
) != B2_B3
) {
544 printf("Warning: SERDES8 requires banks two and "
545 "three to be disabled in the RCW\n");
549 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
550 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
551 * for a description of these options.
553 for (bank
= 1; bank
< ARRAY_SIZE(srds_lpd_b
); bank
++) {
554 sprintf(srds_lpd_opt
, "fsl_srds_lpd_b%u", bank
+ 1);
556 hwconfig_subarg_f("serdes", srds_lpd_opt
, &arglen
, buf
);
559 simple_strtoul(srds_lpd_arg
, NULL
, 0) & 0xf;
562 if ((cfg
== 0xf) || (cfg
== 0x10)) {
564 * For SERDES protocols 0xF and 0x10, force bank 3 to be
565 * disabled, because it is not supported.
567 srds_lpd_b
[FSL_SRDS_BANK_3
] = 0xF;
571 /* Look for banks with all lanes disabled, and power down the bank. */
572 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
573 enum srds_prtcl lane_prtcl
= serdes_get_prtcl(cfg
, lane
);
574 if (serdes_lane_enabled(lane
)) {
575 have_bank
[serdes_get_bank_by_lane(lane
)] = 1;
576 serdes_prtcl_map
|= (1 << lane_prtcl
);
580 #ifdef CONFIG_PPC_P5040
582 * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
583 * protocols, these lanes are routed to SATA. We use serdes_prtcl_map
584 * to decide whether a protocol is supported on a given lane, so SATA
585 * will be identified as not supported, and therefore not initialized.
586 * So for protocols which use SATA on bank4, we add SATA support in
598 serdes_prtcl_map
|= 1 << SATA1
| 1 << SATA2
;
601 srds2_regs
= (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR
;
603 /* We don't need bank 4, so power it down */
604 setbits_be32(&srds2_regs
->bank
[0].rstctl
, SRDS_RSTCTL_SDPD
);
610 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
612 * Bank two uses the clock from bank three, so if bank two is enabled,
613 * then bank three must also be enabled.
615 if (have_bank
[FSL_SRDS_BANK_2
])
616 have_bank
[FSL_SRDS_BANK_3
] = 1;
619 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
621 * The work-aroud for erratum SERDES-A001 is needed only if bank two
622 * is disabled and bank three is enabled. The converse is also true,
623 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
624 * enabled, so there's no point in complicating the code to handle
628 !have_bank
[FSL_SRDS_BANK_2
] && have_bank
[FSL_SRDS_BANK_3
];
631 /* Power down the banks we're not interested in */
632 for (bank
= 0; bank
< SRDS_MAX_BANK
; bank
++) {
633 if (!have_bank
[bank
]) {
634 printf("SERDES: bank %d disabled\n", bank
+ 1);
635 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
637 * Erratum SERDES-A001 says bank two needs to be powered
638 * down after bank three is powered up, so don't power
639 * down bank two here.
641 if (!need_serdes_a001
|| (bank
!= FSL_SRDS_BANK_2
))
642 setbits_be32(&srds_regs
->bank
[bank
].rstctl
,
645 setbits_be32(&srds_regs
->bank
[bank
].rstctl
,
651 #ifdef CONFIG_SYS_FSL_ERRATUM_A004699
653 * To avoid the situation that resulted in the P4080 erratum
654 * SERDES-8, a given SerDes bank will use the PLLs from the previous
655 * bank if one of the PLL frequencies is a multiple of the other. For
656 * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
657 * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says
658 * that, in this situation, lane synchronization is not initiated. So
659 * when we detect a bank with a "borrowed" PLL, we have to manually
660 * initiate lane synchronization.
662 for (bank
= FSL_SRDS_BANK_2
; bank
<= FSL_SRDS_BANK_3
; bank
++) {
663 /* Determine the first lane for this bank */
666 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++)
667 if (lanes
[lane
].bank
== bank
)
669 idx
= lanes
[lane
].idx
;
672 * Check if the PLL for the bank is borrowed. The UOTHL
673 * bit of the first lane will tell us that.
675 if (in_be32(&srds_regs
->lane
[idx
].gcr0
) & SRDS_GCR0_UOTHL
) {
676 /* Manually start lane synchronization */
677 setbits_be32(&srds_regs
->bank
[bank
].pllcr0
,
678 SRDS_PLLCR0_PVCOCNT_EN
);
683 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
684 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
685 enum srds_prtcl lane_prtcl
;
687 idx
= serdes_get_lane_idx(lane
);
688 lane_prtcl
= serdes_get_prtcl(cfg
, lane
);
705 printf("%s ", serdes_prtcl_str
[lane_prtcl
]);
708 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
710 * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
711 * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
712 * or AURORA before the device is initialized.
714 * Note that this part of the SERDES-9 work-around is
715 * redundant if the work-around for A-4580 has already been
718 switch (lane_prtcl
) {
719 case SGMII_FM1_DTSEC1
:
720 case SGMII_FM1_DTSEC2
:
721 case SGMII_FM1_DTSEC3
:
722 case SGMII_FM1_DTSEC4
:
723 case SGMII_FM2_DTSEC1
:
724 case SGMII_FM2_DTSEC2
:
725 case SGMII_FM2_DTSEC3
:
726 case SGMII_FM2_DTSEC4
:
727 case SGMII_FM2_DTSEC5
:
733 out_be32(&srds_regs
->lane
[idx
].ttlcr0
,
734 SRDS_TTLCR0_FLT_SEL_KFR_26
|
735 SRDS_TTLCR0_FLT_SEL_KPH_28
|
736 SRDS_TTLCR0_FLT_SEL_750PPM
|
737 SRDS_TTLCR0_FREQOVD_EN
);
744 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
745 switch (lane_prtcl
) {
749 serdes8_devdisr
|= FSL_CORENET_DEVDISR_PCIE1
>>
750 (lane_prtcl
- PCIE1
);
754 serdes8_devdisr
|= FSL_CORENET_DEVDISR_SRIO1
>>
755 (lane_prtcl
- SRIO1
);
757 case SGMII_FM1_DTSEC1
:
758 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
759 FSL_CORENET_DEVDISR2_DTSEC1_1
;
761 case SGMII_FM1_DTSEC2
:
762 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
763 FSL_CORENET_DEVDISR2_DTSEC1_2
;
765 case SGMII_FM1_DTSEC3
:
766 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
767 FSL_CORENET_DEVDISR2_DTSEC1_3
;
769 case SGMII_FM1_DTSEC4
:
770 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
771 FSL_CORENET_DEVDISR2_DTSEC1_4
;
773 case SGMII_FM2_DTSEC1
:
774 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
775 FSL_CORENET_DEVDISR2_DTSEC2_1
;
777 case SGMII_FM2_DTSEC2
:
778 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
779 FSL_CORENET_DEVDISR2_DTSEC2_2
;
781 case SGMII_FM2_DTSEC3
:
782 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
783 FSL_CORENET_DEVDISR2_DTSEC2_3
;
785 case SGMII_FM2_DTSEC4
:
786 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
787 FSL_CORENET_DEVDISR2_DTSEC2_4
;
789 case SGMII_FM2_DTSEC5
:
790 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
791 FSL_CORENET_DEVDISR2_DTSEC2_5
;
794 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
795 FSL_CORENET_DEVDISR2_10GEC1
;
798 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
799 FSL_CORENET_DEVDISR2_10GEC2
;
815 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
816 p4080_erratum_serdes_a005(srds_regs
, cfg
);
819 for (idx
= 0; idx
< SRDS_MAX_BANK
; idx
++) {
822 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
824 * Change bank init order to 0, 2, 1, so that the third bank's
825 * PLL is established before we start the second bank. The
826 * second bank uses the third bank's PLL.
830 bank
= FSL_SRDS_BANK_3
;
832 bank
= FSL_SRDS_BANK_2
;
835 /* Skip disabled banks */
836 if (!have_bank
[bank
])
839 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
842 * Re-enable devices on banks two and three that were
843 * disabled by the RCW, and then enable bank three. The
844 * devices need to be enabled before either bank is
847 p4080_erratum_serdes8(srds_regs
, gur
, serdes8_devdisr
,
848 serdes8_devdisr2
, cfg
);
849 } else if (idx
== 2) {
850 /* Enable bank two now that bank three is enabled. */
851 enable_bank(gur
, FSL_SRDS_BANK_2
);
855 wait_for_rstdone(bank
);
858 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
859 if (need_serdes_a001
) {
860 /* Bank 3 has been enabled, so now we can disable bank 2 */
861 setbits_be32(&srds_regs
->bank
[FSL_SRDS_BANK_2
].rstctl
,
866 /* Set the first bit to indicate serdes has been initialized */
867 serdes_prtcl_map
|= (1 << NONE
);
870 const char *serdes_clock_to_string(u32 clock
)
873 case SRDS_PLLCR0_RFCK_SEL_100
:
875 case SRDS_PLLCR0_RFCK_SEL_125
:
877 case SRDS_PLLCR0_RFCK_SEL_156_25
:
879 case SRDS_PLLCR0_RFCK_SEL_161_13
:
880 return "161.1328123";