arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2010 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <config.h>
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/immap_85xx.h>
  10 #include <asm/fsl_serdes.h>
  11
  12 #define SRDS1_MAX_LANES         8
  13 #define SRDS2_MAX_LANES         4
  14
  15 static u32 serdes1_prtcl_map, serdes2_prtcl_map;
  16
  17 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  18         [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  19         [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  20         [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  21         [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  22         [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  23         [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  24 };
  25
  26 static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
  27         [0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  28         [0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  29         [0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  30         [0x6] = {PCIE3, NONE, NONE, NONE},
  31         [0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
  32 };
  33
  34 int is_serdes_configured(enum srds_prtcl device)
  35 {
  36         int ret;
  37
  38         if (!(serdes1_prtcl_map & (1 << NONE)))
  39                 fsl_serdes_init();
  40
  41         ret = (1 << device) & serdes1_prtcl_map;
  42
  43         if (ret)
  44                 return ret;
  45
  46         if (!(serdes2_prtcl_map & (1 << NONE)))
  47                 fsl_serdes_init();
  48
  49         return (1 << device) & serdes2_prtcl_map;
  50 }
  51
  52 void fsl_serdes_init(void)
  53 {
  54         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  55         u32 pordevsr = in_be32(&gur->pordevsr);
  56         u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  57                                 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  58         int lane;
  59
  60         if (serdes1_prtcl_map & (1 << NONE) &&
  61             serdes2_prtcl_map & (1 << NONE))
  62                 return;
  63
  64         debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  65
  66         if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  67                 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  68                 return;
  69         }
  70         for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  71                 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  72                 serdes1_prtcl_map |= (1 << lane_prtcl);
  73         }
  74
  75         /* Set the first bit to indicate serdes has been initialized */
  76         serdes1_prtcl_map |= (1 << NONE);
  77
  78         if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
  79                 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  80                 return;
  81         }
  82
  83         for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
  84                 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
  85                 serdes2_prtcl_map |= (1 << lane_prtcl);
  86         }
  87
  88         if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
  89                 serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
  90
  91         if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
  92                 serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
  93
  94         /* Set the first bit to indicate serdes has been initialized */
  95         serdes2_prtcl_map |= (1 << NONE);
  96 }