2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <ppc_asm.tmpl>
15 #include <linux/compiler.h>
16 #include <asm/processor.h>
19 DECLARE_GLOBAL_DATA_PTR
;
22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
25 /* --------------------------------------------------------------- */
27 void get_sys_info(sys_info_t
*sys_info
)
29 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
31 struct fsl_ifc
*ifc_regs
= (void *)CONFIG_SYS_IFC_ADDR
;
34 #ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t
*clk
= (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR
);
37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
38 int cc_group
[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS
;
41 const u8 core_cplx_PLL
[16] = {
42 [ 0] = 0, /* CC1 PPL / 1 */
43 [ 1] = 0, /* CC1 PPL / 2 */
44 [ 2] = 0, /* CC1 PPL / 4 */
45 [ 4] = 1, /* CC2 PPL / 1 */
46 [ 5] = 1, /* CC2 PPL / 2 */
47 [ 6] = 1, /* CC2 PPL / 4 */
48 [ 8] = 2, /* CC3 PPL / 1 */
49 [ 9] = 2, /* CC3 PPL / 2 */
50 [10] = 2, /* CC3 PPL / 4 */
51 [12] = 3, /* CC4 PPL / 1 */
52 [13] = 3, /* CC4 PPL / 2 */
53 [14] = 3, /* CC4 PPL / 4 */
56 const u8 core_cplx_pll_div
[16] = {
57 [ 0] = 1, /* CC1 PPL / 1 */
58 [ 1] = 2, /* CC1 PPL / 2 */
59 [ 2] = 4, /* CC1 PPL / 4 */
60 [ 4] = 1, /* CC2 PPL / 1 */
61 [ 5] = 2, /* CC2 PPL / 2 */
62 [ 6] = 4, /* CC2 PPL / 4 */
63 [ 8] = 1, /* CC3 PPL / 1 */
64 [ 9] = 2, /* CC3 PPL / 2 */
65 [10] = 4, /* CC3 PPL / 4 */
66 [12] = 1, /* CC4 PPL / 1 */
67 [13] = 2, /* CC4 PPL / 2 */
68 [14] = 4, /* CC4 PPL / 4 */
70 uint i
, freq_c_pll
[CONFIG_SYS_FSL_NUM_CC_PLLS
];
71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
74 uint ratio
[CONFIG_SYS_FSL_NUM_CC_PLLS
];
75 unsigned long sysclk
= CONFIG_SYS_CLK_FREQ
;
77 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
81 sys_info
->freq_systembus
= sysclk
;
82 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
85 * are driven by separate DDR Refclock or single source
88 single_src
= (in_be32(&gur
->rcwsr
[5]) >>
89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT
) &
90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK
;
92 * For single source clocking, both ddrclock and syclock
93 * are driven by differential sysclock.
95 if (single_src
== FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK
) {
96 printf("Single Source Clock Configuration\n");
97 sys_info
->freq_ddrbus
= CONFIG_SYS_CLK_FREQ
;
100 #ifdef CONFIG_DDR_CLK_FREQ
101 sys_info
->freq_ddrbus
= CONFIG_DDR_CLK_FREQ
;
103 sys_info
->freq_ddrbus
= sysclk
;
106 sys_info
->freq_systembus
*= (in_be32(&gur
->rcwsr
[0]) >> 25) & 0x1f;
107 mem_pll_rat
= (in_be32(&gur
->rcwsr
[0]) >>
108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT
)
109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK
;
110 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
111 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
114 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
115 if (SVR_MAJ(get_svr()) >= 2)
119 sys_info
->freq_ddrbus
*= mem_pll_rat
;
121 sys_info
->freq_ddrbus
= sys_info
->freq_systembus
* mem_pll_rat
;
123 for (i
= 0; i
< CONFIG_SYS_FSL_NUM_CC_PLLS
; i
++) {
124 ratio
[i
] = (in_be32(&clk
->pllcgsr
[i
].pllcngsr
) >> 1) & 0x3f;
126 freq_c_pll
[i
] = sysclk
* ratio
[i
];
128 freq_c_pll
[i
] = sys_info
->freq_systembus
* ratio
[i
];
130 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
132 * As per CHASSIS2 architeture total 12 clusters are posible and
133 * Each cluster has up to 4 cores, sharing the same PLL selection.
134 * The cluster clock assignment is SoC defined.
136 * Total 4 clock groups are possible with 3 PLLs each.
137 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
138 * clock group B has 3, 4, 6 and so on.
140 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
141 * depends upon the SoC architeture. Same applies to other
142 * clock groups and clusters.
145 for_each_cpu(i
, cpu
, cpu_numcores(), cpu_mask()) {
146 int cluster
= fsl_qoriq_core_to_cluster(cpu
);
147 u32 c_pll_sel
= (in_be32(&clk
->clkcsr
[cluster
].clkcncsr
) >> 27)
149 u32 cplx_pll
= core_cplx_PLL
[c_pll_sel
];
150 cplx_pll
+= cc_group
[cluster
] - 1;
151 sys_info
->freq_processor
[cpu
] =
152 freq_c_pll
[cplx_pll
] / core_cplx_pll_div
[c_pll_sel
];
154 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
155 defined(CONFIG_PPC_T2081)
156 #define FM1_CLK_SEL 0xe0000000
157 #define FM1_CLK_SHIFT 29
159 #define PME_CLK_SEL 0xe0000000
160 #define PME_CLK_SHIFT 29
161 #define FM1_CLK_SEL 0x1c000000
162 #define FM1_CLK_SHIFT 26
164 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
165 rcw_tmp
= in_be32(&gur
->rcwsr
[7]);
168 #ifdef CONFIG_SYS_DPAA_PME
169 #ifndef CONFIG_PME_PLAT_CLK_DIV
170 switch ((rcw_tmp
& PME_CLK_SEL
) >> PME_CLK_SHIFT
) {
172 sys_info
->freq_pme
= freq_c_pll
[CONFIG_SYS_PME_CLK
];
175 sys_info
->freq_pme
= freq_c_pll
[CONFIG_SYS_PME_CLK
] / 2;
178 sys_info
->freq_pme
= freq_c_pll
[CONFIG_SYS_PME_CLK
] / 3;
181 sys_info
->freq_pme
= freq_c_pll
[CONFIG_SYS_PME_CLK
] / 4;
184 sys_info
->freq_pme
= freq_c_pll
[CONFIG_SYS_PME_CLK
+ 1] / 2;
187 sys_info
->freq_pme
= freq_c_pll
[CONFIG_SYS_PME_CLK
+ 1] / 3;
190 printf("Error: Unknown PME clock select!\n");
192 sys_info
->freq_pme
= sys_info
->freq_systembus
/ 2;
197 sys_info
->freq_pme
= sys_info
->freq_systembus
/ CONFIG_SYS_PME_CLK
;
202 #ifdef CONFIG_SYS_DPAA_QBMAN
203 sys_info
->freq_qman
= sys_info
->freq_systembus
/ 2;
206 #ifdef CONFIG_SYS_DPAA_FMAN
207 #ifndef CONFIG_FM_PLAT_CLK_DIV
208 switch ((rcw_tmp
& FM1_CLK_SEL
) >> FM1_CLK_SHIFT
) {
210 sys_info
->freq_fman
[0] = freq_c_pll
[CONFIG_SYS_FM1_CLK
];
213 sys_info
->freq_fman
[0] = freq_c_pll
[CONFIG_SYS_FM1_CLK
] / 2;
216 sys_info
->freq_fman
[0] = freq_c_pll
[CONFIG_SYS_FM1_CLK
] / 3;
219 sys_info
->freq_fman
[0] = freq_c_pll
[CONFIG_SYS_FM1_CLK
] / 4;
222 sys_info
->freq_fman
[0] = sys_info
->freq_systembus
;
225 sys_info
->freq_fman
[0] = freq_c_pll
[CONFIG_SYS_FM1_CLK
+ 1] / 2;
228 sys_info
->freq_fman
[0] = freq_c_pll
[CONFIG_SYS_FM1_CLK
+ 1] / 3;
231 printf("Error: Unknown FMan1 clock select!\n");
233 sys_info
->freq_fman
[0] = sys_info
->freq_systembus
/ 2;
236 #if (CONFIG_SYS_NUM_FMAN) == 2
237 #ifdef CONFIG_SYS_FM2_CLK
238 #define FM2_CLK_SEL 0x00000038
239 #define FM2_CLK_SHIFT 3
240 rcw_tmp
= in_be32(&gur
->rcwsr
[15]);
241 switch ((rcw_tmp
& FM2_CLK_SEL
) >> FM2_CLK_SHIFT
) {
243 sys_info
->freq_fman
[1] = freq_c_pll
[CONFIG_SYS_FM2_CLK
+ 1];
246 sys_info
->freq_fman
[1] = freq_c_pll
[CONFIG_SYS_FM2_CLK
+ 1] / 2;
249 sys_info
->freq_fman
[1] = freq_c_pll
[CONFIG_SYS_FM2_CLK
+ 1] / 3;
252 sys_info
->freq_fman
[1] = freq_c_pll
[CONFIG_SYS_FM2_CLK
+ 1] / 4;
255 sys_info
->freq_fman
[1] = sys_info
->freq_systembus
;
258 sys_info
->freq_fman
[1] = freq_c_pll
[CONFIG_SYS_FM2_CLK
] / 2;
261 sys_info
->freq_fman
[1] = freq_c_pll
[CONFIG_SYS_FM2_CLK
] / 3;
264 printf("Error: Unknown FMan2 clock select!\n");
266 sys_info
->freq_fman
[1] = sys_info
->freq_systembus
/ 2;
270 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
272 sys_info
->freq_fman
[0] = sys_info
->freq_systembus
/ CONFIG_SYS_FM1_CLK
;
276 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
278 for_each_cpu(i
, cpu
, cpu_numcores(), cpu_mask()) {
279 u32 c_pll_sel
= (in_be32(&clk
->clkcsr
[cpu
].clkcncsr
) >> 27)
281 u32 cplx_pll
= core_cplx_PLL
[c_pll_sel
];
283 sys_info
->freq_processor
[cpu
] =
284 freq_c_pll
[cplx_pll
] / core_cplx_pll_div
[c_pll_sel
];
286 #define PME_CLK_SEL 0x80000000
287 #define FM1_CLK_SEL 0x40000000
288 #define FM2_CLK_SEL 0x20000000
289 #define HWA_ASYNC_DIV 0x04000000
290 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
292 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
294 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
297 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
299 rcw_tmp
= in_be32(&gur
->rcwsr
[7]);
301 #ifdef CONFIG_SYS_DPAA_PME
302 if (rcw_tmp
& PME_CLK_SEL
) {
303 if (rcw_tmp
& HWA_ASYNC_DIV
)
304 sys_info
->freq_pme
= freq_c_pll
[HWA_CC_PLL
] / 4;
306 sys_info
->freq_pme
= freq_c_pll
[HWA_CC_PLL
] / 2;
308 sys_info
->freq_pme
= sys_info
->freq_systembus
/ 2;
312 #ifdef CONFIG_SYS_DPAA_FMAN
313 if (rcw_tmp
& FM1_CLK_SEL
) {
314 if (rcw_tmp
& HWA_ASYNC_DIV
)
315 sys_info
->freq_fman
[0] = freq_c_pll
[HWA_CC_PLL
] / 4;
317 sys_info
->freq_fman
[0] = freq_c_pll
[HWA_CC_PLL
] / 2;
319 sys_info
->freq_fman
[0] = sys_info
->freq_systembus
/ 2;
321 #if (CONFIG_SYS_NUM_FMAN) == 2
322 if (rcw_tmp
& FM2_CLK_SEL
) {
323 if (rcw_tmp
& HWA_ASYNC_DIV
)
324 sys_info
->freq_fman
[1] = freq_c_pll
[HWA_CC_PLL
] / 4;
326 sys_info
->freq_fman
[1] = freq_c_pll
[HWA_CC_PLL
] / 2;
328 sys_info
->freq_fman
[1] = sys_info
->freq_systembus
/ 2;
333 #ifdef CONFIG_SYS_DPAA_QBMAN
334 sys_info
->freq_qman
= sys_info
->freq_systembus
/ 2;
337 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
339 #else /* CONFIG_FSL_CORENET */
340 uint plat_ratio
, e500_ratio
, half_freq_systembus
;
343 __maybe_unused u32 qe_ratio
;
346 plat_ratio
= (gur
->porpllsr
) & 0x0000003e;
348 sys_info
->freq_systembus
= plat_ratio
* CONFIG_SYS_CLK_FREQ
;
350 /* Divide before multiply to avoid integer
351 * overflow for processor speeds above 2GHz */
352 half_freq_systembus
= sys_info
->freq_systembus
/2;
353 for (i
= 0; i
< cpu_numcores(); i
++) {
354 e500_ratio
= ((gur
->porpllsr
) >> (i
* 8 + 16)) & 0x3f;
355 sys_info
->freq_processor
[i
] = e500_ratio
* half_freq_systembus
;
358 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
359 sys_info
->freq_ddrbus
= sys_info
->freq_systembus
;
361 #ifdef CONFIG_DDR_CLK_FREQ
363 u32 ddr_ratio
= ((gur
->porpllsr
) & MPC85xx_PORPLLSR_DDR_RATIO
)
364 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT
;
365 if (ddr_ratio
!= 0x7)
366 sys_info
->freq_ddrbus
= ddr_ratio
* CONFIG_DDR_CLK_FREQ
;
371 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
372 sys_info
->freq_qe
= sys_info
->freq_systembus
;
374 qe_ratio
= ((gur
->porpllsr
) & MPC85xx_PORPLLSR_QE_RATIO
)
375 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT
;
376 sys_info
->freq_qe
= qe_ratio
* CONFIG_SYS_CLK_FREQ
;
380 #ifdef CONFIG_SYS_DPAA_FMAN
381 sys_info
->freq_fman
[0] = sys_info
->freq_systembus
;
384 #endif /* CONFIG_FSL_CORENET */
386 #if defined(CONFIG_FSL_LBC)
388 #if defined(CONFIG_SYS_LBC_LCRR)
389 /* We will program LCRR to this value later */
390 lcrr_div
= CONFIG_SYS_LBC_LCRR
& LCRR_CLKDIV
;
392 lcrr_div
= in_be32(&(LBC_BASE_ADDR
)->lcrr
) & LCRR_CLKDIV
;
394 if (lcrr_div
== 2 || lcrr_div
== 4 || lcrr_div
== 8) {
395 #if defined(CONFIG_FSL_CORENET)
396 /* If this is corenet based SoC, bit-representation
397 * for four times the clock divider values.
400 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
401 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
403 * Yes, the entire PQ38 family use the same
404 * bit-representation for twice the clock divider values.
408 sys_info
->freq_localbus
= sys_info
->freq_systembus
/ lcrr_div
;
410 /* In case anyone cares what the unknown value is */
411 sys_info
->freq_localbus
= lcrr_div
;
415 #if defined(CONFIG_FSL_IFC)
416 ccr
= in_be32(&ifc_regs
->ifc_ccr
);
417 ccr
= ((ccr
& IFC_CCR_CLK_DIV_MASK
) >> IFC_CCR_CLK_DIV_SHIFT
) + 1;
419 sys_info
->freq_localbus
= sys_info
->freq_systembus
/ ccr
;
424 int get_clocks (void)
427 #ifdef CONFIG_MPC8544
428 volatile ccsr_gur_t
*gur
= (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR
;
430 #if defined(CONFIG_CPM2)
431 volatile ccsr_cpm_t
*cpm
= (ccsr_cpm_t
*)CONFIG_SYS_MPC85xx_CPM_ADDR
;
434 /* set VCO = 4 * BRG */
435 cpm
->im_cpm_intctl
.sccr
&= 0xfffffffc;
436 sccr
= cpm
->im_cpm_intctl
.sccr
;
437 dfbrg
= (sccr
& SCCR_DFBRG_MSK
) >> SCCR_DFBRG_SHIFT
;
439 get_sys_info (&sys_info
);
440 gd
->cpu_clk
= sys_info
.freq_processor
[0];
441 gd
->bus_clk
= sys_info
.freq_systembus
;
442 gd
->mem_clk
= sys_info
.freq_ddrbus
;
443 gd
->arch
.lbc_clk
= sys_info
.freq_localbus
;
446 gd
->arch
.qe_clk
= sys_info
.freq_qe
;
447 gd
->arch
.brg_clk
= gd
->arch
.qe_clk
/ 2;
450 * The base clock for I2C depends on the actual SOC. Unfortunately,
451 * there is no pattern that can be used to determine the frequency, so
452 * the only choice is to look up the actual SOC number and use the value
453 * for that SOC. This information is taken from application note
456 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
457 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
458 defined(CONFIG_P1022)
459 gd
->arch
.i2c1_clk
= sys_info
.freq_systembus
;
460 #elif defined(CONFIG_MPC8544)
462 * On the 8544, the I2C clock is the same as the SEC clock. This can be
463 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
464 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
465 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
466 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
468 if (gur
->pordevsr2
& MPC85xx_PORDEVSR2_SEC_CFG
)
469 gd
->arch
.i2c1_clk
= sys_info
.freq_systembus
/ 3;
471 gd
->arch
.i2c1_clk
= sys_info
.freq_systembus
/ 2;
473 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
474 gd
->arch
.i2c1_clk
= sys_info
.freq_systembus
/ 2;
476 gd
->arch
.i2c2_clk
= gd
->arch
.i2c1_clk
;
478 #if defined(CONFIG_FSL_ESDHC)
479 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
480 defined(CONFIG_P1014)
481 gd
->arch
.sdhc_clk
= gd
->bus_clk
;
483 gd
->arch
.sdhc_clk
= gd
->bus_clk
/ 2;
485 #endif /* defined(CONFIG_FSL_ESDHC) */
487 #if defined(CONFIG_CPM2)
488 gd
->arch
.vco_out
= 2*sys_info
.freq_systembus
;
489 gd
->arch
.cpm_clk
= gd
->arch
.vco_out
/ 2;
490 gd
->arch
.scc_clk
= gd
->arch
.vco_out
/ 4;
491 gd
->arch
.brg_clk
= gd
->arch
.vco_out
/ (1 << (2 * (dfbrg
+ 1)));
494 if(gd
->cpu_clk
!= 0) return (0);
499 /********************************************
501 * return system bus freq in Hz
502 *********************************************/
503 ulong
get_bus_freq (ulong dummy
)
508 /********************************************
510 * return ddr bus freq in Hz
511 *********************************************/
512 ulong
get_ddr_freq (ulong dummy
)