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Merge branch 'master' of git://git.denx.de/u-boot-mips
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c
1 /*
2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13 #include <common.h>
14 #include <ppc_asm.tmpl>
15 #include <linux/compiler.h>
16 #include <asm/processor.h>
17 #include <asm/io.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21
22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24 #endif
25 /* --------------------------------------------------------------- */
26
27 void get_sys_info(sys_info_t *sys_info)
28 {
29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
30 #ifdef CONFIG_FSL_IFC
31 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
32 u32 ccr;
33 #endif
34 #ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
36 unsigned int cpu;
37 #ifdef CONFIG_HETROGENOUS_CLUSTERS
38 unsigned int dsp_cpu;
39 uint rcw_tmp1, rcw_tmp2;
40 #endif
41 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
42 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
43 #endif
44 __maybe_unused u32 svr;
45
46 const u8 core_cplx_PLL[16] = {
47 [ 0] = 0, /* CC1 PPL / 1 */
48 [ 1] = 0, /* CC1 PPL / 2 */
49 [ 2] = 0, /* CC1 PPL / 4 */
50 [ 4] = 1, /* CC2 PPL / 1 */
51 [ 5] = 1, /* CC2 PPL / 2 */
52 [ 6] = 1, /* CC2 PPL / 4 */
53 [ 8] = 2, /* CC3 PPL / 1 */
54 [ 9] = 2, /* CC3 PPL / 2 */
55 [10] = 2, /* CC3 PPL / 4 */
56 [12] = 3, /* CC4 PPL / 1 */
57 [13] = 3, /* CC4 PPL / 2 */
58 [14] = 3, /* CC4 PPL / 4 */
59 };
60
61 const u8 core_cplx_pll_div[16] = {
62 [ 0] = 1, /* CC1 PPL / 1 */
63 [ 1] = 2, /* CC1 PPL / 2 */
64 [ 2] = 4, /* CC1 PPL / 4 */
65 [ 4] = 1, /* CC2 PPL / 1 */
66 [ 5] = 2, /* CC2 PPL / 2 */
67 [ 6] = 4, /* CC2 PPL / 4 */
68 [ 8] = 1, /* CC3 PPL / 1 */
69 [ 9] = 2, /* CC3 PPL / 2 */
70 [10] = 4, /* CC3 PPL / 4 */
71 [12] = 1, /* CC4 PPL / 1 */
72 [13] = 2, /* CC4 PPL / 2 */
73 [14] = 4, /* CC4 PPL / 4 */
74 };
75 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
76 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
77 uint rcw_tmp;
78 #endif
79 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
80 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
81 uint mem_pll_rat;
82
83 sys_info->freq_systembus = sysclk;
84 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
85 uint ddr_refclk_sel;
86 unsigned int porsr1_sys_clk;
87 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
88 & FSL_DCFG_PORSR1_SYSCLK_MASK;
89 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
90 sys_info->diff_sysclk = 1;
91 else
92 sys_info->diff_sysclk = 0;
93
94 /*
95 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
96 * are driven by separate DDR Refclock or single source
97 * differential clock.
98 */
99 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
100 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
101 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
102 /*
103 * For single source clocking, both ddrclock and sysclock
104 * are driven by differential sysclock.
105 */
106 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
107 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
108 else
109 #endif
110 #ifdef CONFIG_DDR_CLK_FREQ
111 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
112 #else
113 sys_info->freq_ddrbus = sysclk;
114 #endif
115
116 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
117 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
118 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
119 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
120 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
121 if (mem_pll_rat == 0) {
122 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
123 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
124 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
125 }
126 #endif
127 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
128 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
129 * it uses 6.
130 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
131 */
132 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
133 defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
134 svr = get_svr();
135 switch (SVR_SOC_VER(svr)) {
136 case SVR_T4240:
137 case SVR_T4160:
138 case SVR_T4120:
139 case SVR_T4080:
140 if (SVR_MAJ(svr) >= 2)
141 mem_pll_rat *= 2;
142 break;
143 case SVR_T2080:
144 case SVR_T2081:
145 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
146 mem_pll_rat *= 2;
147 break;
148 default:
149 break;
150 }
151 #endif
152 if (mem_pll_rat > 2)
153 sys_info->freq_ddrbus *= mem_pll_rat;
154 else
155 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
156
157 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
158 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
159 if (ratio[i] > 4)
160 freq_c_pll[i] = sysclk * ratio[i];
161 else
162 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
163 }
164
165 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
166 /*
167 * As per CHASSIS2 architeture total 12 clusters are posible and
168 * Each cluster has up to 4 cores, sharing the same PLL selection.
169 * The cluster clock assignment is SoC defined.
170 *
171 * Total 4 clock groups are possible with 3 PLLs each.
172 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
173 * clock group B has 3, 4, 6 and so on.
174 *
175 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
176 * depends upon the SoC architeture. Same applies to other
177 * clock groups and clusters.
178 *
179 */
180 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
181 int cluster = fsl_qoriq_core_to_cluster(cpu);
182 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
183 & 0xf;
184 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
185 cplx_pll += cc_group[cluster] - 1;
186 sys_info->freq_processor[cpu] =
187 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
188 }
189
190 #ifdef CONFIG_HETROGENOUS_CLUSTERS
191 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
192 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
193 u32 c_pll_sel = (in_be32
194 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
195 & 0xf;
196 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
197 cplx_pll += cc_group[dsp_cluster] - 1;
198 sys_info->freq_processor_dsp[dsp_cpu] =
199 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
200 }
201 #endif
202
203 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
204 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
205 #define FM1_CLK_SEL 0xe0000000
206 #define FM1_CLK_SHIFT 29
207 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
208 #define FM1_CLK_SEL 0x00000007
209 #define FM1_CLK_SHIFT 0
210 #else
211 #define PME_CLK_SEL 0xe0000000
212 #define PME_CLK_SHIFT 29
213 #define FM1_CLK_SEL 0x1c000000
214 #define FM1_CLK_SHIFT 26
215 #endif
216 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
217 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
218 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
219 #else
220 rcw_tmp = in_be32(&gur->rcwsr[7]);
221 #endif
222 #endif
223
224 #ifdef CONFIG_SYS_DPAA_PME
225 #ifndef CONFIG_PME_PLAT_CLK_DIV
226 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
227 case 1:
228 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
229 break;
230 case 2:
231 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
232 break;
233 case 3:
234 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
235 break;
236 case 4:
237 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
238 break;
239 case 6:
240 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
241 break;
242 case 7:
243 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
244 break;
245 default:
246 printf("Error: Unknown PME clock select!\n");
247 case 0:
248 sys_info->freq_pme = sys_info->freq_systembus / 2;
249 break;
250
251 }
252 #else
253 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
254
255 #endif
256 #endif
257
258 #ifdef CONFIG_SYS_DPAA_QBMAN
259 #ifndef CONFIG_QBMAN_CLK_DIV
260 #define CONFIG_QBMAN_CLK_DIV 2
261 #endif
262 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
263 #endif
264
265 #if defined(CONFIG_SYS_MAPLE)
266 #define CPRI_CLK_SEL 0x1C000000
267 #define CPRI_CLK_SHIFT 26
268 #define CPRI_ALT_CLK_SEL 0x00007000
269 #define CPRI_ALT_CLK_SHIFT 12
270
271 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
272 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
273 /* For MAPLE and CPRI frequency */
274 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
275 case 1:
276 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
277 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
278 break;
279 case 2:
280 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
281 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
282 break;
283 case 3:
284 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
285 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
286 break;
287 case 4:
288 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
289 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
290 break;
291 case 5:
292 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
293 >> CPRI_ALT_CLK_SHIFT) == 6) {
294 sys_info->freq_maple =
295 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
296 sys_info->freq_cpri =
297 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
298 }
299 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
300 >> CPRI_ALT_CLK_SHIFT) == 7) {
301 sys_info->freq_maple =
302 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
303 sys_info->freq_cpri =
304 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
305 }
306 break;
307 case 6:
308 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
309 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
310 break;
311 case 7:
312 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
313 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
314 break;
315 default:
316 printf("Error: Unknown MAPLE/CPRI clock select!\n");
317 }
318
319 /* For MAPLE ULB and eTVPE frequencies */
320 #define ULB_CLK_SEL 0x00000038
321 #define ULB_CLK_SHIFT 3
322 #define ETVPE_CLK_SEL 0x00000007
323 #define ETVPE_CLK_SHIFT 0
324
325 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
326 case 1:
327 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
328 break;
329 case 2:
330 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
331 break;
332 case 3:
333 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
334 break;
335 case 4:
336 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
337 break;
338 case 5:
339 sys_info->freq_maple_ulb = sys_info->freq_systembus;
340 break;
341 case 6:
342 sys_info->freq_maple_ulb =
343 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
344 break;
345 case 7:
346 sys_info->freq_maple_ulb =
347 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
348 break;
349 default:
350 printf("Error: Unknown MAPLE ULB clock select!\n");
351 }
352
353 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
354 case 1:
355 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
356 break;
357 case 2:
358 sys_info->freq_maple_etvpe =
359 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
360 break;
361 case 3:
362 sys_info->freq_maple_etvpe =
363 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
364 break;
365 case 4:
366 sys_info->freq_maple_etvpe =
367 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
368 break;
369 case 5:
370 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
371 break;
372 case 6:
373 sys_info->freq_maple_etvpe =
374 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
375 break;
376 case 7:
377 sys_info->freq_maple_etvpe =
378 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
379 break;
380 default:
381 printf("Error: Unknown MAPLE eTVPE clock select!\n");
382 }
383
384 #endif
385
386 #ifdef CONFIG_SYS_DPAA_FMAN
387 #ifndef CONFIG_FM_PLAT_CLK_DIV
388 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
389 case 1:
390 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
391 break;
392 case 2:
393 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
394 break;
395 case 3:
396 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
397 break;
398 case 4:
399 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
400 break;
401 case 5:
402 sys_info->freq_fman[0] = sys_info->freq_systembus;
403 break;
404 case 6:
405 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
406 break;
407 case 7:
408 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
409 break;
410 default:
411 printf("Error: Unknown FMan1 clock select!\n");
412 case 0:
413 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
414 break;
415 }
416 #if (CONFIG_SYS_NUM_FMAN) == 2
417 #ifdef CONFIG_SYS_FM2_CLK
418 #define FM2_CLK_SEL 0x00000038
419 #define FM2_CLK_SHIFT 3
420 rcw_tmp = in_be32(&gur->rcwsr[15]);
421 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
422 case 1:
423 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
424 break;
425 case 2:
426 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
427 break;
428 case 3:
429 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
430 break;
431 case 4:
432 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
433 break;
434 case 5:
435 sys_info->freq_fman[1] = sys_info->freq_systembus;
436 break;
437 case 6:
438 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
439 break;
440 case 7:
441 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
442 break;
443 default:
444 printf("Error: Unknown FMan2 clock select!\n");
445 case 0:
446 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
447 break;
448 }
449 #endif
450 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
451 #else
452 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
453 #endif
454 #endif
455
456 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
457
458 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
459 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
460 & 0xf;
461 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
462
463 sys_info->freq_processor[cpu] =
464 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
465 }
466 #define PME_CLK_SEL 0x80000000
467 #define FM1_CLK_SEL 0x40000000
468 #define FM2_CLK_SEL 0x20000000
469 #define HWA_ASYNC_DIV 0x04000000
470 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
471 #define HWA_CC_PLL 1
472 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
473 #define HWA_CC_PLL 2
474 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
475 #define HWA_CC_PLL 2
476 #else
477 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
478 #endif
479 rcw_tmp = in_be32(&gur->rcwsr[7]);
480
481 #ifdef CONFIG_SYS_DPAA_PME
482 if (rcw_tmp & PME_CLK_SEL) {
483 if (rcw_tmp & HWA_ASYNC_DIV)
484 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
485 else
486 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
487 } else {
488 sys_info->freq_pme = sys_info->freq_systembus / 2;
489 }
490 #endif
491
492 #ifdef CONFIG_SYS_DPAA_FMAN
493 if (rcw_tmp & FM1_CLK_SEL) {
494 if (rcw_tmp & HWA_ASYNC_DIV)
495 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
496 else
497 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
498 } else {
499 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
500 }
501 #if (CONFIG_SYS_NUM_FMAN) == 2
502 if (rcw_tmp & FM2_CLK_SEL) {
503 if (rcw_tmp & HWA_ASYNC_DIV)
504 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
505 else
506 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
507 } else {
508 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
509 }
510 #endif
511 #endif
512
513 #ifdef CONFIG_SYS_DPAA_QBMAN
514 sys_info->freq_qman = sys_info->freq_systembus / 2;
515 #endif
516
517 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
518
519 #ifdef CONFIG_U_QE
520 sys_info->freq_qe = sys_info->freq_systembus / 2;
521 #endif
522
523 #else /* CONFIG_FSL_CORENET */
524 uint plat_ratio, e500_ratio, half_freq_systembus;
525 int i;
526 #ifdef CONFIG_QE
527 __maybe_unused u32 qe_ratio;
528 #endif
529
530 plat_ratio = (gur->porpllsr) & 0x0000003e;
531 plat_ratio >>= 1;
532 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
533
534 /* Divide before multiply to avoid integer
535 * overflow for processor speeds above 2GHz */
536 half_freq_systembus = sys_info->freq_systembus/2;
537 for (i = 0; i < cpu_numcores(); i++) {
538 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
539 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
540 }
541
542 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
543 sys_info->freq_ddrbus = sys_info->freq_systembus;
544
545 #ifdef CONFIG_DDR_CLK_FREQ
546 {
547 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
548 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
549 if (ddr_ratio != 0x7)
550 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
551 }
552 #endif
553
554 #ifdef CONFIG_QE
555 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
556 sys_info->freq_qe = sys_info->freq_systembus;
557 #else
558 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
559 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
560 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
561 #endif
562 #endif
563
564 #ifdef CONFIG_SYS_DPAA_FMAN
565 sys_info->freq_fman[0] = sys_info->freq_systembus;
566 #endif
567
568 #endif /* CONFIG_FSL_CORENET */
569
570 #if defined(CONFIG_FSL_LBC)
571 uint lcrr_div;
572 #if defined(CONFIG_SYS_LBC_LCRR)
573 /* We will program LCRR to this value later */
574 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
575 #else
576 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
577 #endif
578 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
579 #if defined(CONFIG_FSL_CORENET)
580 /* If this is corenet based SoC, bit-representation
581 * for four times the clock divider values.
582 */
583 lcrr_div *= 4;
584 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
585 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
586 /*
587 * Yes, the entire PQ38 family use the same
588 * bit-representation for twice the clock divider values.
589 */
590 lcrr_div *= 2;
591 #endif
592 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
593 } else {
594 /* In case anyone cares what the unknown value is */
595 sys_info->freq_localbus = lcrr_div;
596 }
597 #endif
598
599 #if defined(CONFIG_FSL_IFC)
600 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
601 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
602
603 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
604 #endif
605 }
606
607
608 int get_clocks (void)
609 {
610 sys_info_t sys_info;
611 #ifdef CONFIG_MPC8544
612 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
613 #endif
614 #if defined(CONFIG_CPM2)
615 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
616 uint sccr, dfbrg;
617
618 /* set VCO = 4 * BRG */
619 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
620 sccr = cpm->im_cpm_intctl.sccr;
621 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
622 #endif
623 get_sys_info (&sys_info);
624 gd->cpu_clk = sys_info.freq_processor[0];
625 gd->bus_clk = sys_info.freq_systembus;
626 gd->mem_clk = sys_info.freq_ddrbus;
627 gd->arch.lbc_clk = sys_info.freq_localbus;
628
629 #ifdef CONFIG_QE
630 gd->arch.qe_clk = sys_info.freq_qe;
631 gd->arch.brg_clk = gd->arch.qe_clk / 2;
632 #endif
633 /*
634 * The base clock for I2C depends on the actual SOC. Unfortunately,
635 * there is no pattern that can be used to determine the frequency, so
636 * the only choice is to look up the actual SOC number and use the value
637 * for that SOC. This information is taken from application note
638 * AN2919.
639 */
640 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
641 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
642 defined(CONFIG_P1022)
643 gd->arch.i2c1_clk = sys_info.freq_systembus;
644 #elif defined(CONFIG_MPC8544)
645 /*
646 * On the 8544, the I2C clock is the same as the SEC clock. This can be
647 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
648 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
649 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
650 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
651 */
652 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
653 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
654 else
655 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
656 #else
657 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
658 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
659 #endif
660 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
661
662 #if defined(CONFIG_FSL_ESDHC)
663 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
664 defined(CONFIG_P1014)
665 gd->arch.sdhc_clk = gd->bus_clk;
666 #else
667 gd->arch.sdhc_clk = gd->bus_clk / 2;
668 #endif
669 #endif /* defined(CONFIG_FSL_ESDHC) */
670
671 #if defined(CONFIG_CPM2)
672 gd->arch.vco_out = 2*sys_info.freq_systembus;
673 gd->arch.cpm_clk = gd->arch.vco_out / 2;
674 gd->arch.scc_clk = gd->arch.vco_out / 4;
675 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
676 #endif
677
678 if(gd->cpu_clk != 0) return (0);
679 else return (1);
680 }
681
682
683 /********************************************
684 * get_bus_freq
685 * return system bus freq in Hz
686 *********************************************/
687 ulong get_bus_freq (ulong dummy)
688 {
689 return gd->bus_clk;
690 }
691
692 /********************************************
693 * get_ddr_freq
694 * return ddr bus freq in Hz
695 *********************************************/
696 ulong get_ddr_freq (ulong dummy)
697 {
698 return gd->mem_clk;
699 }
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