arch/powerpc/cpu/mpc85xx/start.S

   1 /*
   2  * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2003  Motorola,Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
  25  *
  26  * The processor starts at 0xfffffffc and the code is first executed in the
  27  * last 4K page(0xfffff000-0xffffffff) in flash/rom.
  28  *
  29  */
  30
  31 #include <asm-offsets.h>
  32 #include <config.h>
  33 #include <mpc85xx.h>
  34 #include <timestamp.h>
  35 #include <version.h>
  36
  37 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  38
  39 #include <ppc_asm.tmpl>
  40 #include <ppc_defs.h>
  41
  42 #include <asm/cache.h>
  43 #include <asm/mmu.h>
  44
  45 #ifndef  CONFIG_IDENT_STRING
  46 #define  CONFIG_IDENT_STRING ""
  47 #endif
  48
  49 #undef  MSR_KERNEL
  50 #define MSR_KERNEL ( MSR_ME )   /* Machine Check */
  51
  52 /*
  53  * Set up GOT: Global Offset Table
  54  *
  55  * Use r12 to access the GOT
  56  */
  57         START_GOT
  58         GOT_ENTRY(_GOT2_TABLE_)
  59         GOT_ENTRY(_FIXUP_TABLE_)
  60
  61 #ifndef CONFIG_NAND_SPL
  62         GOT_ENTRY(_start)
  63         GOT_ENTRY(_start_of_vectors)
  64         GOT_ENTRY(_end_of_vectors)
  65         GOT_ENTRY(transfer_to_handler)
  66 #endif
  67
  68         GOT_ENTRY(__init_end)
  69         GOT_ENTRY(__bss_end__)
  70         GOT_ENTRY(__bss_start)
  71         END_GOT
  72
  73 /*
  74  * e500 Startup -- after reset only the last 4KB of the effective
  75  * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
  76  * section is located at THIS LAST page and basically does three
  77  * things: clear some registers, set up exception tables and
  78  * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
  79  * continue the boot procedure.
  80
  81  * Once the boot rom is mapped by TLB entries we can proceed
  82  * with normal startup.
  83  *
  84  */
  85
  86         .section .bootpg,"ax"
  87         .globl _start_e500
  88
  89 _start_e500:
  90
  91 /* clear registers/arrays not reset by hardware */
  92
  93         /* L1 */
  94         li      r0,2
  95         mtspr   L1CSR0,r0       /* invalidate d-cache */
  96         mtspr   L1CSR1,r0       /* invalidate i-cache */
  97
  98         mfspr   r1,DBSR
  99         mtspr   DBSR,r1         /* Clear all valid bits */
 100
 101         /*
 102          *      Enable L1 Caches early
 103          *
 104          */
 105
 106 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
 107         /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
 108         li      r2,(32 + 0)
 109         mtspr   L1CSR2,r2
 110 #endif
 111
 112         /* Enable/invalidate the I-Cache */
 113         lis     r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
 114         ori     r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
 115         mtspr   SPRN_L1CSR1,r2
 116 1:
 117         mfspr   r3,SPRN_L1CSR1
 118         and.    r1,r3,r2
 119         bne     1b
 120
 121         lis     r3,(L1CSR1_CPE|L1CSR1_ICE)@h
 122         ori     r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
 123         mtspr   SPRN_L1CSR1,r3
 124         isync
 125 2:
 126         mfspr   r3,SPRN_L1CSR1
 127         andi.   r1,r3,L1CSR1_ICE@l
 128         beq     2b
 129
 130         /* Enable/invalidate the D-Cache */
 131         lis     r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
 132         ori     r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
 133         mtspr   SPRN_L1CSR0,r2
 134 1:
 135         mfspr   r3,SPRN_L1CSR0
 136         and.    r1,r3,r2
 137         bne     1b
 138
 139         lis     r3,(L1CSR0_CPE|L1CSR0_DCE)@h
 140         ori     r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
 141         mtspr   SPRN_L1CSR0,r3
 142         isync
 143 2:
 144         mfspr   r3,SPRN_L1CSR0
 145         andi.   r1,r3,L1CSR0_DCE@l
 146         beq     2b
 147
 148         /* Setup interrupt vectors */
 149         lis     r1,CONFIG_SYS_MONITOR_BASE@h
 150         mtspr   IVPR,r1
 151
 152         li      r1,0x0100
 153         mtspr   IVOR0,r1        /* 0: Critical input */
 154         li      r1,0x0200
 155         mtspr   IVOR1,r1        /* 1: Machine check */
 156         li      r1,0x0300
 157         mtspr   IVOR2,r1        /* 2: Data storage */
 158         li      r1,0x0400
 159         mtspr   IVOR3,r1        /* 3: Instruction storage */
 160         li      r1,0x0500
 161         mtspr   IVOR4,r1        /* 4: External interrupt */
 162         li      r1,0x0600
 163         mtspr   IVOR5,r1        /* 5: Alignment */
 164         li      r1,0x0700
 165         mtspr   IVOR6,r1        /* 6: Program check */
 166         li      r1,0x0800
 167         mtspr   IVOR7,r1        /* 7: floating point unavailable */
 168         li      r1,0x0900
 169         mtspr   IVOR8,r1        /* 8: System call */
 170         /* 9: Auxiliary processor unavailable(unsupported) */
 171         li      r1,0x0a00
 172         mtspr   IVOR10,r1       /* 10: Decrementer */
 173         li      r1,0x0b00
 174         mtspr   IVOR11,r1       /* 11: Interval timer */
 175         li      r1,0x0c00
 176         mtspr   IVOR12,r1       /* 12: Watchdog timer */
 177         li      r1,0x0d00
 178         mtspr   IVOR13,r1       /* 13: Data TLB error */
 179         li      r1,0x0e00
 180         mtspr   IVOR14,r1       /* 14: Instruction TLB error */
 181         li      r1,0x0f00
 182         mtspr   IVOR15,r1       /* 15: Debug */
 183
 184         /* Clear and set up some registers. */
 185         li      r0,0x0000
 186         lis     r1,0xffff
 187         mtspr   DEC,r0                  /* prevent dec exceptions */
 188         mttbl   r0                      /* prevent fit & wdt exceptions */
 189         mttbu   r0
 190         mtspr   TSR,r1                  /* clear all timer exception status */
 191         mtspr   TCR,r0                  /* disable all */
 192         mtspr   ESR,r0                  /* clear exception syndrome register */
 193         mtspr   MCSR,r0                 /* machine check syndrome register */
 194         mtxer   r0                      /* clear integer exception register */
 195
 196 #ifdef CONFIG_SYS_BOOK3E_HV
 197         mtspr   MAS8,r0                 /* make sure MAS8 is clear */
 198 #endif
 199
 200         /* Enable Time Base and Select Time Base Clock */
 201         lis     r0,HID0_EMCP@h          /* Enable machine check */
 202 #if defined(CONFIG_ENABLE_36BIT_PHYS)
 203         ori     r0,r0,HID0_ENMAS7@l     /* Enable MAS7 */
 204 #endif
 205 #ifndef CONFIG_E500MC
 206         ori     r0,r0,HID0_TBEN@l       /* Enable Timebase */
 207 #endif
 208         mtspr   HID0,r0
 209
 210 #ifndef CONFIG_E500MC
 211         li      r0,(HID1_ASTME|HID1_ABE)@l      /* Addr streaming & broadcast */
 212         mfspr   r3,PVR
 213         andi.   r3,r3, 0xff
 214         cmpwi   r3,0x50@l       /* if we are rev 5.0 or greater set MBDD */
 215         blt 1f
 216         /* Set MBDD bit also */
 217         ori r0, r0, HID1_MBDD@l
 218 1:
 219         mtspr   HID1,r0
 220 #endif
 221
 222         /* Enable Branch Prediction */
 223 #if defined(CONFIG_BTB)
 224         lis     r0,BUCSR_ENABLE@h
 225         ori     r0,r0,BUCSR_ENABLE@l
 226         mtspr   SPRN_BUCSR,r0
 227 #endif
 228
 229 #if defined(CONFIG_SYS_INIT_DBCR)
 230         lis     r1,0xffff
 231         ori     r1,r1,0xffff
 232         mtspr   DBSR,r1                 /* Clear all status bits */
 233         lis     r0,CONFIG_SYS_INIT_DBCR@h       /* DBCR0[IDM] must be set */
 234         ori     r0,r0,CONFIG_SYS_INIT_DBCR@l
 235         mtspr   DBCR0,r0
 236 #endif
 237
 238 #ifdef CONFIG_MPC8569
 239 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
 240 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
 241
 242         /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
 243          * use address space which is more than 12bits, and it must be done in
 244          * the 4K boot page. So we set this bit here.
 245          */
 246
 247         /* create a temp mapping TLB0[0] for LBCR  */
 248         lis     r6,FSL_BOOKE_MAS0(0, 0, 0)@h
 249         ori     r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
 250
 251         lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
 252         ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
 253
 254         lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
 255         ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
 256
 257         lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
 258                                                 (MAS3_SX|MAS3_SW|MAS3_SR))@h
 259         ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
 260                                                 (MAS3_SX|MAS3_SW|MAS3_SR))@l
 261
 262         mtspr   MAS0,r6
 263         mtspr   MAS1,r7
 264         mtspr   MAS2,r8
 265         mtspr   MAS3,r9
 266         isync
 267         msync
 268         tlbwe
 269
 270         /* Set LBCR register */
 271         lis     r4,CONFIG_SYS_LBCR_ADDR@h
 272         ori     r4,r4,CONFIG_SYS_LBCR_ADDR@l
 273
 274         lis     r5,CONFIG_SYS_LBC_LBCR@h
 275         ori     r5,r5,CONFIG_SYS_LBC_LBCR@l
 276         stw     r5,0(r4)
 277         isync
 278
 279         /* invalidate this temp TLB */
 280         lis     r4,CONFIG_SYS_LBC_ADDR@h
 281         ori     r4,r4,CONFIG_SYS_LBC_ADDR@l
 282         tlbivax 0,r4
 283         isync
 284
 285 #endif /* CONFIG_MPC8569 */
 286
 287         lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
 288         ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 289
 290 #ifndef CONFIG_SYS_RAMBOOT
 291         /* create a temp mapping in AS=1 to the 4M boot window */
 292         lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
 293         ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
 294
 295         lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
 296         ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
 297
 298         /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
 299         lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 300         ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 301 #else
 302         /*
 303          * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
 304          * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
 305          */
 306         lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
 307         ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
 308
 309         lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
 310         ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
 311
 312         lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 313         ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 314 #endif
 315
 316         mtspr   MAS0,r6
 317         mtspr   MAS1,r7
 318         mtspr   MAS2,r8
 319         mtspr   MAS3,r9
 320         isync
 321         msync
 322         tlbwe
 323
 324         /* create a temp mapping in AS=1 to the stack */
 325         lis     r6,FSL_BOOKE_MAS0(1, 14, 0)@h
 326         ori     r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
 327
 328         lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
 329         ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
 330
 331         lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
 332         ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
 333
 334 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
 335     defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
 336         lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
 337                                 (MAS3_SX|MAS3_SW|MAS3_SR))@h
 338         ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
 339                                 (MAS3_SX|MAS3_SW|MAS3_SR))@l
 340         li      r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
 341         mtspr   MAS7,r10
 342 #else
 343         lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 344         ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 345 #endif
 346
 347         mtspr   MAS0,r6
 348         mtspr   MAS1,r7
 349         mtspr   MAS2,r8
 350         mtspr   MAS3,r9
 351         isync
 352         msync
 353         tlbwe
 354
 355         lis     r6,MSR_IS|MSR_DS@h
 356         ori     r6,r6,MSR_IS|MSR_DS@l
 357         lis     r7,switch_as@h
 358         ori     r7,r7,switch_as@l
 359
 360         mtspr   SPRN_SRR0,r7
 361         mtspr   SPRN_SRR1,r6
 362         rfi
 363
 364 switch_as:
 365 /* L1 DCache is used for initial RAM */
 366
 367         /* Allocate Initial RAM in data cache.
 368          */
 369         lis     r3,CONFIG_SYS_INIT_RAM_ADDR@h
 370         ori     r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
 371         mfspr   r2, L1CFG0
 372         andi.   r2, r2, 0x1ff
 373         /* cache size * 1024 / (2 * L1 line size) */
 374         slwi    r2, r2, (10 - 1 - L1_CACHE_SHIFT)
 375         mtctr   r2
 376         li      r0,0
 377 1:
 378         dcbz    r0,r3
 379         dcbtls  0,r0,r3
 380         addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
 381         bdnz    1b
 382
 383         /* Jump out the last 4K page and continue to 'normal' start */
 384 #ifdef CONFIG_SYS_RAMBOOT
 385         b       _start_cont
 386 #else
 387         /* Calculate absolute address in FLASH and jump there           */
 388         /*--------------------------------------------------------------*/
 389         lis     r3,CONFIG_SYS_MONITOR_BASE@h
 390         ori     r3,r3,CONFIG_SYS_MONITOR_BASE@l
 391         addi    r3,r3,_start_cont - _start + _START_OFFSET
 392         mtlr    r3
 393         blr
 394 #endif
 395
 396         .text
 397         .globl  _start
 398 _start:
 399         .long   0x27051956              /* U-BOOT Magic Number */
 400         .globl  version_string
 401 version_string:
 402         .ascii U_BOOT_VERSION
 403         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
 404         .ascii CONFIG_IDENT_STRING, "\0"
 405
 406         .align  4
 407         .globl  _start_cont
 408 _start_cont:
 409         /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 410         lis     r1,CONFIG_SYS_INIT_RAM_ADDR@h
 411         ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
 412
 413         li      r0,0
 414         stwu    r0,-4(r1)
 415         stwu    r0,-4(r1)               /* Terminate call chain */
 416
 417         stwu    r1,-8(r1)               /* Save back chain and move SP */
 418         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 419         ori     r0,r0,RESET_VECTOR@l
 420         stwu    r1,-8(r1)               /* Save back chain and move SP */
 421         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 422
 423         GET_GOT
 424 #if defined(__pic__) && __pic__ == 1
 425         /* Needed for upcoming -msingle-pic-base */
 426         bl      _GLOBAL_OFFSET_TABLE_@local-4
 427         mflr    r30
 428 #endif
 429         bl      cpu_init_early_f
 430
 431         /* switch back to AS = 0 */
 432         lis     r3,(MSR_CE|MSR_ME|MSR_DE)@h
 433         ori     r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
 434         mtmsr   r3
 435         isync
 436
 437         bl      cpu_init_f
 438         bl      board_init_f
 439         isync
 440
 441         /* NOTREACHED - board_init_f() does not return */
 442
 443 #ifndef CONFIG_NAND_SPL
 444         . = EXC_OFF_SYS_RESET
 445         .globl  _start_of_vectors
 446 _start_of_vectors:
 447
 448 /* Critical input. */
 449         CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
 450
 451 /* Machine check */
 452         MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 453
 454 /* Data Storage exception. */
 455         STD_EXCEPTION(0x0300, DataStorage, UnknownException)
 456
 457 /* Instruction Storage exception. */
 458         STD_EXCEPTION(0x0400, InstStorage, UnknownException)
 459
 460 /* External Interrupt exception. */
 461         STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
 462
 463 /* Alignment exception. */
 464         . = 0x0600
 465 Alignment:
 466         EXCEPTION_PROLOG(SRR0, SRR1)
 467         mfspr   r4,DAR
 468         stw     r4,_DAR(r21)
 469         mfspr   r5,DSISR
 470         stw     r5,_DSISR(r21)
 471         addi    r3,r1,STACK_FRAME_OVERHEAD
 472         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 473
 474 /* Program check exception */
 475         . = 0x0700
 476 ProgramCheck:
 477         EXCEPTION_PROLOG(SRR0, SRR1)
 478         addi    r3,r1,STACK_FRAME_OVERHEAD
 479         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 480                 MSR_KERNEL, COPY_EE)
 481
 482         /* No FPU on MPC85xx.  This exception is not supposed to happen.
 483         */
 484         STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
 485
 486         . = 0x0900
 487 /*
 488  * r0 - SYSCALL number
 489  * r3-... arguments
 490  */
 491 SystemCall:
 492         addis   r11,r0,0        /* get functions table addr */
 493         ori     r11,r11,0       /* Note: this code is patched in trap_init */
 494         addis   r12,r0,0        /* get number of functions */
 495         ori     r12,r12,0
 496
 497         cmplw   0,r0,r12
 498         bge     1f
 499
 500         rlwinm  r0,r0,2,0,31    /* fn_addr = fn_tbl[r0] */
 501         add     r11,r11,r0
 502         lwz     r11,0(r11)
 503
 504         li      r20,0xd00-4     /* Get stack pointer */
 505         lwz     r12,0(r20)
 506         subi    r12,r12,12      /* Adjust stack pointer */
 507         li      r0,0xc00+_end_back-SystemCall
 508         cmplw   0,r0,r12        /* Check stack overflow */
 509         bgt     1f
 510         stw     r12,0(r20)
 511
 512         mflr    r0
 513         stw     r0,0(r12)
 514         mfspr   r0,SRR0
 515         stw     r0,4(r12)
 516         mfspr   r0,SRR1
 517         stw     r0,8(r12)
 518
 519         li      r12,0xc00+_back-SystemCall
 520         mtlr    r12
 521         mtspr   SRR0,r11
 522
 523 1:      SYNC
 524         rfi
 525 _back:
 526
 527         mfmsr   r11                     /* Disable interrupts */
 528         li      r12,0
 529         ori     r12,r12,MSR_EE
 530         andc    r11,r11,r12
 531         SYNC                            /* Some chip revs need this... */
 532         mtmsr   r11
 533         SYNC
 534
 535         li      r12,0xd00-4             /* restore regs */
 536         lwz     r12,0(r12)
 537
 538         lwz     r11,0(r12)
 539         mtlr    r11
 540         lwz     r11,4(r12)
 541         mtspr   SRR0,r11
 542         lwz     r11,8(r12)
 543         mtspr   SRR1,r11
 544
 545         addi    r12,r12,12              /* Adjust stack pointer */
 546         li      r20,0xd00-4
 547         stw     r12,0(r20)
 548
 549         SYNC
 550         rfi
 551 _end_back:
 552
 553         STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
 554         STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
 555         STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
 556
 557         STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
 558         STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
 559
 560         CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
 561
 562         .globl  _end_of_vectors
 563 _end_of_vectors:
 564
 565
 566         . = . + (0x100 - ( . & 0xff ))  /* align for debug */
 567
 568 /*
 569  * This code finishes saving the registers to the exception frame
 570  * and jumps to the appropriate handler for the exception.
 571  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 572  */
 573         .globl  transfer_to_handler
 574 transfer_to_handler:
 575         stw     r22,_NIP(r21)
 576         lis     r22,MSR_POW@h
 577         andc    r23,r23,r22
 578         stw     r23,_MSR(r21)
 579         SAVE_GPR(7, r21)
 580         SAVE_4GPRS(8, r21)
 581         SAVE_8GPRS(12, r21)
 582         SAVE_8GPRS(24, r21)
 583
 584         mflr    r23
 585         andi.   r24,r23,0x3f00          /* get vector offset */
 586         stw     r24,TRAP(r21)
 587         li      r22,0
 588         stw     r22,RESULT(r21)
 589         mtspr   SPRG2,r22               /* r1 is now kernel sp */
 590
 591         lwz     r24,0(r23)              /* virtual address of handler */
 592         lwz     r23,4(r23)              /* where to go when done */
 593         mtspr   SRR0,r24
 594         mtspr   SRR1,r20
 595         mtlr    r23
 596         SYNC
 597         rfi                             /* jump to handler, enable MMU */
 598
 599 int_return:
 600         mfmsr   r28             /* Disable interrupts */
 601         li      r4,0
 602         ori     r4,r4,MSR_EE
 603         andc    r28,r28,r4
 604         SYNC                    /* Some chip revs need this... */
 605         mtmsr   r28
 606         SYNC
 607         lwz     r2,_CTR(r1)
 608         lwz     r0,_LINK(r1)
 609         mtctr   r2
 610         mtlr    r0
 611         lwz     r2,_XER(r1)
 612         lwz     r0,_CCR(r1)
 613         mtspr   XER,r2
 614         mtcrf   0xFF,r0
 615         REST_10GPRS(3, r1)
 616         REST_10GPRS(13, r1)
 617         REST_8GPRS(23, r1)
 618         REST_GPR(31, r1)
 619         lwz     r2,_NIP(r1)     /* Restore environment */
 620         lwz     r0,_MSR(r1)
 621         mtspr   SRR0,r2
 622         mtspr   SRR1,r0
 623         lwz     r0,GPR0(r1)
 624         lwz     r2,GPR2(r1)
 625         lwz     r1,GPR1(r1)
 626         SYNC
 627         rfi
 628
 629 crit_return:
 630         mfmsr   r28             /* Disable interrupts */
 631         li      r4,0
 632         ori     r4,r4,MSR_EE
 633         andc    r28,r28,r4
 634         SYNC                    /* Some chip revs need this... */
 635         mtmsr   r28
 636         SYNC
 637         lwz     r2,_CTR(r1)
 638         lwz     r0,_LINK(r1)
 639         mtctr   r2
 640         mtlr    r0
 641         lwz     r2,_XER(r1)
 642         lwz     r0,_CCR(r1)
 643         mtspr   XER,r2
 644         mtcrf   0xFF,r0
 645         REST_10GPRS(3, r1)
 646         REST_10GPRS(13, r1)
 647         REST_8GPRS(23, r1)
 648         REST_GPR(31, r1)
 649         lwz     r2,_NIP(r1)     /* Restore environment */
 650         lwz     r0,_MSR(r1)
 651         mtspr   SPRN_CSRR0,r2
 652         mtspr   SPRN_CSRR1,r0
 653         lwz     r0,GPR0(r1)
 654         lwz     r2,GPR2(r1)
 655         lwz     r1,GPR1(r1)
 656         SYNC
 657         rfci
 658
 659 mck_return:
 660         mfmsr   r28             /* Disable interrupts */
 661         li      r4,0
 662         ori     r4,r4,MSR_EE
 663         andc    r28,r28,r4
 664         SYNC                    /* Some chip revs need this... */
 665         mtmsr   r28
 666         SYNC
 667         lwz     r2,_CTR(r1)
 668         lwz     r0,_LINK(r1)
 669         mtctr   r2
 670         mtlr    r0
 671         lwz     r2,_XER(r1)
 672         lwz     r0,_CCR(r1)
 673         mtspr   XER,r2
 674         mtcrf   0xFF,r0
 675         REST_10GPRS(3, r1)
 676         REST_10GPRS(13, r1)
 677         REST_8GPRS(23, r1)
 678         REST_GPR(31, r1)
 679         lwz     r2,_NIP(r1)     /* Restore environment */
 680         lwz     r0,_MSR(r1)
 681         mtspr   SPRN_MCSRR0,r2
 682         mtspr   SPRN_MCSRR1,r0
 683         lwz     r0,GPR0(r1)
 684         lwz     r2,GPR2(r1)
 685         lwz     r1,GPR1(r1)
 686         SYNC
 687         rfmci
 688
 689 /* Cache functions.
 690 */
 691 .globl invalidate_icache
 692 invalidate_icache:
 693         mfspr   r0,L1CSR1
 694         ori     r0,r0,L1CSR1_ICFI
 695         msync
 696         isync
 697         mtspr   L1CSR1,r0
 698         isync
 699         blr                             /* entire I cache */
 700
 701 .globl invalidate_dcache
 702 invalidate_dcache:
 703         mfspr   r0,L1CSR0
 704         ori     r0,r0,L1CSR0_DCFI
 705         msync
 706         isync
 707         mtspr   L1CSR0,r0
 708         isync
 709         blr
 710
 711         .globl  icache_enable
 712 icache_enable:
 713         mflr    r8
 714         bl      invalidate_icache
 715         mtlr    r8
 716         isync
 717         mfspr   r4,L1CSR1
 718         ori     r4,r4,0x0001
 719         oris    r4,r4,0x0001
 720         mtspr   L1CSR1,r4
 721         isync
 722         blr
 723
 724         .globl  icache_disable
 725 icache_disable:
 726         mfspr   r0,L1CSR1
 727         lis     r3,0
 728         ori     r3,r3,L1CSR1_ICE
 729         andc    r0,r0,r3
 730         mtspr   L1CSR1,r0
 731         isync
 732         blr
 733
 734         .globl  icache_status
 735 icache_status:
 736         mfspr   r3,L1CSR1
 737         andi.   r3,r3,L1CSR1_ICE
 738         blr
 739
 740         .globl  dcache_enable
 741 dcache_enable:
 742         mflr    r8
 743         bl      invalidate_dcache
 744         mtlr    r8
 745         isync
 746         mfspr   r0,L1CSR0
 747         ori     r0,r0,0x0001
 748         oris    r0,r0,0x0001
 749         msync
 750         isync
 751         mtspr   L1CSR0,r0
 752         isync
 753         blr
 754
 755         .globl  dcache_disable
 756 dcache_disable:
 757         mfspr   r3,L1CSR0
 758         lis     r4,0
 759         ori     r4,r4,L1CSR0_DCE
 760         andc    r3,r3,r4
 761         mtspr   L1CSR0,r3
 762         isync
 763         blr
 764
 765         .globl  dcache_status
 766 dcache_status:
 767         mfspr   r3,L1CSR0
 768         andi.   r3,r3,L1CSR0_DCE
 769         blr
 770
 771         .globl get_pir
 772 get_pir:
 773         mfspr   r3,PIR
 774         blr
 775
 776         .globl get_pvr
 777 get_pvr:
 778         mfspr   r3,PVR
 779         blr
 780
 781         .globl get_svr
 782 get_svr:
 783         mfspr   r3,SVR
 784         blr
 785
 786         .globl wr_tcr
 787 wr_tcr:
 788         mtspr   TCR,r3
 789         blr
 790
 791 /*------------------------------------------------------------------------------- */
 792 /* Function:     in8 */
 793 /* Description:  Input 8 bits */
 794 /*------------------------------------------------------------------------------- */
 795         .globl  in8
 796 in8:
 797         lbz     r3,0x0000(r3)
 798         blr
 799
 800 /*------------------------------------------------------------------------------- */
 801 /* Function:     out8 */
 802 /* Description:  Output 8 bits */
 803 /*------------------------------------------------------------------------------- */
 804         .globl  out8
 805 out8:
 806         stb     r4,0x0000(r3)
 807         sync
 808         blr
 809
 810 /*------------------------------------------------------------------------------- */
 811 /* Function:     out16 */
 812 /* Description:  Output 16 bits */
 813 /*------------------------------------------------------------------------------- */
 814         .globl  out16
 815 out16:
 816         sth     r4,0x0000(r3)
 817         sync
 818         blr
 819
 820 /*------------------------------------------------------------------------------- */
 821 /* Function:     out16r */
 822 /* Description:  Byte reverse and output 16 bits */
 823 /*------------------------------------------------------------------------------- */
 824         .globl  out16r
 825 out16r:
 826         sthbrx  r4,r0,r3
 827         sync
 828         blr
 829
 830 /*------------------------------------------------------------------------------- */
 831 /* Function:     out32 */
 832 /* Description:  Output 32 bits */
 833 /*------------------------------------------------------------------------------- */
 834         .globl  out32
 835 out32:
 836         stw     r4,0x0000(r3)
 837         sync
 838         blr
 839
 840 /*------------------------------------------------------------------------------- */
 841 /* Function:     out32r */
 842 /* Description:  Byte reverse and output 32 bits */
 843 /*------------------------------------------------------------------------------- */
 844         .globl  out32r
 845 out32r:
 846         stwbrx  r4,r0,r3
 847         sync
 848         blr
 849
 850 /*------------------------------------------------------------------------------- */
 851 /* Function:     in16 */
 852 /* Description:  Input 16 bits */
 853 /*------------------------------------------------------------------------------- */
 854         .globl  in16
 855 in16:
 856         lhz     r3,0x0000(r3)
 857         blr
 858
 859 /*------------------------------------------------------------------------------- */
 860 /* Function:     in16r */
 861 /* Description:  Input 16 bits and byte reverse */
 862 /*------------------------------------------------------------------------------- */
 863         .globl  in16r
 864 in16r:
 865         lhbrx   r3,r0,r3
 866         blr
 867
 868 /*------------------------------------------------------------------------------- */
 869 /* Function:     in32 */
 870 /* Description:  Input 32 bits */
 871 /*------------------------------------------------------------------------------- */
 872         .globl  in32
 873 in32:
 874         lwz     3,0x0000(3)
 875         blr
 876
 877 /*------------------------------------------------------------------------------- */
 878 /* Function:     in32r */
 879 /* Description:  Input 32 bits and byte reverse */
 880 /*------------------------------------------------------------------------------- */
 881         .globl  in32r
 882 in32r:
 883         lwbrx   r3,r0,r3
 884         blr
 885 #endif  /* !CONFIG_NAND_SPL */
 886
 887 /*------------------------------------------------------------------------------*/
 888
 889 /*
 890  * void write_tlb(mas0, mas1, mas2, mas3, mas7)
 891  */
 892         .globl  write_tlb
 893 write_tlb:
 894         mtspr   MAS0,r3
 895         mtspr   MAS1,r4
 896         mtspr   MAS2,r5
 897         mtspr   MAS3,r6
 898 #ifdef CONFIG_ENABLE_36BIT_PHYS
 899         mtspr   MAS7,r7
 900 #endif
 901         li      r3,0
 902 #ifdef CONFIG_SYS_BOOK3E_HV
 903         mtspr   MAS8,r3
 904 #endif
 905         isync
 906         tlbwe
 907         msync
 908         isync
 909         blr
 910
 911 /*
 912  * void relocate_code (addr_sp, gd, addr_moni)
 913  *
 914  * This "function" does not return, instead it continues in RAM
 915  * after relocating the monitor code.
 916  *
 917  * r3 = dest
 918  * r4 = src
 919  * r5 = length in bytes
 920  * r6 = cachelinesize
 921  */
 922         .globl  relocate_code
 923 relocate_code:
 924         mr      r1,r3           /* Set new stack pointer                */
 925         mr      r9,r4           /* Save copy of Init Data pointer       */
 926         mr      r10,r5          /* Save copy of Destination Address     */
 927
 928         GET_GOT
 929 #if defined(__pic__) && __pic__ == 1
 930         /* Needed for upcoming -msingle-pic-base */
 931         bl      _GLOBAL_OFFSET_TABLE_@local-4
 932         mflr    r30
 933 #endif
 934         mr      r3,r5                           /* Destination Address  */
 935         lis     r4,CONFIG_SYS_MONITOR_BASE@h            /* Source      Address  */
 936         ori     r4,r4,CONFIG_SYS_MONITOR_BASE@l
 937         lwz     r5,GOT(__init_end)
 938         sub     r5,r5,r4
 939         li      r6,CONFIG_SYS_CACHELINE_SIZE            /* Cache Line Size      */
 940
 941         /*
 942          * Fix GOT pointer:
 943          *
 944          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 945          *
 946          * Offset:
 947          */
 948         sub     r15,r10,r4
 949
 950         /* First our own GOT */
 951         add     r12,r12,r15
 952         /* the the one used by the C code */
 953         add     r30,r30,r15
 954
 955         /*
 956          * Now relocate code
 957          */
 958
 959         cmplw   cr1,r3,r4
 960         addi    r0,r5,3
 961         srwi.   r0,r0,2
 962         beq     cr1,4f          /* In place copy is not necessary       */
 963         beq     7f              /* Protect against 0 count              */
 964         mtctr   r0
 965         bge     cr1,2f
 966
 967         la      r8,-4(r4)
 968         la      r7,-4(r3)
 969 1:      lwzu    r0,4(r8)
 970         stwu    r0,4(r7)
 971         bdnz    1b
 972         b       4f
 973
 974 2:      slwi    r0,r0,2
 975         add     r8,r4,r0
 976         add     r7,r3,r0
 977 3:      lwzu    r0,-4(r8)
 978         stwu    r0,-4(r7)
 979         bdnz    3b
 980
 981 /*
 982  * Now flush the cache: note that we must start from a cache aligned
 983  * address. Otherwise we might miss one cache line.
 984  */
 985 4:      cmpwi   r6,0
 986         add     r5,r3,r5
 987         beq     7f              /* Always flush prefetch queue in any case */
 988         subi    r0,r6,1
 989         andc    r3,r3,r0
 990         mr      r4,r3
 991 5:      dcbst   0,r4
 992         add     r4,r4,r6
 993         cmplw   r4,r5
 994         blt     5b
 995         sync                    /* Wait for all dcbst to complete on bus */
 996         mr      r4,r3
 997 6:      icbi    0,r4
 998         add     r4,r4,r6
 999         cmplw   r4,r5
1000         blt     6b
1001 7:      sync                    /* Wait for all icbi to complete on bus */
1002         isync
1003
1004         /*
1005          * Re-point the IVPR at RAM
1006          */
1007         mtspr   IVPR,r10
1008
1009 /*
1010  * We are done. Do not return, instead branch to second part of board
1011  * initialization, now running from RAM.
1012  */
1013
1014         addi    r0,r10,in_ram - _start + _START_OFFSET
1015         mtlr    r0
1016         blr                             /* NEVER RETURNS! */
1017         .globl  in_ram
1018 in_ram:
1019
1020         /*
1021          * Relocation Function, r12 point to got2+0x8000
1022          *
1023          * Adjust got2 pointers, no need to check for 0, this code
1024          * already puts a few entries in the table.
1025          */
1026         li      r0,__got2_entries@sectoff@l
1027         la      r3,GOT(_GOT2_TABLE_)
1028         lwz     r11,GOT(_GOT2_TABLE_)
1029         mtctr   r0
1030         sub     r11,r3,r11
1031         addi    r3,r3,-4
1032 1:      lwzu    r0,4(r3)
1033         cmpwi   r0,0
1034         beq-    2f
1035         add     r0,r0,r11
1036         stw     r0,0(r3)
1037 2:      bdnz    1b
1038
1039         /*
1040          * Now adjust the fixups and the pointers to the fixups
1041          * in case we need to move ourselves again.
1042          */
1043         li      r0,__fixup_entries@sectoff@l
1044         lwz     r3,GOT(_FIXUP_TABLE_)
1045         cmpwi   r0,0
1046         mtctr   r0
1047         addi    r3,r3,-4
1048         beq     4f
1049 3:      lwzu    r4,4(r3)
1050         lwzux   r0,r4,r11
1051         cmpwi   r0,0
1052         add     r0,r0,r11
1053         stw     r4,0(r3)
1054         beq-    5f
1055         stw     r0,0(r4)
1056 5:      bdnz    3b
1057 4:
1058 clear_bss:
1059         /*
1060          * Now clear BSS segment
1061          */
1062         lwz     r3,GOT(__bss_start)
1063         lwz     r4,GOT(__bss_end__)
1064
1065         cmplw   0,r3,r4
1066         beq     6f
1067
1068         li      r0,0
1069 5:
1070         stw     r0,0(r3)
1071         addi    r3,r3,4
1072         cmplw   0,r3,r4
1073         bne     5b
1074 6:
1075
1076         mr      r3,r9           /* Init Data pointer            */
1077         mr      r4,r10          /* Destination Address          */
1078         bl      board_init_r
1079
1080 #ifndef CONFIG_NAND_SPL
1081         /*
1082          * Copy exception vector code to low memory
1083          *
1084          * r3: dest_addr
1085          * r7: source address, r8: end address, r9: target address
1086          */
1087         .globl  trap_init
1088 trap_init:
1089         mflr    r4                      /* save link register           */
1090         GET_GOT
1091         lwz     r7,GOT(_start_of_vectors)
1092         lwz     r8,GOT(_end_of_vectors)
1093
1094         li      r9,0x100                /* reset vector always at 0x100 */
1095
1096         cmplw   0,r7,r8
1097         bgelr                           /* return if r7>=r8 - just in case */
1098 1:
1099         lwz     r0,0(r7)
1100         stw     r0,0(r9)
1101         addi    r7,r7,4
1102         addi    r9,r9,4
1103         cmplw   0,r7,r8
1104         bne     1b
1105
1106         /*
1107          * relocate `hdlr' and `int_return' entries
1108          */
1109         li      r7,.L_CriticalInput - _start + _START_OFFSET
1110         bl      trap_reloc
1111         li      r7,.L_MachineCheck - _start + _START_OFFSET
1112         bl      trap_reloc
1113         li      r7,.L_DataStorage - _start + _START_OFFSET
1114         bl      trap_reloc
1115         li      r7,.L_InstStorage - _start + _START_OFFSET
1116         bl      trap_reloc
1117         li      r7,.L_ExtInterrupt - _start + _START_OFFSET
1118         bl      trap_reloc
1119         li      r7,.L_Alignment - _start + _START_OFFSET
1120         bl      trap_reloc
1121         li      r7,.L_ProgramCheck - _start + _START_OFFSET
1122         bl      trap_reloc
1123         li      r7,.L_FPUnavailable - _start + _START_OFFSET
1124         bl      trap_reloc
1125         li      r7,.L_Decrementer - _start + _START_OFFSET
1126         bl      trap_reloc
1127         li      r7,.L_IntervalTimer - _start + _START_OFFSET
1128         li      r8,_end_of_vectors - _start + _START_OFFSET
1129 2:
1130         bl      trap_reloc
1131         addi    r7,r7,0x100             /* next exception vector        */
1132         cmplw   0,r7,r8
1133         blt     2b
1134
1135         lis     r7,0x0
1136         mtspr   IVPR,r7
1137
1138         mtlr    r4                      /* restore link register        */
1139         blr
1140
1141 .globl unlock_ram_in_cache
1142 unlock_ram_in_cache:
1143         /* invalidate the INIT_RAM section */
1144         lis     r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1145         ori     r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1146         mfspr   r4,L1CFG0
1147         andi.   r4,r4,0x1ff
1148         slwi    r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1149         mtctr   r4
1150 1:      dcbi    r0,r3
1151         addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
1152         bdnz    1b
1153         sync
1154
1155         /* Invalidate the TLB entries for the cache */
1156         lis     r3,CONFIG_SYS_INIT_RAM_ADDR@h
1157         ori     r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1158         tlbivax 0,r3
1159         addi    r3,r3,0x1000
1160         tlbivax 0,r3
1161         addi    r3,r3,0x1000
1162         tlbivax 0,r3
1163         addi    r3,r3,0x1000
1164         tlbivax 0,r3
1165         isync
1166         blr
1167
1168 .globl flush_dcache
1169 flush_dcache:
1170         mfspr   r3,SPRN_L1CFG0
1171
1172         rlwinm  r5,r3,9,3       /* Extract cache block size */
1173         twlgti  r5,1            /* Only 32 and 64 byte cache blocks
1174                                  * are currently defined.
1175                                  */
1176         li      r4,32
1177         subfic  r6,r5,2         /* r6 = log2(1KiB / cache block size) -
1178                                  *      log2(number of ways)
1179                                  */
1180         slw     r5,r4,r5        /* r5 = cache block size */
1181
1182         rlwinm  r7,r3,0,0xff    /* Extract number of KiB in the cache */
1183         mulli   r7,r7,13        /* An 8-way cache will require 13
1184                                  * loads per set.
1185                                  */
1186         slw     r7,r7,r6
1187
1188         /* save off HID0 and set DCFA */
1189         mfspr   r8,SPRN_HID0
1190         ori     r9,r8,HID0_DCFA@l
1191         mtspr   SPRN_HID0,r9
1192         isync
1193
1194         lis     r4,0
1195         mtctr   r7
1196
1197 1:      lwz     r3,0(r4)        /* Load... */
1198         add     r4,r4,r5
1199         bdnz    1b
1200
1201         msync
1202         lis     r4,0
1203         mtctr   r7
1204
1205 1:      dcbf    0,r4            /* ...and flush. */
1206         add     r4,r4,r5
1207         bdnz    1b
1208
1209         /* restore HID0 */
1210         mtspr   SPRN_HID0,r8
1211         isync
1212
1213         blr
1214
1215 .globl setup_ivors
1216 setup_ivors:
1217
1218 #include "fixed_ivor.S"
1219         blr
1220 #endif /* !CONFIG_NAND_SPL */