arch/powerpc/cpu/mpc85xx/start.S

   1 /*
   2  * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2003  Motorola,Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
  25  *
  26  * The processor starts at 0xfffffffc and the code is first executed in the
  27  * last 4K page(0xfffff000-0xffffffff) in flash/rom.
  28  *
  29  */
  30
  31 #include <config.h>
  32 #include <mpc85xx.h>
  33 #include <timestamp.h>
  34 #include <version.h>
  35
  36 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  37
  38 #include <ppc_asm.tmpl>
  39 #include <ppc_defs.h>
  40
  41 #include <asm/cache.h>
  42 #include <asm/mmu.h>
  43
  44 #ifndef  CONFIG_IDENT_STRING
  45 #define  CONFIG_IDENT_STRING ""
  46 #endif
  47
  48 #undef  MSR_KERNEL
  49 #define MSR_KERNEL ( MSR_ME )   /* Machine Check */
  50
  51 /*
  52  * Set up GOT: Global Offset Table
  53  *
  54  * Use r12 to access the GOT
  55  */
  56         START_GOT
  57         GOT_ENTRY(_GOT2_TABLE_)
  58         GOT_ENTRY(_FIXUP_TABLE_)
  59
  60 #ifndef CONFIG_NAND_SPL
  61         GOT_ENTRY(_start)
  62         GOT_ENTRY(_start_of_vectors)
  63         GOT_ENTRY(_end_of_vectors)
  64         GOT_ENTRY(transfer_to_handler)
  65 #endif
  66
  67         GOT_ENTRY(__init_end)
  68         GOT_ENTRY(_end)
  69         GOT_ENTRY(__bss_start)
  70         END_GOT
  71
  72 /*
  73  * e500 Startup -- after reset only the last 4KB of the effective
  74  * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
  75  * section is located at THIS LAST page and basically does three
  76  * things: clear some registers, set up exception tables and
  77  * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
  78  * continue the boot procedure.
  79
  80  * Once the boot rom is mapped by TLB entries we can proceed
  81  * with normal startup.
  82  *
  83  */
  84
  85         .section .bootpg,"ax"
  86         .globl _start_e500
  87
  88 _start_e500:
  89
  90 /* clear registers/arrays not reset by hardware */
  91
  92         /* L1 */
  93         li      r0,2
  94         mtspr   L1CSR0,r0       /* invalidate d-cache */
  95         mtspr   L1CSR1,r0       /* invalidate i-cache */
  96
  97         mfspr   r1,DBSR
  98         mtspr   DBSR,r1         /* Clear all valid bits */
  99
 100         /*
 101          *      Enable L1 Caches early
 102          *
 103          */
 104
 105 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
 106         /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
 107         li      r2,(32 + 0)
 108         mtspr   L1CSR2,r2
 109 #endif
 110
 111         /* Enable/invalidate the I-Cache */
 112         lis     r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
 113         ori     r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
 114         mtspr   SPRN_L1CSR1,r2
 115 1:
 116         mfspr   r3,SPRN_L1CSR1
 117         and.    r1,r3,r2
 118         bne     1b
 119
 120         lis     r3,(L1CSR1_CPE|L1CSR1_ICE)@h
 121         ori     r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
 122         mtspr   SPRN_L1CSR1,r3
 123         isync
 124 2:
 125         mfspr   r3,SPRN_L1CSR1
 126         andi.   r1,r3,L1CSR1_ICE@l
 127         beq     2b
 128
 129         /* Enable/invalidate the D-Cache */
 130         lis     r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
 131         ori     r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
 132         mtspr   SPRN_L1CSR0,r2
 133 1:
 134         mfspr   r3,SPRN_L1CSR0
 135         and.    r1,r3,r2
 136         bne     1b
 137
 138         lis     r3,(L1CSR0_CPE|L1CSR0_DCE)@h
 139         ori     r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
 140         mtspr   SPRN_L1CSR0,r3
 141         isync
 142 2:
 143         mfspr   r3,SPRN_L1CSR0
 144         andi.   r1,r3,L1CSR0_DCE@l
 145         beq     2b
 146
 147         /* Setup interrupt vectors */
 148         lis     r1,CONFIG_SYS_TEXT_BASE@h
 149         mtspr   IVPR,r1
 150
 151         li      r1,0x0100
 152         mtspr   IVOR0,r1        /* 0: Critical input */
 153         li      r1,0x0200
 154         mtspr   IVOR1,r1        /* 1: Machine check */
 155         li      r1,0x0300
 156         mtspr   IVOR2,r1        /* 2: Data storage */
 157         li      r1,0x0400
 158         mtspr   IVOR3,r1        /* 3: Instruction storage */
 159         li      r1,0x0500
 160         mtspr   IVOR4,r1        /* 4: External interrupt */
 161         li      r1,0x0600
 162         mtspr   IVOR5,r1        /* 5: Alignment */
 163         li      r1,0x0700
 164         mtspr   IVOR6,r1        /* 6: Program check */
 165         li      r1,0x0800
 166         mtspr   IVOR7,r1        /* 7: floating point unavailable */
 167         li      r1,0x0900
 168         mtspr   IVOR8,r1        /* 8: System call */
 169         /* 9: Auxiliary processor unavailable(unsupported) */
 170         li      r1,0x0a00
 171         mtspr   IVOR10,r1       /* 10: Decrementer */
 172         li      r1,0x0b00
 173         mtspr   IVOR11,r1       /* 11: Interval timer */
 174         li      r1,0x0c00
 175         mtspr   IVOR12,r1       /* 12: Watchdog timer */
 176         li      r1,0x0d00
 177         mtspr   IVOR13,r1       /* 13: Data TLB error */
 178         li      r1,0x0e00
 179         mtspr   IVOR14,r1       /* 14: Instruction TLB error */
 180         li      r1,0x0f00
 181         mtspr   IVOR15,r1       /* 15: Debug */
 182
 183         /* Clear and set up some registers. */
 184         li      r0,0x0000
 185         lis     r1,0xffff
 186         mtspr   DEC,r0                  /* prevent dec exceptions */
 187         mttbl   r0                      /* prevent fit & wdt exceptions */
 188         mttbu   r0
 189         mtspr   TSR,r1                  /* clear all timer exception status */
 190         mtspr   TCR,r0                  /* disable all */
 191         mtspr   ESR,r0                  /* clear exception syndrome register */
 192         mtspr   MCSR,r0                 /* machine check syndrome register */
 193         mtxer   r0                      /* clear integer exception register */
 194
 195 #ifdef CONFIG_SYS_BOOK3E_HV
 196         mtspr   MAS8,r0                 /* make sure MAS8 is clear */
 197 #endif
 198
 199         /* Enable Time Base and Select Time Base Clock */
 200         lis     r0,HID0_EMCP@h          /* Enable machine check */
 201 #if defined(CONFIG_ENABLE_36BIT_PHYS)
 202         ori     r0,r0,HID0_ENMAS7@l     /* Enable MAS7 */
 203 #endif
 204 #ifndef CONFIG_E500MC
 205         ori     r0,r0,HID0_TBEN@l       /* Enable Timebase */
 206 #endif
 207         mtspr   HID0,r0
 208
 209 #ifndef CONFIG_E500MC
 210         li      r0,(HID1_ASTME|HID1_ABE)@l      /* Addr streaming & broadcast */
 211         mfspr   r3,PVR
 212         andi.   r3,r3, 0xff
 213         cmpwi   r3,0x50@l       /* if we are rev 5.0 or greater set MBDD */
 214         blt 1f
 215         /* Set MBDD bit also */
 216         ori r0, r0, HID1_MBDD@l
 217 1:
 218         mtspr   HID1,r0
 219 #endif
 220
 221         /* Enable Branch Prediction */
 222 #if defined(CONFIG_BTB)
 223         lis     r0,BUCSR_ENABLE@h
 224         ori     r0,r0,BUCSR_ENABLE@l
 225         mtspr   SPRN_BUCSR,r0
 226 #endif
 227
 228 #if defined(CONFIG_SYS_INIT_DBCR)
 229         lis     r1,0xffff
 230         ori     r1,r1,0xffff
 231         mtspr   DBSR,r1                 /* Clear all status bits */
 232         lis     r0,CONFIG_SYS_INIT_DBCR@h       /* DBCR0[IDM] must be set */
 233         ori     r0,r0,CONFIG_SYS_INIT_DBCR@l
 234         mtspr   DBCR0,r0
 235 #endif
 236
 237 #ifdef CONFIG_MPC8569
 238 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
 239 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
 240
 241         /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
 242          * use address space which is more than 12bits, and it must be done in
 243          * the 4K boot page. So we set this bit here.
 244          */
 245
 246         /* create a temp mapping TLB0[0] for LBCR  */
 247         lis     r6,FSL_BOOKE_MAS0(0, 0, 0)@h
 248         ori     r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
 249
 250         lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
 251         ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
 252
 253         lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
 254         ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
 255
 256         lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
 257                                                 (MAS3_SX|MAS3_SW|MAS3_SR))@h
 258         ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
 259                                                 (MAS3_SX|MAS3_SW|MAS3_SR))@l
 260
 261         mtspr   MAS0,r6
 262         mtspr   MAS1,r7
 263         mtspr   MAS2,r8
 264         mtspr   MAS3,r9
 265         isync
 266         msync
 267         tlbwe
 268
 269         /* Set LBCR register */
 270         lis     r4,CONFIG_SYS_LBCR_ADDR@h
 271         ori     r4,r4,CONFIG_SYS_LBCR_ADDR@l
 272
 273         lis     r5,CONFIG_SYS_LBC_LBCR@h
 274         ori     r5,r5,CONFIG_SYS_LBC_LBCR@l
 275         stw     r5,0(r4)
 276         isync
 277
 278         /* invalidate this temp TLB */
 279         lis     r4,CONFIG_SYS_LBC_ADDR@h
 280         ori     r4,r4,CONFIG_SYS_LBC_ADDR@l
 281         tlbivax 0,r4
 282         isync
 283
 284 #endif /* CONFIG_MPC8569 */
 285
 286         lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
 287         ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 288
 289 #ifndef CONFIG_SYS_RAMBOOT
 290         /* create a temp mapping in AS=1 to the 4M boot window */
 291         lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
 292         ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
 293
 294         lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
 295         ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
 296
 297         /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
 298         lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 299         ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 300 #else
 301         /*
 302          * create a temp mapping in AS=1 to the 1M CONFIG_SYS_TEXT_BASE space, the main
 303          * image has been relocated to CONFIG_SYS_TEXT_BASE on the second stage.
 304          */
 305         lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
 306         ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
 307
 308         lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@h
 309         ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@l
 310
 311         lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 312         ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 313 #endif
 314
 315         mtspr   MAS0,r6
 316         mtspr   MAS1,r7
 317         mtspr   MAS2,r8
 318         mtspr   MAS3,r9
 319         isync
 320         msync
 321         tlbwe
 322
 323         /* create a temp mapping in AS=1 to the stack */
 324         lis     r6,FSL_BOOKE_MAS0(1, 14, 0)@h
 325         ori     r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
 326
 327         lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
 328         ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
 329
 330         lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
 331         ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
 332
 333 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
 334     defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
 335         lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
 336                                 (MAS3_SX|MAS3_SW|MAS3_SR))@h
 337         ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
 338                                 (MAS3_SX|MAS3_SW|MAS3_SR))@l
 339         li      r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
 340         mtspr   MAS7,r10
 341 #else
 342         lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 343         ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 344 #endif
 345
 346         mtspr   MAS0,r6
 347         mtspr   MAS1,r7
 348         mtspr   MAS2,r8
 349         mtspr   MAS3,r9
 350         isync
 351         msync
 352         tlbwe
 353
 354         lis     r6,MSR_IS|MSR_DS@h
 355         ori     r6,r6,MSR_IS|MSR_DS@l
 356         lis     r7,switch_as@h
 357         ori     r7,r7,switch_as@l
 358
 359         mtspr   SPRN_SRR0,r7
 360         mtspr   SPRN_SRR1,r6
 361         rfi
 362
 363 switch_as:
 364 /* L1 DCache is used for initial RAM */
 365
 366         /* Allocate Initial RAM in data cache.
 367          */
 368         lis     r3,CONFIG_SYS_INIT_RAM_ADDR@h
 369         ori     r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
 370         mfspr   r2, L1CFG0
 371         andi.   r2, r2, 0x1ff
 372         /* cache size * 1024 / (2 * L1 line size) */
 373         slwi    r2, r2, (10 - 1 - L1_CACHE_SHIFT)
 374         mtctr   r2
 375         li      r0,0
 376 1:
 377         dcbz    r0,r3
 378         dcbtls  0,r0,r3
 379         addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
 380         bdnz    1b
 381
 382         /* Jump out the last 4K page and continue to 'normal' start */
 383 #ifdef CONFIG_SYS_RAMBOOT
 384         b       _start_cont
 385 #else
 386         /* Calculate absolute address in FLASH and jump there           */
 387         /*--------------------------------------------------------------*/
 388         lis     r3,CONFIG_SYS_MONITOR_BASE@h
 389         ori     r3,r3,CONFIG_SYS_MONITOR_BASE@l
 390         addi    r3,r3,_start_cont - _start + _START_OFFSET
 391         mtlr    r3
 392         blr
 393 #endif
 394
 395         .text
 396         .globl  _start
 397 _start:
 398         .long   0x27051956              /* U-BOOT Magic Number */
 399         .globl  version_string
 400 version_string:
 401         .ascii U_BOOT_VERSION
 402         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
 403         .ascii CONFIG_IDENT_STRING, "\0"
 404
 405         .align  4
 406         .globl  _start_cont
 407 _start_cont:
 408         /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 409         lis     r1,CONFIG_SYS_INIT_RAM_ADDR@h
 410         ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
 411
 412         li      r0,0
 413         stwu    r0,-4(r1)
 414         stwu    r0,-4(r1)               /* Terminate call chain */
 415
 416         stwu    r1,-8(r1)               /* Save back chain and move SP */
 417         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 418         ori     r0,r0,RESET_VECTOR@l
 419         stwu    r1,-8(r1)               /* Save back chain and move SP */
 420         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 421
 422         GET_GOT
 423         bl      cpu_init_early_f
 424
 425         /* switch back to AS = 0 */
 426         lis     r3,(MSR_CE|MSR_ME|MSR_DE)@h
 427         ori     r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
 428         mtmsr   r3
 429         isync
 430
 431         bl      cpu_init_f
 432         bl      board_init_f
 433         isync
 434
 435         /* NOTREACHED - board_init_f() does not return */
 436
 437 #ifndef CONFIG_NAND_SPL
 438         . = EXC_OFF_SYS_RESET
 439         .globl  _start_of_vectors
 440 _start_of_vectors:
 441
 442 /* Critical input. */
 443         CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
 444
 445 /* Machine check */
 446         MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 447
 448 /* Data Storage exception. */
 449         STD_EXCEPTION(0x0300, DataStorage, UnknownException)
 450
 451 /* Instruction Storage exception. */
 452         STD_EXCEPTION(0x0400, InstStorage, UnknownException)
 453
 454 /* External Interrupt exception. */
 455         STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
 456
 457 /* Alignment exception. */
 458         . = 0x0600
 459 Alignment:
 460         EXCEPTION_PROLOG(SRR0, SRR1)
 461         mfspr   r4,DAR
 462         stw     r4,_DAR(r21)
 463         mfspr   r5,DSISR
 464         stw     r5,_DSISR(r21)
 465         addi    r3,r1,STACK_FRAME_OVERHEAD
 466         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 467
 468 /* Program check exception */
 469         . = 0x0700
 470 ProgramCheck:
 471         EXCEPTION_PROLOG(SRR0, SRR1)
 472         addi    r3,r1,STACK_FRAME_OVERHEAD
 473         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 474                 MSR_KERNEL, COPY_EE)
 475
 476         /* No FPU on MPC85xx.  This exception is not supposed to happen.
 477         */
 478         STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
 479
 480         . = 0x0900
 481 /*
 482  * r0 - SYSCALL number
 483  * r3-... arguments
 484  */
 485 SystemCall:
 486         addis   r11,r0,0        /* get functions table addr */
 487         ori     r11,r11,0       /* Note: this code is patched in trap_init */
 488         addis   r12,r0,0        /* get number of functions */
 489         ori     r12,r12,0
 490
 491         cmplw   0,r0,r12
 492         bge     1f
 493
 494         rlwinm  r0,r0,2,0,31    /* fn_addr = fn_tbl[r0] */
 495         add     r11,r11,r0
 496         lwz     r11,0(r11)
 497
 498         li      r20,0xd00-4     /* Get stack pointer */
 499         lwz     r12,0(r20)
 500         subi    r12,r12,12      /* Adjust stack pointer */
 501         li      r0,0xc00+_end_back-SystemCall
 502         cmplw   0,r0,r12        /* Check stack overflow */
 503         bgt     1f
 504         stw     r12,0(r20)
 505
 506         mflr    r0
 507         stw     r0,0(r12)
 508         mfspr   r0,SRR0
 509         stw     r0,4(r12)
 510         mfspr   r0,SRR1
 511         stw     r0,8(r12)
 512
 513         li      r12,0xc00+_back-SystemCall
 514         mtlr    r12
 515         mtspr   SRR0,r11
 516
 517 1:      SYNC
 518         rfi
 519 _back:
 520
 521         mfmsr   r11                     /* Disable interrupts */
 522         li      r12,0
 523         ori     r12,r12,MSR_EE
 524         andc    r11,r11,r12
 525         SYNC                            /* Some chip revs need this... */
 526         mtmsr   r11
 527         SYNC
 528
 529         li      r12,0xd00-4             /* restore regs */
 530         lwz     r12,0(r12)
 531
 532         lwz     r11,0(r12)
 533         mtlr    r11
 534         lwz     r11,4(r12)
 535         mtspr   SRR0,r11
 536         lwz     r11,8(r12)
 537         mtspr   SRR1,r11
 538
 539         addi    r12,r12,12              /* Adjust stack pointer */
 540         li      r20,0xd00-4
 541         stw     r12,0(r20)
 542
 543         SYNC
 544         rfi
 545 _end_back:
 546
 547         STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
 548         STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
 549         STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
 550
 551         STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
 552         STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
 553
 554         CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
 555
 556         .globl  _end_of_vectors
 557 _end_of_vectors:
 558
 559
 560         . = . + (0x100 - ( . & 0xff ))  /* align for debug */
 561
 562 /*
 563  * This code finishes saving the registers to the exception frame
 564  * and jumps to the appropriate handler for the exception.
 565  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 566  */
 567         .globl  transfer_to_handler
 568 transfer_to_handler:
 569         stw     r22,_NIP(r21)
 570         lis     r22,MSR_POW@h
 571         andc    r23,r23,r22
 572         stw     r23,_MSR(r21)
 573         SAVE_GPR(7, r21)
 574         SAVE_4GPRS(8, r21)
 575         SAVE_8GPRS(12, r21)
 576         SAVE_8GPRS(24, r21)
 577
 578         mflr    r23
 579         andi.   r24,r23,0x3f00          /* get vector offset */
 580         stw     r24,TRAP(r21)
 581         li      r22,0
 582         stw     r22,RESULT(r21)
 583         mtspr   SPRG2,r22               /* r1 is now kernel sp */
 584
 585         lwz     r24,0(r23)              /* virtual address of handler */
 586         lwz     r23,4(r23)              /* where to go when done */
 587         mtspr   SRR0,r24
 588         mtspr   SRR1,r20
 589         mtlr    r23
 590         SYNC
 591         rfi                             /* jump to handler, enable MMU */
 592
 593 int_return:
 594         mfmsr   r28             /* Disable interrupts */
 595         li      r4,0
 596         ori     r4,r4,MSR_EE
 597         andc    r28,r28,r4
 598         SYNC                    /* Some chip revs need this... */
 599         mtmsr   r28
 600         SYNC
 601         lwz     r2,_CTR(r1)
 602         lwz     r0,_LINK(r1)
 603         mtctr   r2
 604         mtlr    r0
 605         lwz     r2,_XER(r1)
 606         lwz     r0,_CCR(r1)
 607         mtspr   XER,r2
 608         mtcrf   0xFF,r0
 609         REST_10GPRS(3, r1)
 610         REST_10GPRS(13, r1)
 611         REST_8GPRS(23, r1)
 612         REST_GPR(31, r1)
 613         lwz     r2,_NIP(r1)     /* Restore environment */
 614         lwz     r0,_MSR(r1)
 615         mtspr   SRR0,r2
 616         mtspr   SRR1,r0
 617         lwz     r0,GPR0(r1)
 618         lwz     r2,GPR2(r1)
 619         lwz     r1,GPR1(r1)
 620         SYNC
 621         rfi
 622
 623 crit_return:
 624         mfmsr   r28             /* Disable interrupts */
 625         li      r4,0
 626         ori     r4,r4,MSR_EE
 627         andc    r28,r28,r4
 628         SYNC                    /* Some chip revs need this... */
 629         mtmsr   r28
 630         SYNC
 631         lwz     r2,_CTR(r1)
 632         lwz     r0,_LINK(r1)
 633         mtctr   r2
 634         mtlr    r0
 635         lwz     r2,_XER(r1)
 636         lwz     r0,_CCR(r1)
 637         mtspr   XER,r2
 638         mtcrf   0xFF,r0
 639         REST_10GPRS(3, r1)
 640         REST_10GPRS(13, r1)
 641         REST_8GPRS(23, r1)
 642         REST_GPR(31, r1)
 643         lwz     r2,_NIP(r1)     /* Restore environment */
 644         lwz     r0,_MSR(r1)
 645         mtspr   SPRN_CSRR0,r2
 646         mtspr   SPRN_CSRR1,r0
 647         lwz     r0,GPR0(r1)
 648         lwz     r2,GPR2(r1)
 649         lwz     r1,GPR1(r1)
 650         SYNC
 651         rfci
 652
 653 mck_return:
 654         mfmsr   r28             /* Disable interrupts */
 655         li      r4,0
 656         ori     r4,r4,MSR_EE
 657         andc    r28,r28,r4
 658         SYNC                    /* Some chip revs need this... */
 659         mtmsr   r28
 660         SYNC
 661         lwz     r2,_CTR(r1)
 662         lwz     r0,_LINK(r1)
 663         mtctr   r2
 664         mtlr    r0
 665         lwz     r2,_XER(r1)
 666         lwz     r0,_CCR(r1)
 667         mtspr   XER,r2
 668         mtcrf   0xFF,r0
 669         REST_10GPRS(3, r1)
 670         REST_10GPRS(13, r1)
 671         REST_8GPRS(23, r1)
 672         REST_GPR(31, r1)
 673         lwz     r2,_NIP(r1)     /* Restore environment */
 674         lwz     r0,_MSR(r1)
 675         mtspr   SPRN_MCSRR0,r2
 676         mtspr   SPRN_MCSRR1,r0
 677         lwz     r0,GPR0(r1)
 678         lwz     r2,GPR2(r1)
 679         lwz     r1,GPR1(r1)
 680         SYNC
 681         rfmci
 682
 683 /* Cache functions.
 684 */
 685 .globl invalidate_icache
 686 invalidate_icache:
 687         mfspr   r0,L1CSR1
 688         ori     r0,r0,L1CSR1_ICFI
 689         msync
 690         isync
 691         mtspr   L1CSR1,r0
 692         isync
 693         blr                             /* entire I cache */
 694
 695 .globl invalidate_dcache
 696 invalidate_dcache:
 697         mfspr   r0,L1CSR0
 698         ori     r0,r0,L1CSR0_DCFI
 699         msync
 700         isync
 701         mtspr   L1CSR0,r0
 702         isync
 703         blr
 704
 705         .globl  icache_enable
 706 icache_enable:
 707         mflr    r8
 708         bl      invalidate_icache
 709         mtlr    r8
 710         isync
 711         mfspr   r4,L1CSR1
 712         ori     r4,r4,0x0001
 713         oris    r4,r4,0x0001
 714         mtspr   L1CSR1,r4
 715         isync
 716         blr
 717
 718         .globl  icache_disable
 719 icache_disable:
 720         mfspr   r0,L1CSR1
 721         lis     r3,0
 722         ori     r3,r3,L1CSR1_ICE
 723         andc    r0,r0,r3
 724         mtspr   L1CSR1,r0
 725         isync
 726         blr
 727
 728         .globl  icache_status
 729 icache_status:
 730         mfspr   r3,L1CSR1
 731         andi.   r3,r3,L1CSR1_ICE
 732         blr
 733
 734         .globl  dcache_enable
 735 dcache_enable:
 736         mflr    r8
 737         bl      invalidate_dcache
 738         mtlr    r8
 739         isync
 740         mfspr   r0,L1CSR0
 741         ori     r0,r0,0x0001
 742         oris    r0,r0,0x0001
 743         msync
 744         isync
 745         mtspr   L1CSR0,r0
 746         isync
 747         blr
 748
 749         .globl  dcache_disable
 750 dcache_disable:
 751         mfspr   r3,L1CSR0
 752         lis     r4,0
 753         ori     r4,r4,L1CSR0_DCE
 754         andc    r3,r3,r4
 755         mtspr   L1CSR0,r0
 756         isync
 757         blr
 758
 759         .globl  dcache_status
 760 dcache_status:
 761         mfspr   r3,L1CSR0
 762         andi.   r3,r3,L1CSR0_DCE
 763         blr
 764
 765         .globl get_pir
 766 get_pir:
 767         mfspr   r3,PIR
 768         blr
 769
 770         .globl get_pvr
 771 get_pvr:
 772         mfspr   r3,PVR
 773         blr
 774
 775         .globl get_svr
 776 get_svr:
 777         mfspr   r3,SVR
 778         blr
 779
 780         .globl wr_tcr
 781 wr_tcr:
 782         mtspr   TCR,r3
 783         blr
 784
 785 /*------------------------------------------------------------------------------- */
 786 /* Function:     in8 */
 787 /* Description:  Input 8 bits */
 788 /*------------------------------------------------------------------------------- */
 789         .globl  in8
 790 in8:
 791         lbz     r3,0x0000(r3)
 792         blr
 793
 794 /*------------------------------------------------------------------------------- */
 795 /* Function:     out8 */
 796 /* Description:  Output 8 bits */
 797 /*------------------------------------------------------------------------------- */
 798         .globl  out8
 799 out8:
 800         stb     r4,0x0000(r3)
 801         sync
 802         blr
 803
 804 /*------------------------------------------------------------------------------- */
 805 /* Function:     out16 */
 806 /* Description:  Output 16 bits */
 807 /*------------------------------------------------------------------------------- */
 808         .globl  out16
 809 out16:
 810         sth     r4,0x0000(r3)
 811         sync
 812         blr
 813
 814 /*------------------------------------------------------------------------------- */
 815 /* Function:     out16r */
 816 /* Description:  Byte reverse and output 16 bits */
 817 /*------------------------------------------------------------------------------- */
 818         .globl  out16r
 819 out16r:
 820         sthbrx  r4,r0,r3
 821         sync
 822         blr
 823
 824 /*------------------------------------------------------------------------------- */
 825 /* Function:     out32 */
 826 /* Description:  Output 32 bits */
 827 /*------------------------------------------------------------------------------- */
 828         .globl  out32
 829 out32:
 830         stw     r4,0x0000(r3)
 831         sync
 832         blr
 833
 834 /*------------------------------------------------------------------------------- */
 835 /* Function:     out32r */
 836 /* Description:  Byte reverse and output 32 bits */
 837 /*------------------------------------------------------------------------------- */
 838         .globl  out32r
 839 out32r:
 840         stwbrx  r4,r0,r3
 841         sync
 842         blr
 843
 844 /*------------------------------------------------------------------------------- */
 845 /* Function:     in16 */
 846 /* Description:  Input 16 bits */
 847 /*------------------------------------------------------------------------------- */
 848         .globl  in16
 849 in16:
 850         lhz     r3,0x0000(r3)
 851         blr
 852
 853 /*------------------------------------------------------------------------------- */
 854 /* Function:     in16r */
 855 /* Description:  Input 16 bits and byte reverse */
 856 /*------------------------------------------------------------------------------- */
 857         .globl  in16r
 858 in16r:
 859         lhbrx   r3,r0,r3
 860         blr
 861
 862 /*------------------------------------------------------------------------------- */
 863 /* Function:     in32 */
 864 /* Description:  Input 32 bits */
 865 /*------------------------------------------------------------------------------- */
 866         .globl  in32
 867 in32:
 868         lwz     3,0x0000(3)
 869         blr
 870
 871 /*------------------------------------------------------------------------------- */
 872 /* Function:     in32r */
 873 /* Description:  Input 32 bits and byte reverse */
 874 /*------------------------------------------------------------------------------- */
 875         .globl  in32r
 876 in32r:
 877         lwbrx   r3,r0,r3
 878         blr
 879 #endif  /* !CONFIG_NAND_SPL */
 880
 881 /*------------------------------------------------------------------------------*/
 882
 883 /*
 884  * void write_tlb(mas0, mas1, mas2, mas3, mas7)
 885  */
 886         .globl  write_tlb
 887 write_tlb:
 888         mtspr   MAS0,r3
 889         mtspr   MAS1,r4
 890         mtspr   MAS2,r5
 891         mtspr   MAS3,r6
 892 #ifdef CONFIG_ENABLE_36BIT_PHYS
 893         mtspr   MAS7,r7
 894 #endif
 895         li      r3,0
 896 #ifdef CONFIG_SYS_BOOK3E_HV
 897         mtspr   MAS8,r3
 898 #endif
 899         isync
 900         tlbwe
 901         msync
 902         isync
 903         blr
 904
 905 /*
 906  * void relocate_code (addr_sp, gd, addr_moni)
 907  *
 908  * This "function" does not return, instead it continues in RAM
 909  * after relocating the monitor code.
 910  *
 911  * r3 = dest
 912  * r4 = src
 913  * r5 = length in bytes
 914  * r6 = cachelinesize
 915  */
 916         .globl  relocate_code
 917 relocate_code:
 918         mr      r1,r3           /* Set new stack pointer                */
 919         mr      r9,r4           /* Save copy of Init Data pointer       */
 920         mr      r10,r5          /* Save copy of Destination Address     */
 921
 922         GET_GOT
 923         mr      r3,r5                           /* Destination Address  */
 924         lis     r4,CONFIG_SYS_MONITOR_BASE@h            /* Source      Address  */
 925         ori     r4,r4,CONFIG_SYS_MONITOR_BASE@l
 926         lwz     r5,GOT(__init_end)
 927         sub     r5,r5,r4
 928         li      r6,CONFIG_SYS_CACHELINE_SIZE            /* Cache Line Size      */
 929
 930         /*
 931          * Fix GOT pointer:
 932          *
 933          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 934          *
 935          * Offset:
 936          */
 937         sub     r15,r10,r4
 938
 939         /* First our own GOT */
 940         add     r12,r12,r15
 941         /* the the one used by the C code */
 942         add     r30,r30,r15
 943
 944         /*
 945          * Now relocate code
 946          */
 947
 948         cmplw   cr1,r3,r4
 949         addi    r0,r5,3
 950         srwi.   r0,r0,2
 951         beq     cr1,4f          /* In place copy is not necessary       */
 952         beq     7f              /* Protect against 0 count              */
 953         mtctr   r0
 954         bge     cr1,2f
 955
 956         la      r8,-4(r4)
 957         la      r7,-4(r3)
 958 1:      lwzu    r0,4(r8)
 959         stwu    r0,4(r7)
 960         bdnz    1b
 961         b       4f
 962
 963 2:      slwi    r0,r0,2
 964         add     r8,r4,r0
 965         add     r7,r3,r0
 966 3:      lwzu    r0,-4(r8)
 967         stwu    r0,-4(r7)
 968         bdnz    3b
 969
 970 /*
 971  * Now flush the cache: note that we must start from a cache aligned
 972  * address. Otherwise we might miss one cache line.
 973  */
 974 4:      cmpwi   r6,0
 975         add     r5,r3,r5
 976         beq     7f              /* Always flush prefetch queue in any case */
 977         subi    r0,r6,1
 978         andc    r3,r3,r0
 979         mr      r4,r3
 980 5:      dcbst   0,r4
 981         add     r4,r4,r6
 982         cmplw   r4,r5
 983         blt     5b
 984         sync                    /* Wait for all dcbst to complete on bus */
 985         mr      r4,r3
 986 6:      icbi    0,r4
 987         add     r4,r4,r6
 988         cmplw   r4,r5
 989         blt     6b
 990 7:      sync                    /* Wait for all icbi to complete on bus */
 991         isync
 992
 993         /*
 994          * Re-point the IVPR at RAM
 995          */
 996         mtspr   IVPR,r10
 997
 998 /*
 999  * We are done. Do not return, instead branch to second part of board
1000  * initialization, now running from RAM.
1001  */
1002
1003         addi    r0,r10,in_ram - _start + _START_OFFSET
1004         mtlr    r0
1005         blr                             /* NEVER RETURNS! */
1006         .globl  in_ram
1007 in_ram:
1008
1009         /*
1010          * Relocation Function, r12 point to got2+0x8000
1011          *
1012          * Adjust got2 pointers, no need to check for 0, this code
1013          * already puts a few entries in the table.
1014          */
1015         li      r0,__got2_entries@sectoff@l
1016         la      r3,GOT(_GOT2_TABLE_)
1017         lwz     r11,GOT(_GOT2_TABLE_)
1018         mtctr   r0
1019         sub     r11,r3,r11
1020         addi    r3,r3,-4
1021 1:      lwzu    r0,4(r3)
1022         cmpwi   r0,0
1023         beq-    2f
1024         add     r0,r0,r11
1025         stw     r0,0(r3)
1026 2:      bdnz    1b
1027
1028         /*
1029          * Now adjust the fixups and the pointers to the fixups
1030          * in case we need to move ourselves again.
1031          */
1032         li      r0,__fixup_entries@sectoff@l
1033         lwz     r3,GOT(_FIXUP_TABLE_)
1034         cmpwi   r0,0
1035         mtctr   r0
1036         addi    r3,r3,-4
1037         beq     4f
1038 3:      lwzu    r4,4(r3)
1039         lwzux   r0,r4,r11
1040         add     r0,r0,r11
1041         stw     r10,0(r3)
1042         stw     r0,0(r4)
1043         bdnz    3b
1044 4:
1045 clear_bss:
1046         /*
1047          * Now clear BSS segment
1048          */
1049         lwz     r3,GOT(__bss_start)
1050         lwz     r4,GOT(_end)
1051
1052         cmplw   0,r3,r4
1053         beq     6f
1054
1055         li      r0,0
1056 5:
1057         stw     r0,0(r3)
1058         addi    r3,r3,4
1059         cmplw   0,r3,r4
1060         bne     5b
1061 6:
1062
1063         mr      r3,r9           /* Init Data pointer            */
1064         mr      r4,r10          /* Destination Address          */
1065         bl      board_init_r
1066
1067 #ifndef CONFIG_NAND_SPL
1068         /*
1069          * Copy exception vector code to low memory
1070          *
1071          * r3: dest_addr
1072          * r7: source address, r8: end address, r9: target address
1073          */
1074         .globl  trap_init
1075 trap_init:
1076         mflr    r4                      /* save link register           */
1077         GET_GOT
1078         lwz     r7,GOT(_start_of_vectors)
1079         lwz     r8,GOT(_end_of_vectors)
1080
1081         li      r9,0x100                /* reset vector always at 0x100 */
1082
1083         cmplw   0,r7,r8
1084         bgelr                           /* return if r7>=r8 - just in case */
1085 1:
1086         lwz     r0,0(r7)
1087         stw     r0,0(r9)
1088         addi    r7,r7,4
1089         addi    r9,r9,4
1090         cmplw   0,r7,r8
1091         bne     1b
1092
1093         /*
1094          * relocate `hdlr' and `int_return' entries
1095          */
1096         li      r7,.L_CriticalInput - _start + _START_OFFSET
1097         bl      trap_reloc
1098         li      r7,.L_MachineCheck - _start + _START_OFFSET
1099         bl      trap_reloc
1100         li      r7,.L_DataStorage - _start + _START_OFFSET
1101         bl      trap_reloc
1102         li      r7,.L_InstStorage - _start + _START_OFFSET
1103         bl      trap_reloc
1104         li      r7,.L_ExtInterrupt - _start + _START_OFFSET
1105         bl      trap_reloc
1106         li      r7,.L_Alignment - _start + _START_OFFSET
1107         bl      trap_reloc
1108         li      r7,.L_ProgramCheck - _start + _START_OFFSET
1109         bl      trap_reloc
1110         li      r7,.L_FPUnavailable - _start + _START_OFFSET
1111         bl      trap_reloc
1112         li      r7,.L_Decrementer - _start + _START_OFFSET
1113         bl      trap_reloc
1114         li      r7,.L_IntervalTimer - _start + _START_OFFSET
1115         li      r8,_end_of_vectors - _start + _START_OFFSET
1116 2:
1117         bl      trap_reloc
1118         addi    r7,r7,0x100             /* next exception vector        */
1119         cmplw   0,r7,r8
1120         blt     2b
1121
1122         lis     r7,0x0
1123         mtspr   IVPR,r7
1124
1125         mtlr    r4                      /* restore link register        */
1126         blr
1127
1128 .globl unlock_ram_in_cache
1129 unlock_ram_in_cache:
1130         /* invalidate the INIT_RAM section */
1131         lis     r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1132         ori     r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1133         mfspr   r4,L1CFG0
1134         andi.   r4,r4,0x1ff
1135         slwi    r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1136         mtctr   r4
1137 1:      dcbi    r0,r3
1138         addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
1139         bdnz    1b
1140         sync
1141
1142         /* Invalidate the TLB entries for the cache */
1143         lis     r3,CONFIG_SYS_INIT_RAM_ADDR@h
1144         ori     r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1145         tlbivax 0,r3
1146         addi    r3,r3,0x1000
1147         tlbivax 0,r3
1148         addi    r3,r3,0x1000
1149         tlbivax 0,r3
1150         addi    r3,r3,0x1000
1151         tlbivax 0,r3
1152         isync
1153         blr
1154
1155 .globl flush_dcache
1156 flush_dcache:
1157         mfspr   r3,SPRN_L1CFG0
1158
1159         rlwinm  r5,r3,9,3       /* Extract cache block size */
1160         twlgti  r5,1            /* Only 32 and 64 byte cache blocks
1161                                  * are currently defined.
1162                                  */
1163         li      r4,32
1164         subfic  r6,r5,2         /* r6 = log2(1KiB / cache block size) -
1165                                  *      log2(number of ways)
1166                                  */
1167         slw     r5,r4,r5        /* r5 = cache block size */
1168
1169         rlwinm  r7,r3,0,0xff    /* Extract number of KiB in the cache */
1170         mulli   r7,r7,13        /* An 8-way cache will require 13
1171                                  * loads per set.
1172                                  */
1173         slw     r7,r7,r6
1174
1175         /* save off HID0 and set DCFA */
1176         mfspr   r8,SPRN_HID0
1177         ori     r9,r8,HID0_DCFA@l
1178         mtspr   SPRN_HID0,r9
1179         isync
1180
1181         lis     r4,0
1182         mtctr   r7
1183
1184 1:      lwz     r3,0(r4)        /* Load... */
1185         add     r4,r4,r5
1186         bdnz    1b
1187
1188         msync
1189         lis     r4,0
1190         mtctr   r7
1191
1192 1:      dcbf    0,r4            /* ...and flush. */
1193         add     r4,r4,r5
1194         bdnz    1b
1195
1196         /* restore HID0 */
1197         mtspr   SPRN_HID0,r8
1198         isync
1199
1200         blr
1201
1202 .globl setup_ivors
1203 setup_ivors:
1204
1205 #include "fixed_ivor.S"
1206         blr
1207 #endif /* !CONFIG_NAND_SPL */