2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
42 #include <asm/cache.h>
44 #if defined(CONFIG_OF_LIBFDT)
46 #include <libfdt_env.h>
47 #include <fdt_support.h>
50 DECLARE_GLOBAL_DATA_PTR
;
52 static char *cpu_warning
= "\n " \
53 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
55 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
56 !defined(CONFIG_MPC862))
58 static int check_CPU (long clock
, uint pvr
, uint immr
)
61 # if defined(CONFIG_MPC855)
63 # elif defined(CONFIG_MPC860P)
68 volatile immap_t
*immap
= (immap_t
*) (immr
& 0xFFFF0000);
75 /* the highest 16 bits should be 0x0050 for a 860 */
77 if ((pvr
>> 16) != 0x0050)
80 k
= (immr
<< 16) | *((ushort
*) & immap
->im_cpm
.cp_dparam
[0xB0]);
85 * Some boards use sockets so different CPUs can be used.
86 * We have to check chip version in run time.
89 case 0x00020001: pre
= 'P'; break;
90 case 0x00030001: break;
91 case 0x00120003: suf
= "A"; break;
92 case 0x00130003: suf
= "A3"; break;
94 case 0x00200004: suf
= "B"; break;
96 case 0x00300004: suf
= "C"; break;
97 case 0x00310004: suf
= "C1"; m
= 1; break;
99 case 0x00200064: mid
= "SR"; suf
= "B"; break;
100 case 0x00300065: mid
= "SR"; suf
= "C"; break;
101 case 0x00310065: mid
= "SR"; suf
= "C1"; m
= 1; break;
102 case 0x05010000: suf
= "D3"; m
= 1; break;
103 case 0x05020000: suf
= "D4"; m
= 1; break;
104 /* this value is not documented anywhere */
105 case 0x40000000: pre
= 'P'; suf
= "D"; m
= 1; break;
106 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
107 case 0x08010004: /* Rev. A.0 */
110 case 0x08000003: /* Rev. 0.3 */
114 # if defined(CONFIG_MPC852T)
116 # elif defined(CONFIG_MPC859T)
118 # elif defined(CONFIG_MPC859DSL)
120 # elif defined(CONFIG_MPC866T)
123 "PC866x"; /* Unknown chip from MPC866 family */
126 case 0x09000000: pre
= 'M'; mid
= suf
= ""; m
= 1;
128 id_str
= "PC885"; /* 870/875/880/885 */
131 default: suf
= NULL
; break;
135 id_str
= "PC86x"; /* Unknown 86x chip */
137 printf ("%c%s%sZPnn%s", pre
, id_str
, mid
, suf
);
139 printf ("unknown M%s (0x%08x)", id_str
, k
);
142 #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
143 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
145 CONFIG_SYS_8xx_CPUCLK_MIN
/ 1000000,
146 ((CONFIG_SYS_8xx_CPUCLK_MIN
% 1000000) + 50000) / 100000,
147 CONFIG_SYS_8xx_CPUCLK_MAX
/ 1000000,
148 ((CONFIG_SYS_8xx_CPUCLK_MAX
% 1000000) + 50000) / 100000
151 printf (" at %s MHz: ", strmhz (buf
, clock
));
153 printf ("%u kB I-Cache %u kB D-Cache",
154 checkicache () >> 10,
158 /* do we have a FEC (860T/P or 852/859/866/885)? */
160 immap
->im_cpm
.cp_fec
.fec_addr_low
= 0x12345678;
161 if (immap
->im_cpm
.cp_fec
.fec_addr_low
== 0x12345678) {
162 printf (" FEC present");
172 if(clock
!= measure_gclk()) {
173 printf ("clock %ldHz != %dHz\n", clock
, measure_gclk());
180 #elif defined(CONFIG_MPC862)
182 static int check_CPU (long clock
, uint pvr
, uint immr
)
184 volatile immap_t
*immap
= (immap_t
*) (immr
& 0xFFFF0000);
191 /* the highest 16 bits should be 0x0050 for a 8xx */
193 if ((pvr
>> 16) != 0x0050)
196 k
= (immr
<< 16) | *((ushort
*) & immap
->im_cpm
.cp_dparam
[0xB0]);
201 /* this value is not documented anywhere */
202 case 0x06000000: mid
= "P"; suf
= "0"; break;
203 case 0x06010001: mid
= "P"; suf
= "A"; m
= 1; break;
204 case 0x07000003: mid
= "P"; suf
= "B"; m
= 1; break;
205 default: suf
= NULL
; break;
208 #ifndef CONFIG_MPC857
210 printf ("%cPC862%sZPnn%s", pre
, mid
, suf
);
212 printf ("unknown MPC862 (0x%08x)", k
);
215 printf ("%cPC857TZPnn%s", pre
, suf
); /* only 857T tested right now! */
217 printf ("unknown MPC857 (0x%08x)", k
);
220 printf (" at %s MHz:", strmhz (buf
, clock
));
222 printf (" %u kB I-Cache", checkicache () >> 10);
223 printf (" %u kB D-Cache", checkdcache () >> 10);
225 /* lets check and see if we're running on a 862T (or P?) */
227 immap
->im_cpm
.cp_fec
.fec_addr_low
= 0x12345678;
228 if (immap
->im_cpm
.cp_fec
.fec_addr_low
== 0x12345678) {
229 printf (" FEC present");
241 #elif defined(CONFIG_MPC823)
243 static int check_CPU (long clock
, uint pvr
, uint immr
)
245 volatile immap_t
*immap
= (immap_t
*) (immr
& 0xFFFF0000);
250 /* the highest 16 bits should be 0x0050 for a 8xx */
252 if ((pvr
>> 16) != 0x0050)
255 k
= (immr
<< 16) | *((ushort
*) & immap
->im_cpm
.cp_dparam
[0xB0]);
260 case 0x20000000: suf
= "0"; break;
261 case 0x20010000: suf
= "0.1"; break;
262 case 0x20020000: suf
= "Z2/3"; break;
263 case 0x20020001: suf
= "Z3"; break;
264 case 0x21000000: suf
= "A"; break;
265 case 0x21010000: suf
= "B"; m
= 1; break;
266 case 0x21010001: suf
= "B2"; m
= 1; break;
268 case 0x24010000: suf
= NULL
;
269 puts ("PPC823EZTnnB2");
274 printf ("unknown MPC823 (0x%08x)", k
);
278 printf ("PPC823ZTnn%s", suf
);
280 printf (" at %s MHz:", strmhz (buf
, clock
));
282 printf (" %u kB I-Cache", checkicache () >> 10);
283 printf (" %u kB D-Cache", checkdcache () >> 10);
285 /* lets check and see if we're running on a 860T (or P?) */
287 immap
->im_cpm
.cp_fec
.fec_addr_low
= 0x12345678;
288 if (immap
->im_cpm
.cp_fec
.fec_addr_low
== 0x12345678) {
289 puts (" FEC present");
301 #elif defined(CONFIG_MPC850)
303 static int check_CPU (long clock
, uint pvr
, uint immr
)
305 volatile immap_t
*immap
= (immap_t
*) (immr
& 0xFFFF0000);
309 /* the highest 16 bits should be 0x0050 for a 8xx */
311 if ((pvr
>> 16) != 0x0050)
314 k
= (immr
<< 16) | *((ushort
*) & immap
->im_cpm
.cp_dparam
[0xB0]);
319 printf ("XPC850xxZT");
322 printf ("XPC850xxZTA");
325 printf ("XPC850xxZTB");
329 printf ("XPC850xxZTC");
333 printf ("unknown MPC850 (0x%08x)", k
);
335 printf (" at %s MHz:", strmhz (buf
, clock
));
337 printf (" %u kB I-Cache", checkicache () >> 10);
338 printf (" %u kB D-Cache", checkdcache () >> 10);
340 /* lets check and see if we're running on a 850T (or P?) */
342 immap
->im_cpm
.cp_fec
.fec_addr_low
= 0x12345678;
343 if (immap
->im_cpm
.cp_fec
.fec_addr_low
== 0x12345678) {
344 printf (" FEC present");
358 /* ------------------------------------------------------------------------- */
362 ulong clock
= gd
->cpu_clk
;
363 uint immr
= get_immr (0); /* Return full IMMR contents */
364 uint pvr
= get_pvr ();
368 /* 850 has PARTNUM 20 */
369 /* 801 has PARTNUM 10 */
370 return check_CPU (clock
, pvr
, immr
);
373 /* ------------------------------------------------------------------------- */
375 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
376 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
378 int checkicache (void)
380 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
381 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
382 u32 cacheon
= rd_ic_cst () & IDC_ENABLED
;
385 u32 k
= memctl
->memc_br1
& ~0x00007fff; /* probe in flash memoryarea */
387 u32 k
= memctl
->memc_br0
& ~0x00007fff; /* probe in flash memoryarea */
392 wr_ic_cst (IDC_UNALL
);
393 wr_ic_cst (IDC_INVALL
);
394 wr_ic_cst (IDC_DISABLE
);
395 __asm__
volatile ("isync");
397 while (!((m
= rd_ic_cst ()) & IDC_CERR2
)) {
399 wr_ic_cst (IDC_LDLCK
);
400 __asm__
volatile ("isync");
403 k
+= 0x10; /* the number of bytes in a cacheline */
406 wr_ic_cst (IDC_UNALL
);
407 wr_ic_cst (IDC_INVALL
);
410 wr_ic_cst (IDC_ENABLE
);
412 wr_ic_cst (IDC_DISABLE
);
414 __asm__
volatile ("isync");
419 /* ------------------------------------------------------------------------- */
421 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
422 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
423 /* call with cache disabled */
425 int checkdcache (void)
427 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
428 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
429 u32 cacheon
= rd_dc_cst () & IDC_ENABLED
;
432 u32 k
= memctl
->memc_br1
& ~0x00007fff; /* probe in flash memoryarea */
434 u32 k
= memctl
->memc_br0
& ~0x00007fff; /* probe in flash memoryarea */
439 wr_dc_cst (IDC_UNALL
);
440 wr_dc_cst (IDC_INVALL
);
441 wr_dc_cst (IDC_DISABLE
);
443 while (!((m
= rd_dc_cst ()) & IDC_CERR2
)) {
445 wr_dc_cst (IDC_LDLCK
);
447 k
+= 0x10; /* the number of bytes in a cacheline */
450 wr_dc_cst (IDC_UNALL
);
451 wr_dc_cst (IDC_INVALL
);
454 wr_dc_cst (IDC_ENABLE
);
456 wr_dc_cst (IDC_DISABLE
);
461 /* ------------------------------------------------------------------------- */
463 void upmconfig (uint upm
, uint
* table
, uint size
)
467 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
468 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
470 for (i
= 0; i
< size
; i
++) {
471 memctl
->memc_mdr
= table
[i
]; /* (16-15) */
472 memctl
->memc_mcr
= addr
| upm
; /* (16-16) */
477 /* ------------------------------------------------------------------------- */
481 int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
485 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
487 immap
->im_clkrst
.car_plprcr
|= PLPRCR_CSR
; /* Checkstop Reset enable */
489 /* Interrupts and MMU off */
490 __asm__
volatile ("mtspr 81, 0");
491 __asm__
volatile ("mfmsr %0":"=r" (msr
));
494 __asm__
volatile ("mtmsr %0"::"r" (msr
));
497 * Trying to execute the next instruction at a non-existing address
498 * should cause a machine check, resulting in reset
500 #ifdef CONFIG_SYS_RESET_ADDRESS
501 addr
= CONFIG_SYS_RESET_ADDRESS
;
504 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
505 * - sizeof (ulong) is usually a valid address. Better pick an address
506 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
507 * "(ulong)-1" used to be a good choice for many systems...
509 addr
= CONFIG_SYS_MONITOR_BASE
- sizeof (ulong
);
511 ((void (*)(void)) addr
) ();
515 #else /* CONFIG_LWMON */
518 * On the LWMON board, the MCLR reset input of the PIC's on the board
519 * uses a 47K/1n RC combination which has a 47us time constant. The
520 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
521 * and thus too short to reset the external hardware. So we use the
522 * watchdog to reset the board.
524 int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
526 /* prevent triggering the watchdog */
527 disable_interrupts ();
529 /* make sure the watchdog is running */
530 reset_8xx_watchdog ((immap_t
*) CONFIG_SYS_IMMR
);
532 /* wait for watchdog reset */
539 #endif /* CONFIG_LWMON */
541 /* ------------------------------------------------------------------------- */
544 * Get timebase clock frequency (like cpu_clk in Hz)
546 * See sections 14.2 and 14.6 of the User's Manual
548 unsigned long get_tbclk (void)
550 uint immr
= get_immr (0); /* Return full IMMR contents */
551 volatile immap_t
*immap
= (volatile immap_t
*)(immr
& 0xFFFF0000);
552 ulong oscclk
, factor
, pll
;
554 if (immap
->im_clkrst
.car_sccr
& SCCR_TBS
) {
555 return (gd
->cpu_clk
/ 16);
558 pll
= immap
->im_clkrst
.car_plprcr
;
560 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
563 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
564 * factor is calculated as follows:
569 * factor = -----------------
572 * For older chips, it's just MF field of PLPRCR plus one.
574 if ((immr
& 0x0FFF) >= MPC8xx_NEW_CLK
) { /* MPC866/87x/88x series */
575 factor
= (PLPRCR_val(MFI
) + PLPRCR_val(MFN
)/(PLPRCR_val(MFD
)+1))/
576 (PLPRCR_val(PDF
)+1) / (1<<PLPRCR_val(S
));
578 factor
= PLPRCR_val(MF
)+1;
581 oscclk
= gd
->cpu_clk
/ factor
;
583 if ((immap
->im_clkrst
.car_sccr
& SCCR_RTSEL
) == 0 || factor
> 2) {
586 return (oscclk
/ 16);
589 /* ------------------------------------------------------------------------- */
591 #if defined(CONFIG_WATCHDOG)
592 void watchdog_reset (void)
594 int re_enable
= disable_interrupts ();
596 reset_8xx_watchdog ((immap_t
*) CONFIG_SYS_IMMR
);
598 enable_interrupts ();
600 #endif /* CONFIG_WATCHDOG */
602 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
604 void reset_8xx_watchdog (volatile immap_t
* immr
)
606 # if defined(CONFIG_LWMON)
608 * The LWMON board uses a MAX6301 Watchdog
609 * with the trigger pin connected to port PA.7
611 * (The old board version used a MAX706TESA Watchdog, which
612 * had to be handled exactly the same.)
614 # define WATCHDOG_BIT 0x0100
615 immr
->im_ioport
.iop_papar
&= ~(WATCHDOG_BIT
); /* GPIO */
616 immr
->im_ioport
.iop_padir
|= WATCHDOG_BIT
; /* Output */
617 immr
->im_ioport
.iop_paodr
&= ~(WATCHDOG_BIT
); /* active output */
619 immr
->im_ioport
.iop_padat
^= WATCHDOG_BIT
; /* Toggle WDI */
620 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
622 * The KUP4 boards uses a TPS3705 Watchdog
623 * with the trigger pin connected to port PA.5
625 # define WATCHDOG_BIT 0x0400
626 immr
->im_ioport
.iop_papar
&= ~(WATCHDOG_BIT
); /* GPIO */
627 immr
->im_ioport
.iop_padir
|= WATCHDOG_BIT
; /* Output */
628 immr
->im_ioport
.iop_paodr
&= ~(WATCHDOG_BIT
); /* active output */
630 immr
->im_ioport
.iop_padat
^= WATCHDOG_BIT
; /* Toggle WDI */
633 * All other boards use the MPC8xx Internal Watchdog
635 immr
->im_siu_conf
.sc_swsr
= 0x556c; /* write magic1 */
636 immr
->im_siu_conf
.sc_swsr
= 0xaa39; /* write magic2 */
637 # endif /* CONFIG_LWMON */
639 #endif /* CONFIG_WATCHDOG */
642 * Initializes on-chip ethernet controllers.
643 * to override, implement board_eth_init()
645 int cpu_eth_init(bd_t
*bis
)
647 #if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
650 #if defined(FEC_ENET)