arch/powerpc/cpu/mpc8xx/cpu_init.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <watchdog.h>
  10
  11 #include <mpc8xx.h>
  12 #include <commproc.h>
  13
  14 /*
  15  * Breath some life into the CPU...
  16  *
  17  * Set up the memory map,
  18  * initialize a bunch of registers,
  19  * initialize the UPM's
  20  */
  21 void cpu_init_f (volatile immap_t * immr)
  22 {
  23         volatile memctl8xx_t *memctl = &immr->im_memctl;
  24 # ifdef CONFIG_SYS_PLPRCR
  25         ulong mfmask;
  26 # endif
  27         ulong reg;
  28
  29         /* SYPCR - contains watchdog control (11-9) */
  30
  31         immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
  32
  33 #if defined(CONFIG_WATCHDOG)
  34         reset_8xx_watchdog (immr);
  35 #endif /* CONFIG_WATCHDOG */
  36
  37         /* SIUMCR - contains debug pin configuration (11-6) */
  38         immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
  39         /* initialize timebase status and control register (11-26) */
  40         /* unlock TBSCRK */
  41
  42         immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
  43         immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
  44
  45         /* initialize the PIT (11-31) */
  46
  47         immr->im_sitk.sitk_piscrk = KAPWR_KEY;
  48         immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
  49
  50         /* System integration timers. Don't change EBDF! (15-27) */
  51
  52         immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
  53         reg = immr->im_clkrst.car_sccr;
  54         reg &= SCCR_MASK;
  55         reg |= CONFIG_SYS_SCCR;
  56         immr->im_clkrst.car_sccr = reg;
  57
  58         /* PLL (CPU clock) settings (15-30) */
  59
  60         immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
  61
  62         /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
  63          * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
  64          * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
  65          * field value.
  66          *
  67          * For newer (starting MPC866) chips PLPRCR layout is different.
  68          */
  69 #ifdef CONFIG_SYS_PLPRCR
  70            mfmask = PLPRCR_MFACT_MSK;
  71
  72         if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
  73            reg = CONFIG_SYS_PLPRCR;                     /* reset control bits   */
  74         else {
  75            reg = immr->im_clkrst.car_plprcr;
  76            reg &= mfmask;                       /* isolate MF-related fields */
  77            reg |= CONFIG_SYS_PLPRCR;                    /* reset control bits   */
  78         }
  79         immr->im_clkrst.car_plprcr = reg;
  80 #endif
  81
  82         /*
  83          * Memory Controller:
  84          */
  85
  86         /* perform BR0 reset that MPC850 Rev. A can't guarantee */
  87         reg = memctl->memc_br0;
  88         reg &= BR_PS_MSK;       /* Clear everything except Port Size bits */
  89         reg |= BR_V;            /* then add just the "Bank Valid" bit     */
  90         memctl->memc_br0 = reg;
  91
  92         /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
  93          * preliminary addresses - these have to be modified later
  94          * when FLASH size has been determined
  95          *
  96          * Depending on the size of the memory region defined by
  97          * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
  98          * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
  99          * map CONFIG_SYS_MONITOR_BASE.
 100          *
 101          * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
 102          * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
 103          *
 104          * If BR0 wasn't loaded with address base 0xff000000, then BR0's
 105          * base address remains as 0x00000000. However, the address mask
 106          * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
 107          * into the Bank0.
 108          *
 109          * This is why CONFIG_IVMS8 and similar boards must load BR0 with
 110          * CONFIG_SYS_BR0_PRELIM in advance.
 111          *
 112          * [Thanks to Michael Liao for this explanation.
 113          *  I owe him a free beer. - wd]
 114          */
 115
 116 #if defined(CONFIG_SYS_OR0_REMAP)
 117         memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
 118 #endif
 119 #if defined(CONFIG_SYS_OR1_REMAP)
 120         memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
 121 #endif
 122 #if defined(CONFIG_SYS_OR5_REMAP)
 123         memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
 124 #endif
 125
 126         /* now restrict to preliminary range */
 127         memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
 128         memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
 129
 130 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
 131         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 132         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 133 #endif
 134
 135 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 136         memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
 137         memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 138 #endif
 139
 140 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
 141         memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 142         memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 143 #endif
 144
 145 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
 146         memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
 147         memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
 148 #endif
 149
 150 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
 151         memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
 152         memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
 153 #endif
 154
 155 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
 156         memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
 157         memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
 158 #endif
 159
 160 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
 161         memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
 162         memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
 163 #endif
 164
 165         /*
 166          * Reset CPM
 167          */
 168         immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
 169         do {                    /* Spin until command processed     */
 170                 __asm__ ("eieio");
 171         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 172 }
 173
 174 /*
 175  * initialize higher level parts of CPU like timers
 176  */
 177 int cpu_init_r (void)
 178 {
 179         return (0);
 180 }