arch/powerpc/cpu/mpc8xx/fec.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <commproc.h>
  11 #include <malloc.h>
  12 #include <net.h>
  13
  14 #include <phy.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #if defined(CONFIG_CMD_NET) && \
  19         (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
  20
  21 /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
  22 #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
  23 #define CONFIG_ETHER_ON_FEC1 1
  24 #endif
  25
  26 /* define WANT_MII when MII support is required */
  27 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
  28 #define WANT_MII
  29 #else
  30 #undef WANT_MII
  31 #endif
  32
  33 #if defined(WANT_MII)
  34 #include <miiphy.h>
  35
  36 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  37 #error "CONFIG_MII has to be defined!"
  38 #endif
  39
  40 #endif
  41
  42 #if defined(CONFIG_RMII) && !defined(WANT_MII)
  43 #error RMII support is unusable without a working PHY.
  44 #endif
  45
  46 #ifdef CONFIG_SYS_DISCOVER_PHY
  47 static int mii_discover_phy(struct eth_device *dev);
  48 #endif
  49
  50 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
  51 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  52                         u16 value);
  53
  54 static struct ether_fcc_info_s
  55 {
  56         int ether_index;
  57         int fecp_offset;
  58         int phy_addr;
  59         int actual_phy_addr;
  60         int initialized;
  61 }
  62         ether_fcc_info[] = {
  63 #if defined(CONFIG_ETHER_ON_FEC1)
  64         {
  65                 0,
  66                 offsetof(immap_t, im_cpm.cp_fec1),
  67 #if defined(CONFIG_FEC1_PHY)
  68                 CONFIG_FEC1_PHY,
  69 #else
  70                 -1,     /* discover */
  71 #endif
  72                 -1,
  73                 0,
  74
  75         },
  76 #endif
  77 #if defined(CONFIG_ETHER_ON_FEC2)
  78         {
  79                 1,
  80                 offsetof(immap_t, im_cpm.cp_fec2),
  81 #if defined(CONFIG_FEC2_PHY)
  82                 CONFIG_FEC2_PHY,
  83 #else
  84                 -1,
  85 #endif
  86                 -1,
  87                 0,
  88         },
  89 #endif
  90 };
  91
  92 /* Ethernet Transmit and Receive Buffers */
  93 #define DBUF_LENGTH  1520
  94
  95 #define TX_BUF_CNT 2
  96
  97 #define TOUT_LOOP 100
  98
  99 #define PKT_MAXBUF_SIZE         1518
 100 #define PKT_MINBUF_SIZE         64
 101 #define PKT_MAXBLR_SIZE         1520
 102
 103 #ifdef __GNUC__
 104 static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
 105 #else
 106 #error txbuf must be aligned.
 107 #endif
 108
 109 static uint rxIdx;      /* index of the current RX buffer */
 110 static uint txIdx;      /* index of the current TX buffer */
 111
 112 /*
 113   * FEC Ethernet Tx and Rx buffer descriptors allocated at the
 114   *  immr->udata_bd address on Dual-Port RAM
 115   * Provide for Double Buffering
 116   */
 117
 118 typedef volatile struct CommonBufferDescriptor {
 119     cbd_t rxbd[PKTBUFSRX];              /* Rx BD */
 120     cbd_t txbd[TX_BUF_CNT];             /* Tx BD */
 121 } RTXBD;
 122
 123 static RTXBD *rtx = NULL;
 124
 125 static int fec_send(struct eth_device *dev, void *packet, int length);
 126 static int fec_recv(struct eth_device* dev);
 127 static int fec_init(struct eth_device* dev, bd_t * bd);
 128 static void fec_halt(struct eth_device* dev);
 129 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 130 static void __mii_init(void);
 131 #endif
 132
 133 int fec_initialize(bd_t *bis)
 134 {
 135         struct eth_device* dev;
 136         struct ether_fcc_info_s *efis;
 137         int             i;
 138
 139         for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
 140
 141                 dev = malloc(sizeof(*dev));
 142                 if (dev == NULL)
 143                         hang();
 144
 145                 memset(dev, 0, sizeof(*dev));
 146
 147                 /* for FEC1 make sure that the name of the interface is the same
 148                    as the old one for compatibility reasons */
 149                 if (i == 0) {
 150                         strcpy(dev->name, "FEC");
 151                 } else {
 152                         sprintf (dev->name, "FEC%d",
 153                                 ether_fcc_info[i].ether_index + 1);
 154                 }
 155
 156                 efis = &ether_fcc_info[i];
 157
 158                 /*
 159                  * reset actual phy addr
 160                  */
 161                 efis->actual_phy_addr = -1;
 162
 163                 dev->priv = efis;
 164                 dev->init = fec_init;
 165                 dev->halt = fec_halt;
 166                 dev->send = fec_send;
 167                 dev->recv = fec_recv;
 168
 169                 eth_register(dev);
 170
 171 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 172                 int retval;
 173                 struct mii_dev *mdiodev = mdio_alloc();
 174                 if (!mdiodev)
 175                         return -ENOMEM;
 176                 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 177                 mdiodev->read = fec8xx_miiphy_read;
 178                 mdiodev->write = fec8xx_miiphy_write;
 179
 180                 retval = mdio_register(mdiodev);
 181                 if (retval < 0)
 182                         return retval;
 183 #endif
 184         }
 185         return 1;
 186 }
 187
 188 static int fec_send(struct eth_device *dev, void *packet, int length)
 189 {
 190         int j, rc;
 191         struct ether_fcc_info_s *efis = dev->priv;
 192         volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
 193
 194         /* section 16.9.23.3
 195          * Wait for ready
 196          */
 197         j = 0;
 198         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
 199                 udelay(1);
 200                 j++;
 201         }
 202         if (j>=TOUT_LOOP) {
 203                 printf("TX not ready\n");
 204         }
 205
 206         rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
 207         rtx->txbd[txIdx].cbd_datlen  = length;
 208         rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
 209         __asm__ ("eieio");
 210
 211         /* Activate transmit Buffer Descriptor polling */
 212         fecp->fec_x_des_active = 0x01000000;    /* Descriptor polling active    */
 213
 214         j = 0;
 215         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
 216                 udelay(1);
 217                 j++;
 218         }
 219         if (j>=TOUT_LOOP) {
 220                 printf("TX timeout\n");
 221         }
 222         /* return only status bits */;
 223         rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
 224
 225         txIdx = (txIdx + 1) % TX_BUF_CNT;
 226
 227         return rc;
 228 }
 229
 230 static int fec_recv (struct eth_device *dev)
 231 {
 232         struct ether_fcc_info_s *efis = dev->priv;
 233         volatile fec_t *fecp =
 234                 (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
 235         int length;
 236
 237         for (;;) {
 238                 /* section 16.9.23.2 */
 239                 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
 240                         length = -1;
 241                         break;  /* nothing received - leave for() loop */
 242                 }
 243
 244                 length = rtx->rxbd[rxIdx].cbd_datlen;
 245
 246                 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
 247                 } else {
 248                         uchar *rx = net_rx_packets[rxIdx];
 249
 250                         length -= 4;
 251
 252 #if defined(CONFIG_CMD_CDP)
 253                         if ((rx[0] & 1) != 0 &&
 254                             memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
 255                             !is_cdp_packet((uchar *)rx))
 256                                 rx = NULL;
 257 #endif
 258                         /*
 259                          * Pass the packet up to the protocol layers.
 260                          */
 261                         if (rx != NULL)
 262                                 net_process_received_packet(rx, length);
 263                 }
 264
 265                 /* Give the buffer back to the FEC. */
 266                 rtx->rxbd[rxIdx].cbd_datlen = 0;
 267
 268                 /* wrap around buffer index when necessary */
 269                 if ((rxIdx + 1) >= PKTBUFSRX) {
 270                         rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
 271                                 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
 272                         rxIdx = 0;
 273                 } else {
 274                         rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
 275                         rxIdx++;
 276                 }
 277
 278                 __asm__ ("eieio");
 279
 280                 /* Try to fill Buffer Descriptors */
 281                 fecp->fec_r_des_active = 0x01000000;    /* Descriptor polling active    */
 282         }
 283
 284         return length;
 285 }
 286
 287 /**************************************************************
 288  *
 289  * FEC Ethernet Initialization Routine
 290  *
 291  *************************************************************/
 292
 293 #define FEC_ECNTRL_PINMUX       0x00000004
 294 #define FEC_ECNTRL_ETHER_EN     0x00000002
 295 #define FEC_ECNTRL_RESET        0x00000001
 296
 297 #define FEC_RCNTRL_BC_REJ       0x00000010
 298 #define FEC_RCNTRL_PROM         0x00000008
 299 #define FEC_RCNTRL_MII_MODE     0x00000004
 300 #define FEC_RCNTRL_DRT          0x00000002
 301 #define FEC_RCNTRL_LOOP         0x00000001
 302
 303 #define FEC_TCNTRL_FDEN         0x00000004
 304 #define FEC_TCNTRL_HBC          0x00000002
 305 #define FEC_TCNTRL_GTS          0x00000001
 306
 307 #define FEC_RESET_DELAY         50
 308
 309 #if defined(CONFIG_RMII)
 310
 311 static inline void fec_10Mbps(struct eth_device *dev)
 312 {
 313         struct ether_fcc_info_s *efis = dev->priv;
 314         int fecidx = efis->ether_index;
 315         uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
 316
 317         if ((unsigned int)fecidx >= 2)
 318                 hang();
 319
 320         ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |=  mask;
 321 }
 322
 323 static inline void fec_100Mbps(struct eth_device *dev)
 324 {
 325         struct ether_fcc_info_s *efis = dev->priv;
 326         int fecidx = efis->ether_index;
 327         uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
 328
 329         if ((unsigned int)fecidx >= 2)
 330                 hang();
 331
 332         ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
 333 }
 334
 335 #endif
 336
 337 static inline void fec_full_duplex(struct eth_device *dev)
 338 {
 339         struct ether_fcc_info_s *efis = dev->priv;
 340         volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
 341
 342         fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
 343         fecp->fec_x_cntrl |=  FEC_TCNTRL_FDEN;  /* FD enable */
 344 }
 345
 346 static inline void fec_half_duplex(struct eth_device *dev)
 347 {
 348         struct ether_fcc_info_s *efis = dev->priv;
 349         volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
 350
 351         fecp->fec_r_cntrl |=  FEC_RCNTRL_DRT;
 352         fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN;  /* FD disable */
 353 }
 354
 355 static void fec_pin_init(int fecidx)
 356 {
 357         bd_t           *bd = gd->bd;
 358         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 359
 360         /*
 361          * Set MII speed to 2.5 MHz or slightly below.
 362          *
 363          * According to the MPC860T (Rev. D) Fast ethernet controller user
 364          * manual (6.2.14),
 365          * the MII management interface clock must be less than or equal
 366          * to 2.5 MHz.
 367          * This MDC frequency is equal to system clock / (2 * MII_SPEED).
 368          * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
 369          *
 370          * All MII configuration is done via FEC1 registers:
 371          */
 372         immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
 373
 374 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
 375         /* use MDC for MII */
 376         immr->im_ioport.iop_pdpar |=  0x0080;
 377         immr->im_ioport.iop_pddir &= ~0x0080;
 378 #endif
 379
 380         if (fecidx == 0) {
 381 #if defined(CONFIG_ETHER_ON_FEC1)
 382
 383 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
 384
 385 #if !defined(CONFIG_RMII)
 386
 387                 immr->im_ioport.iop_papar |=  0xf830;
 388                 immr->im_ioport.iop_padir |=  0x0830;
 389                 immr->im_ioport.iop_padir &= ~0xf000;
 390
 391                 immr->im_cpm.cp_pbpar     |=  0x00001001;
 392                 immr->im_cpm.cp_pbdir     &= ~0x00001001;
 393
 394                 immr->im_ioport.iop_pcpar |=  0x000c;
 395                 immr->im_ioport.iop_pcdir &= ~0x000c;
 396
 397                 immr->im_cpm.cp_pepar     |=  0x00000003;
 398                 immr->im_cpm.cp_pedir     |=  0x00000003;
 399                 immr->im_cpm.cp_peso      &= ~0x00000003;
 400
 401                 immr->im_cpm.cp_cptr      &= ~0x00000100;
 402
 403 #else
 404
 405 #if !defined(CONFIG_FEC1_PHY_NORXERR)
 406                 immr->im_ioport.iop_papar |=  0x1000;
 407                 immr->im_ioport.iop_padir &= ~0x1000;
 408 #endif
 409                 immr->im_ioport.iop_papar |=  0xe810;
 410                 immr->im_ioport.iop_padir |=  0x0810;
 411                 immr->im_ioport.iop_padir &= ~0xe000;
 412
 413                 immr->im_cpm.cp_pbpar     |=  0x00000001;
 414                 immr->im_cpm.cp_pbdir     &= ~0x00000001;
 415
 416                 immr->im_cpm.cp_cptr      |=  0x00000100;
 417                 immr->im_cpm.cp_cptr      &= ~0x00000050;
 418
 419 #endif /* !CONFIG_RMII */
 420
 421 #else
 422                 /*
 423                  * Configure all of port D for MII.
 424                  */
 425                 immr->im_ioport.iop_pdpar = 0x1fff;
 426
 427                         immr->im_ioport.iop_pddir = 0x1fff;     /* Rev. D and later */
 428 #endif
 429
 430 #endif  /* CONFIG_ETHER_ON_FEC1 */
 431         } else if (fecidx == 1) {
 432
 433 #if defined(CONFIG_ETHER_ON_FEC2)
 434
 435 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
 436
 437 #if !defined(CONFIG_RMII)
 438                 immr->im_cpm.cp_pepar     |=  0x0003fffc;
 439                 immr->im_cpm.cp_pedir     |=  0x0003fffc;
 440                 immr->im_cpm.cp_peso      &= ~0x000087fc;
 441                 immr->im_cpm.cp_peso      |=  0x00037800;
 442
 443                 immr->im_cpm.cp_cptr      &= ~0x00000080;
 444 #else
 445
 446 #if !defined(CONFIG_FEC2_PHY_NORXERR)
 447                 immr->im_cpm.cp_pepar     |=  0x00000010;
 448                 immr->im_cpm.cp_pedir     |=  0x00000010;
 449                 immr->im_cpm.cp_peso      &= ~0x00000010;
 450 #endif
 451                 immr->im_cpm.cp_pepar     |=  0x00039620;
 452                 immr->im_cpm.cp_pedir     |=  0x00039620;
 453                 immr->im_cpm.cp_peso      |=  0x00031000;
 454                 immr->im_cpm.cp_peso      &= ~0x00008620;
 455
 456                 immr->im_cpm.cp_cptr      |=  0x00000080;
 457                 immr->im_cpm.cp_cptr      &= ~0x00000028;
 458 #endif /* CONFIG_RMII */
 459
 460 #endif /* CONFIG_MPC885_FAMILY */
 461
 462 #endif /* CONFIG_ETHER_ON_FEC2 */
 463
 464         }
 465 }
 466
 467 static int fec_reset(volatile fec_t *fecp)
 468 {
 469         int i;
 470
 471         /* Whack a reset.
 472          * A delay is required between a reset of the FEC block and
 473          * initialization of other FEC registers because the reset takes
 474          * some time to complete. If you don't delay, subsequent writes
 475          * to FEC registers might get killed by the reset routine which is
 476          * still in progress.
 477          */
 478
 479         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
 480         for (i = 0;
 481              (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
 482              ++i) {
 483                 udelay (1);
 484         }
 485         if (i == FEC_RESET_DELAY)
 486                 return -1;
 487
 488         return 0;
 489 }
 490
 491 static int fec_init (struct eth_device *dev, bd_t * bd)
 492 {
 493         struct ether_fcc_info_s *efis = dev->priv;
 494         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 495         volatile fec_t *fecp =
 496                 (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
 497         int i;
 498
 499 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 500         /* the MII interface is connected to FEC1
 501          * so for the miiphy_xxx function to work we must
 502          * call mii_init since fec_halt messes the thing up
 503          */
 504         if (efis->ether_index != 0)
 505                 __mii_init();
 506 #endif
 507
 508         if (fec_reset(fecp) < 0)
 509                 printf ("FEC_RESET_DELAY timeout\n");
 510
 511         /* We use strictly polling mode only
 512          */
 513         fecp->fec_imask = 0;
 514
 515         /* Clear any pending interrupt
 516          */
 517         fecp->fec_ievent = 0xffc0;
 518
 519         /* No need to set the IVEC register */
 520
 521         /* Set station address
 522          */
 523 #define ea dev->enetaddr
 524         fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
 525         fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
 526 #undef ea
 527
 528 #if defined(CONFIG_CMD_CDP)
 529         /*
 530          * Turn on multicast address hash table
 531          */
 532         fecp->fec_hash_table_high = 0xffffffff;
 533         fecp->fec_hash_table_low = 0xffffffff;
 534 #else
 535         /* Clear multicast address hash table
 536          */
 537         fecp->fec_hash_table_high = 0;
 538         fecp->fec_hash_table_low = 0;
 539 #endif
 540
 541         /* Set maximum receive buffer size.
 542          */
 543         fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
 544
 545         /* Set maximum frame length
 546          */
 547         fecp->fec_r_hash = PKT_MAXBUF_SIZE;
 548
 549         /*
 550          * Setup Buffers and Buffer Desriptors
 551          */
 552         rxIdx = 0;
 553         txIdx = 0;
 554
 555         if (!rtx)
 556                 rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
 557         /*
 558          * Setup Receiver Buffer Descriptors (13.14.24.18)
 559          * Settings:
 560          *     Empty, Wrap
 561          */
 562         for (i = 0; i < PKTBUFSRX; i++) {
 563                 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 564                 rtx->rxbd[i].cbd_datlen = 0;    /* Reset */
 565                 rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
 566         }
 567         rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 568
 569         /*
 570          * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 571          * Settings:
 572          *    Last, Tx CRC
 573          */
 574         for (i = 0; i < TX_BUF_CNT; i++) {
 575                 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
 576                 rtx->txbd[i].cbd_datlen = 0;    /* Reset */
 577                 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
 578         }
 579         rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 580
 581         /* Set receive and transmit descriptor base
 582          */
 583         fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
 584         fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
 585
 586         /* Enable MII mode
 587          */
 588         /* Half duplex mode */
 589         fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
 590         fecp->fec_x_cntrl = 0;
 591
 592         /* Enable big endian and don't care about SDMA FC.
 593          */
 594         fecp->fec_fun_code = 0x78000000;
 595
 596         /*
 597          * Setup the pin configuration of the FEC
 598          */
 599         fec_pin_init (efis->ether_index);
 600
 601         rxIdx = 0;
 602         txIdx = 0;
 603
 604         /*
 605          * Now enable the transmit and receive processing
 606          */
 607         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
 608
 609         if (efis->phy_addr == -1) {
 610 #ifdef CONFIG_SYS_DISCOVER_PHY
 611                 /*
 612                  * wait for the PHY to wake up after reset
 613                  */
 614                 efis->actual_phy_addr = mii_discover_phy (dev);
 615
 616                 if (efis->actual_phy_addr == -1) {
 617                         printf ("Unable to discover phy!\n");
 618                         return -1;
 619                 }
 620 #else
 621                 efis->actual_phy_addr = -1;
 622 #endif
 623         } else {
 624                 efis->actual_phy_addr = efis->phy_addr;
 625         }
 626
 627 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
 628         /*
 629          * adapt the RMII speed to the speed of the phy
 630          */
 631         if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
 632                 fec_100Mbps (dev);
 633         } else {
 634                 fec_10Mbps (dev);
 635         }
 636 #endif
 637
 638 #if defined(CONFIG_MII)
 639         /*
 640          * adapt to the half/full speed settings
 641          */
 642         if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
 643                 fec_full_duplex (dev);
 644         } else {
 645                 fec_half_duplex (dev);
 646         }
 647 #endif
 648
 649         /* And last, try to fill Rx Buffer Descriptors */
 650         fecp->fec_r_des_active = 0x01000000;    /* Descriptor polling active    */
 651
 652         efis->initialized = 1;
 653
 654         return 0;
 655 }
 656
 657
 658 static void fec_halt(struct eth_device* dev)
 659 {
 660         struct ether_fcc_info_s *efis = dev->priv;
 661         volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
 662         int i;
 663
 664         /* avoid halt if initialized; mii gets stuck otherwise */
 665         if (!efis->initialized)
 666                 return;
 667
 668         /* Whack a reset.
 669          * A delay is required between a reset of the FEC block and
 670          * initialization of other FEC registers because the reset takes
 671          * some time to complete. If you don't delay, subsequent writes
 672          * to FEC registers might get killed by the reset routine which is
 673          * still in progress.
 674          */
 675
 676         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
 677         for (i = 0;
 678              (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
 679              ++i) {
 680                 udelay (1);
 681         }
 682         if (i == FEC_RESET_DELAY) {
 683                 printf ("FEC_RESET_DELAY timeout\n");
 684                 return;
 685         }
 686
 687         efis->initialized = 0;
 688 }
 689
 690 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 691
 692 /* Make MII read/write commands for the FEC.
 693 */
 694
 695 #define mk_mii_read(ADDR, REG)  (0x60020000 | ((ADDR << 23) | \
 696                                                 (REG & 0x1f) << 18))
 697
 698 #define mk_mii_write(ADDR, REG, VAL)    (0x50020000 | ((ADDR << 23) | \
 699                                                 (REG & 0x1f) << 18) | \
 700                                                 (VAL & 0xffff))
 701
 702 /* Interrupt events/masks.
 703 */
 704 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
 705 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
 706 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
 707 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
 708 #define FEC_ENET_TXF    ((uint)0x08000000)      /* Full frame transmitted */
 709 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
 710 #define FEC_ENET_RXF    ((uint)0x02000000)      /* Full frame received */
 711 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
 712 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
 713 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
 714
 715 /* send command to phy using mii, wait for result */
 716 static uint
 717 mii_send(uint mii_cmd)
 718 {
 719         uint mii_reply;
 720         volatile fec_t  *ep;
 721         int cnt;
 722
 723         ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
 724
 725         ep->fec_mii_data = mii_cmd;     /* command to phy */
 726
 727         /* wait for mii complete */
 728         cnt = 0;
 729         while (!(ep->fec_ievent & FEC_ENET_MII)) {
 730                 if (++cnt > 1000) {
 731                         printf("mii_send STUCK!\n");
 732                         break;
 733                 }
 734         }
 735         mii_reply = ep->fec_mii_data;           /* result from phy */
 736         ep->fec_ievent = FEC_ENET_MII;          /* clear MII complete */
 737         return (mii_reply & 0xffff);            /* data read from phy */
 738 }
 739 #endif
 740
 741 #if defined(CONFIG_SYS_DISCOVER_PHY)
 742 static int mii_discover_phy(struct eth_device *dev)
 743 {
 744 #define MAX_PHY_PASSES 11
 745         uint phyno;
 746         int  pass;
 747         uint phytype;
 748         int phyaddr;
 749
 750         phyaddr = -1;   /* didn't find a PHY yet */
 751         for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
 752                 if (pass > 1) {
 753                         /* PHY may need more time to recover from reset.
 754                          * The LXT970 needs 50ms typical, no maximum is
 755                          * specified, so wait 10ms before try again.
 756                          * With 11 passes this gives it 100ms to wake up.
 757                          */
 758                         udelay(10000);  /* wait 10ms */
 759                 }
 760                 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
 761                         phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
 762                         if (phytype != 0xffff) {
 763                                 phyaddr = phyno;
 764                                 phytype |= mii_send(mk_mii_read(phyno,
 765                                                                 MII_PHYSID1)) << 16;
 766                         }
 767                 }
 768         }
 769         if (phyaddr < 0) {
 770                 printf("No PHY device found.\n");
 771         }
 772         return phyaddr;
 773 }
 774 #endif  /* CONFIG_SYS_DISCOVER_PHY */
 775
 776 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
 777
 778 /****************************************************************************
 779  * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
 780  * This function is a subset of eth_init
 781  ****************************************************************************
 782  */
 783 static void __mii_init(void)
 784 {
 785         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 786         volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
 787
 788         if (fec_reset(fecp) < 0)
 789                 printf ("FEC_RESET_DELAY timeout\n");
 790
 791         /* We use strictly polling mode only
 792          */
 793         fecp->fec_imask = 0;
 794
 795         /* Clear any pending interrupt
 796          */
 797         fecp->fec_ievent = 0xffc0;
 798
 799         /* Now enable the transmit and receive processing
 800          */
 801         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
 802 }
 803
 804 void mii_init (void)
 805 {
 806         int i;
 807
 808         __mii_init();
 809
 810         /* Setup the pin configuration of the FEC(s)
 811         */
 812         for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
 813                 fec_pin_init(ether_fcc_info[i].ether_index);
 814 }
 815
 816 /*****************************************************************************
 817  * Read and write a MII PHY register, routines used by MII Utilities
 818  *
 819  * FIXME: These routines are expected to return 0 on success, but mii_send
 820  *        does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 821  *        no PHY connected...
 822  *        For now always return 0.
 823  * FIXME: These routines only work after calling eth_init() at least once!
 824  *        Otherwise they hang in mii_send() !!! Sorry!
 825  *****************************************************************************/
 826
 827 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
 828 {
 829         unsigned short value = 0;
 830         short rdreg;    /* register working value */
 831
 832         rdreg = mii_send(mk_mii_read(addr, reg));
 833
 834         value = rdreg;
 835         return value;
 836 }
 837
 838 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
 839                         u16 value)
 840 {
 841         (void)mii_send(mk_mii_write(addr, reg, value));
 842
 843         return 0;
 844 }
 845 #endif
 846
 847 #endif