]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/powerpc/cpu/mpc8xx/fec.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
14 DECLARE_GLOBAL_DATA_PTR
;
18 #if defined(CONFIG_CMD_NET) && \
19 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
21 /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
22 #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
23 #define CONFIG_ETHER_ON_FEC1 1
26 /* define WANT_MII when MII support is required */
27 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
36 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
37 #error "CONFIG_MII has to be defined!"
42 #if defined(CONFIG_RMII) && !defined(WANT_MII)
43 #error RMII support is unusable without a working PHY.
46 #ifdef CONFIG_SYS_DISCOVER_PHY
47 static int mii_discover_phy(struct eth_device
*dev
);
50 int fec8xx_miiphy_read(const char *devname
, unsigned char addr
,
51 unsigned char reg
, unsigned short *value
);
52 int fec8xx_miiphy_write(const char *devname
, unsigned char addr
,
53 unsigned char reg
, unsigned short value
);
55 static struct ether_fcc_info_s
64 #if defined(CONFIG_ETHER_ON_FEC1)
67 offsetof(immap_t
, im_cpm
.cp_fec1
),
68 #if defined(CONFIG_FEC1_PHY)
78 #if defined(CONFIG_ETHER_ON_FEC2)
81 offsetof(immap_t
, im_cpm
.cp_fec2
),
82 #if defined(CONFIG_FEC2_PHY)
93 /* Ethernet Transmit and Receive Buffers */
94 #define DBUF_LENGTH 1520
100 #define PKT_MAXBUF_SIZE 1518
101 #define PKT_MINBUF_SIZE 64
102 #define PKT_MAXBLR_SIZE 1520
105 static char txbuf
[DBUF_LENGTH
] __attribute__ ((aligned(8)));
107 #error txbuf must be aligned.
110 static uint rxIdx
; /* index of the current RX buffer */
111 static uint txIdx
; /* index of the current TX buffer */
114 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
115 * immr->udata_bd address on Dual-Port RAM
116 * Provide for Double Buffering
119 typedef volatile struct CommonBufferDescriptor
{
120 cbd_t rxbd
[PKTBUFSRX
]; /* Rx BD */
121 cbd_t txbd
[TX_BUF_CNT
]; /* Tx BD */
124 static RTXBD
*rtx
= NULL
;
126 static int fec_send(struct eth_device
*dev
, void *packet
, int length
);
127 static int fec_recv(struct eth_device
* dev
);
128 static int fec_init(struct eth_device
* dev
, bd_t
* bd
);
129 static void fec_halt(struct eth_device
* dev
);
130 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
131 static void __mii_init(void);
134 int fec_initialize(bd_t
*bis
)
136 struct eth_device
* dev
;
137 struct ether_fcc_info_s
*efis
;
140 for (i
= 0; i
< sizeof(ether_fcc_info
) / sizeof(ether_fcc_info
[0]); i
++) {
142 dev
= malloc(sizeof(*dev
));
146 memset(dev
, 0, sizeof(*dev
));
148 /* for FEC1 make sure that the name of the interface is the same
149 as the old one for compatibility reasons */
151 strcpy(dev
->name
, "FEC");
153 sprintf (dev
->name
, "FEC%d",
154 ether_fcc_info
[i
].ether_index
+ 1);
157 efis
= ðer_fcc_info
[i
];
160 * reset actual phy addr
162 efis
->actual_phy_addr
= -1;
165 dev
->init
= fec_init
;
166 dev
->halt
= fec_halt
;
167 dev
->send
= fec_send
;
168 dev
->recv
= fec_recv
;
172 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
173 miiphy_register(dev
->name
,
174 fec8xx_miiphy_read
, fec8xx_miiphy_write
);
180 static int fec_send(struct eth_device
*dev
, void *packet
, int length
)
183 struct ether_fcc_info_s
*efis
= dev
->priv
;
184 volatile fec_t
*fecp
= (volatile fec_t
*)(CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
190 while ((rtx
->txbd
[txIdx
].cbd_sc
& BD_ENET_TX_READY
) && (j
<TOUT_LOOP
)) {
195 printf("TX not ready\n");
198 rtx
->txbd
[txIdx
].cbd_bufaddr
= (uint
)packet
;
199 rtx
->txbd
[txIdx
].cbd_datlen
= length
;
200 rtx
->txbd
[txIdx
].cbd_sc
|= BD_ENET_TX_READY
| BD_ENET_TX_LAST
;
203 /* Activate transmit Buffer Descriptor polling */
204 fecp
->fec_x_des_active
= 0x01000000; /* Descriptor polling active */
207 while ((rtx
->txbd
[txIdx
].cbd_sc
& BD_ENET_TX_READY
) && (j
<TOUT_LOOP
)) {
212 printf("TX timeout\n");
215 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
216 __FILE__
,__LINE__
,__FUNCTION__
,j
,rtx
->txbd
[txIdx
].cbd_sc
,
217 (rtx
->txbd
[txIdx
].cbd_sc
& 0x003C)>>2);
219 /* return only status bits */;
220 rc
= (rtx
->txbd
[txIdx
].cbd_sc
& BD_ENET_TX_STATS
);
222 txIdx
= (txIdx
+ 1) % TX_BUF_CNT
;
227 static int fec_recv (struct eth_device
*dev
)
229 struct ether_fcc_info_s
*efis
= dev
->priv
;
230 volatile fec_t
*fecp
=
231 (volatile fec_t
*) (CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
235 /* section 16.9.23.2 */
236 if (rtx
->rxbd
[rxIdx
].cbd_sc
& BD_ENET_RX_EMPTY
) {
238 break; /* nothing received - leave for() loop */
241 length
= rtx
->rxbd
[rxIdx
].cbd_datlen
;
243 if (rtx
->rxbd
[rxIdx
].cbd_sc
& 0x003f) {
245 printf ("%s[%d] err: %x\n",
246 __FUNCTION__
, __LINE__
,
247 rtx
->rxbd
[rxIdx
].cbd_sc
);
250 uchar
*rx
= net_rx_packets
[rxIdx
];
254 #if defined(CONFIG_CMD_CDP)
255 if ((rx
[0] & 1) != 0 &&
256 memcmp((uchar
*)rx
, net_bcast_ethaddr
, 6) != 0 &&
257 !is_cdp_packet((uchar
*)rx
))
261 * Pass the packet up to the protocol layers.
264 net_process_received_packet(rx
, length
);
267 /* Give the buffer back to the FEC. */
268 rtx
->rxbd
[rxIdx
].cbd_datlen
= 0;
270 /* wrap around buffer index when necessary */
271 if ((rxIdx
+ 1) >= PKTBUFSRX
) {
272 rtx
->rxbd
[PKTBUFSRX
- 1].cbd_sc
=
273 (BD_ENET_RX_WRAP
| BD_ENET_RX_EMPTY
);
276 rtx
->rxbd
[rxIdx
].cbd_sc
= BD_ENET_RX_EMPTY
;
282 /* Try to fill Buffer Descriptors */
283 fecp
->fec_r_des_active
= 0x01000000; /* Descriptor polling active */
289 /**************************************************************
291 * FEC Ethernet Initialization Routine
293 *************************************************************/
295 #define FEC_ECNTRL_PINMUX 0x00000004
296 #define FEC_ECNTRL_ETHER_EN 0x00000002
297 #define FEC_ECNTRL_RESET 0x00000001
299 #define FEC_RCNTRL_BC_REJ 0x00000010
300 #define FEC_RCNTRL_PROM 0x00000008
301 #define FEC_RCNTRL_MII_MODE 0x00000004
302 #define FEC_RCNTRL_DRT 0x00000002
303 #define FEC_RCNTRL_LOOP 0x00000001
305 #define FEC_TCNTRL_FDEN 0x00000004
306 #define FEC_TCNTRL_HBC 0x00000002
307 #define FEC_TCNTRL_GTS 0x00000001
309 #define FEC_RESET_DELAY 50
311 #if defined(CONFIG_RMII)
313 static inline void fec_10Mbps(struct eth_device
*dev
)
315 struct ether_fcc_info_s
*efis
= dev
->priv
;
316 int fecidx
= efis
->ether_index
;
317 uint mask
= (fecidx
== 0) ? 0x0000010 : 0x0000008;
319 if ((unsigned int)fecidx
>= 2)
322 ((volatile immap_t
*)CONFIG_SYS_IMMR
)->im_cpm
.cp_cptr
|= mask
;
325 static inline void fec_100Mbps(struct eth_device
*dev
)
327 struct ether_fcc_info_s
*efis
= dev
->priv
;
328 int fecidx
= efis
->ether_index
;
329 uint mask
= (fecidx
== 0) ? 0x0000010 : 0x0000008;
331 if ((unsigned int)fecidx
>= 2)
334 ((volatile immap_t
*)CONFIG_SYS_IMMR
)->im_cpm
.cp_cptr
&= ~mask
;
339 static inline void fec_full_duplex(struct eth_device
*dev
)
341 struct ether_fcc_info_s
*efis
= dev
->priv
;
342 volatile fec_t
*fecp
= (volatile fec_t
*)(CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
344 fecp
->fec_r_cntrl
&= ~FEC_RCNTRL_DRT
;
345 fecp
->fec_x_cntrl
|= FEC_TCNTRL_FDEN
; /* FD enable */
348 static inline void fec_half_duplex(struct eth_device
*dev
)
350 struct ether_fcc_info_s
*efis
= dev
->priv
;
351 volatile fec_t
*fecp
= (volatile fec_t
*)(CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
353 fecp
->fec_r_cntrl
|= FEC_RCNTRL_DRT
;
354 fecp
->fec_x_cntrl
&= ~FEC_TCNTRL_FDEN
; /* FD disable */
357 static void fec_pin_init(int fecidx
)
360 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
363 * Set MII speed to 2.5 MHz or slightly below.
365 * According to the MPC860T (Rev. D) Fast ethernet controller user
367 * the MII management interface clock must be less than or equal
369 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
370 * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
372 * All MII configuration is done via FEC1 registers:
374 immr
->im_cpm
.cp_fec1
.fec_mii_speed
= ((bd
->bi_intfreq
+ 4999999) / 5000000) << 1;
376 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
377 /* use MDC for MII */
378 immr
->im_ioport
.iop_pdpar
|= 0x0080;
379 immr
->im_ioport
.iop_pddir
&= ~0x0080;
383 #if defined(CONFIG_ETHER_ON_FEC1)
385 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
387 #if !defined(CONFIG_RMII)
389 immr
->im_ioport
.iop_papar
|= 0xf830;
390 immr
->im_ioport
.iop_padir
|= 0x0830;
391 immr
->im_ioport
.iop_padir
&= ~0xf000;
393 immr
->im_cpm
.cp_pbpar
|= 0x00001001;
394 immr
->im_cpm
.cp_pbdir
&= ~0x00001001;
396 immr
->im_ioport
.iop_pcpar
|= 0x000c;
397 immr
->im_ioport
.iop_pcdir
&= ~0x000c;
399 immr
->im_cpm
.cp_pepar
|= 0x00000003;
400 immr
->im_cpm
.cp_pedir
|= 0x00000003;
401 immr
->im_cpm
.cp_peso
&= ~0x00000003;
403 immr
->im_cpm
.cp_cptr
&= ~0x00000100;
407 #if !defined(CONFIG_FEC1_PHY_NORXERR)
408 immr
->im_ioport
.iop_papar
|= 0x1000;
409 immr
->im_ioport
.iop_padir
&= ~0x1000;
411 immr
->im_ioport
.iop_papar
|= 0xe810;
412 immr
->im_ioport
.iop_padir
|= 0x0810;
413 immr
->im_ioport
.iop_padir
&= ~0xe000;
415 immr
->im_cpm
.cp_pbpar
|= 0x00000001;
416 immr
->im_cpm
.cp_pbdir
&= ~0x00000001;
418 immr
->im_cpm
.cp_cptr
|= 0x00000100;
419 immr
->im_cpm
.cp_cptr
&= ~0x00000050;
421 #endif /* !CONFIG_RMII */
425 * Configure all of port D for MII.
427 immr
->im_ioport
.iop_pdpar
= 0x1fff;
430 * Bits moved from Rev. D onward
432 if ((get_immr(0) & 0xffff) < 0x0501)
433 immr
->im_ioport
.iop_pddir
= 0x1c58; /* Pre rev. D */
435 immr
->im_ioport
.iop_pddir
= 0x1fff; /* Rev. D and later */
438 #endif /* CONFIG_ETHER_ON_FEC1 */
439 } else if (fecidx
== 1) {
441 #if defined(CONFIG_ETHER_ON_FEC2)
443 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
445 #if !defined(CONFIG_RMII)
446 immr
->im_cpm
.cp_pepar
|= 0x0003fffc;
447 immr
->im_cpm
.cp_pedir
|= 0x0003fffc;
448 immr
->im_cpm
.cp_peso
&= ~0x000087fc;
449 immr
->im_cpm
.cp_peso
|= 0x00037800;
451 immr
->im_cpm
.cp_cptr
&= ~0x00000080;
454 #if !defined(CONFIG_FEC2_PHY_NORXERR)
455 immr
->im_cpm
.cp_pepar
|= 0x00000010;
456 immr
->im_cpm
.cp_pedir
|= 0x00000010;
457 immr
->im_cpm
.cp_peso
&= ~0x00000010;
459 immr
->im_cpm
.cp_pepar
|= 0x00039620;
460 immr
->im_cpm
.cp_pedir
|= 0x00039620;
461 immr
->im_cpm
.cp_peso
|= 0x00031000;
462 immr
->im_cpm
.cp_peso
&= ~0x00008620;
464 immr
->im_cpm
.cp_cptr
|= 0x00000080;
465 immr
->im_cpm
.cp_cptr
&= ~0x00000028;
466 #endif /* CONFIG_RMII */
468 #endif /* CONFIG_MPC885_FAMILY */
470 #endif /* CONFIG_ETHER_ON_FEC2 */
475 static int fec_reset(volatile fec_t
*fecp
)
480 * A delay is required between a reset of the FEC block and
481 * initialization of other FEC registers because the reset takes
482 * some time to complete. If you don't delay, subsequent writes
483 * to FEC registers might get killed by the reset routine which is
487 fecp
->fec_ecntrl
= FEC_ECNTRL_PINMUX
| FEC_ECNTRL_RESET
;
489 (fecp
->fec_ecntrl
& FEC_ECNTRL_RESET
) && (i
< FEC_RESET_DELAY
);
493 if (i
== FEC_RESET_DELAY
)
499 static int fec_init (struct eth_device
*dev
, bd_t
* bd
)
501 struct ether_fcc_info_s
*efis
= dev
->priv
;
502 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
503 volatile fec_t
*fecp
=
504 (volatile fec_t
*) (CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
507 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
508 /* the MII interface is connected to FEC1
509 * so for the miiphy_xxx function to work we must
510 * call mii_init since fec_halt messes the thing up
512 if (efis
->ether_index
!= 0)
516 if (fec_reset(fecp
) < 0)
517 printf ("FEC_RESET_DELAY timeout\n");
519 /* We use strictly polling mode only
523 /* Clear any pending interrupt
525 fecp
->fec_ievent
= 0xffc0;
527 /* No need to set the IVEC register */
529 /* Set station address
531 #define ea dev->enetaddr
532 fecp
->fec_addr_low
= (ea
[0] << 24) | (ea
[1] << 16) | (ea
[2] << 8) | (ea
[3]);
533 fecp
->fec_addr_high
= (ea
[4] << 8) | (ea
[5]);
536 #if defined(CONFIG_CMD_CDP)
538 * Turn on multicast address hash table
540 fecp
->fec_hash_table_high
= 0xffffffff;
541 fecp
->fec_hash_table_low
= 0xffffffff;
543 /* Clear multicast address hash table
545 fecp
->fec_hash_table_high
= 0;
546 fecp
->fec_hash_table_low
= 0;
549 /* Set maximum receive buffer size.
551 fecp
->fec_r_buff_size
= PKT_MAXBLR_SIZE
;
553 /* Set maximum frame length
555 fecp
->fec_r_hash
= PKT_MAXBUF_SIZE
;
558 * Setup Buffers and Buffer Desriptors
564 #ifdef CONFIG_SYS_ALLOC_DPRAM
565 rtx
= (RTXBD
*) (immr
->im_cpm
.cp_dpmem
+
566 dpram_alloc_align (sizeof (RTXBD
), 8));
568 rtx
= (RTXBD
*) (immr
->im_cpm
.cp_dpmem
+ CPM_FEC_BASE
);
572 * Setup Receiver Buffer Descriptors (13.14.24.18)
576 for (i
= 0; i
< PKTBUFSRX
; i
++) {
577 rtx
->rxbd
[i
].cbd_sc
= BD_ENET_RX_EMPTY
;
578 rtx
->rxbd
[i
].cbd_datlen
= 0; /* Reset */
579 rtx
->rxbd
[i
].cbd_bufaddr
= (uint
) net_rx_packets
[i
];
581 rtx
->rxbd
[PKTBUFSRX
- 1].cbd_sc
|= BD_ENET_RX_WRAP
;
584 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
588 for (i
= 0; i
< TX_BUF_CNT
; i
++) {
589 rtx
->txbd
[i
].cbd_sc
= BD_ENET_TX_LAST
| BD_ENET_TX_TC
;
590 rtx
->txbd
[i
].cbd_datlen
= 0; /* Reset */
591 rtx
->txbd
[i
].cbd_bufaddr
= (uint
) (&txbuf
[0]);
593 rtx
->txbd
[TX_BUF_CNT
- 1].cbd_sc
|= BD_ENET_TX_WRAP
;
595 /* Set receive and transmit descriptor base
597 fecp
->fec_r_des_start
= (unsigned int) (&rtx
->rxbd
[0]);
598 fecp
->fec_x_des_start
= (unsigned int) (&rtx
->txbd
[0]);
602 #if 0 /* Full duplex mode */
603 fecp
->fec_r_cntrl
= FEC_RCNTRL_MII_MODE
;
604 fecp
->fec_x_cntrl
= FEC_TCNTRL_FDEN
;
605 #else /* Half duplex mode */
606 fecp
->fec_r_cntrl
= FEC_RCNTRL_MII_MODE
| FEC_RCNTRL_DRT
;
607 fecp
->fec_x_cntrl
= 0;
610 /* Enable big endian and don't care about SDMA FC.
612 fecp
->fec_fun_code
= 0x78000000;
615 * Setup the pin configuration of the FEC
617 fec_pin_init (efis
->ether_index
);
623 * Now enable the transmit and receive processing
625 fecp
->fec_ecntrl
= FEC_ECNTRL_PINMUX
| FEC_ECNTRL_ETHER_EN
;
627 if (efis
->phy_addr
== -1) {
628 #ifdef CONFIG_SYS_DISCOVER_PHY
630 * wait for the PHY to wake up after reset
632 efis
->actual_phy_addr
= mii_discover_phy (dev
);
634 if (efis
->actual_phy_addr
== -1) {
635 printf ("Unable to discover phy!\n");
639 efis
->actual_phy_addr
= -1;
642 efis
->actual_phy_addr
= efis
->phy_addr
;
645 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
647 * adapt the RMII speed to the speed of the phy
649 if (miiphy_speed (dev
->name
, efis
->actual_phy_addr
) == _100BASET
) {
656 #if defined(CONFIG_MII)
658 * adapt to the half/full speed settings
660 if (miiphy_duplex (dev
->name
, efis
->actual_phy_addr
) == FULL
) {
661 fec_full_duplex (dev
);
663 fec_half_duplex (dev
);
667 /* And last, try to fill Rx Buffer Descriptors */
668 fecp
->fec_r_des_active
= 0x01000000; /* Descriptor polling active */
670 efis
->initialized
= 1;
676 static void fec_halt(struct eth_device
* dev
)
678 struct ether_fcc_info_s
*efis
= dev
->priv
;
679 volatile fec_t
*fecp
= (volatile fec_t
*)(CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
682 /* avoid halt if initialized; mii gets stuck otherwise */
683 if (!efis
->initialized
)
687 * A delay is required between a reset of the FEC block and
688 * initialization of other FEC registers because the reset takes
689 * some time to complete. If you don't delay, subsequent writes
690 * to FEC registers might get killed by the reset routine which is
694 fecp
->fec_ecntrl
= FEC_ECNTRL_PINMUX
| FEC_ECNTRL_RESET
;
696 (fecp
->fec_ecntrl
& FEC_ECNTRL_RESET
) && (i
< FEC_RESET_DELAY
);
700 if (i
== FEC_RESET_DELAY
) {
701 printf ("FEC_RESET_DELAY timeout\n");
705 efis
->initialized
= 0;
708 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
710 /* Make MII read/write commands for the FEC.
713 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
716 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
717 (REG & 0x1f) << 18) | \
720 /* Interrupt events/masks.
722 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
723 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
724 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
725 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
726 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
727 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
728 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
729 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
730 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
731 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
733 /* PHY identification
735 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
736 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
737 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
738 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
739 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
740 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
741 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
742 #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
743 #define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
745 /* send command to phy using mii, wait for result */
747 mii_send(uint mii_cmd
)
753 ep
= &(((immap_t
*)CONFIG_SYS_IMMR
)->im_cpm
.cp_fec
);
755 ep
->fec_mii_data
= mii_cmd
; /* command to phy */
757 /* wait for mii complete */
759 while (!(ep
->fec_ievent
& FEC_ENET_MII
)) {
761 printf("mii_send STUCK!\n");
765 mii_reply
= ep
->fec_mii_data
; /* result from phy */
766 ep
->fec_ievent
= FEC_ENET_MII
; /* clear MII complete */
768 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
769 __FILE__
,__LINE__
,__FUNCTION__
,mii_cmd
,mii_reply
);
771 return (mii_reply
& 0xffff); /* data read from phy */
775 #if defined(CONFIG_SYS_DISCOVER_PHY)
776 static int mii_discover_phy(struct eth_device
*dev
)
778 #define MAX_PHY_PASSES 11
784 phyaddr
= -1; /* didn't find a PHY yet */
785 for (pass
= 1; pass
<= MAX_PHY_PASSES
&& phyaddr
< 0; ++pass
) {
787 /* PHY may need more time to recover from reset.
788 * The LXT970 needs 50ms typical, no maximum is
789 * specified, so wait 10ms before try again.
790 * With 11 passes this gives it 100ms to wake up.
792 udelay(10000); /* wait 10ms */
794 for (phyno
= 0; phyno
< 32 && phyaddr
< 0; ++phyno
) {
795 phytype
= mii_send(mk_mii_read(phyno
, MII_PHYSID2
));
797 printf("PHY type 0x%x pass %d type ", phytype
, pass
);
799 if (phytype
!= 0xffff) {
801 phytype
|= mii_send(mk_mii_read(phyno
,
805 printf("PHY @ 0x%x pass %d type ",phyno
,pass
);
806 switch (phytype
& 0xfffffff0) {
819 case PHY_ID_AMD79C784
:
820 printf("AMD79C784\n");
822 case PHY_ID_LSI80225B
:
823 printf("LSI L80225/B\n");
826 printf("Davicom DM9161\n");
828 case PHY_ID_KSM8995M
:
829 printf("MICREL KS8995M\n");
832 printf("0x%08x\n", phytype
);
840 printf("No PHY device found.\n");
844 #endif /* CONFIG_SYS_DISCOVER_PHY */
846 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
848 /****************************************************************************
849 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
850 * This function is a subset of eth_init
851 ****************************************************************************
853 static void __mii_init(void)
855 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
856 volatile fec_t
*fecp
= &(immr
->im_cpm
.cp_fec
);
858 if (fec_reset(fecp
) < 0)
859 printf ("FEC_RESET_DELAY timeout\n");
861 /* We use strictly polling mode only
865 /* Clear any pending interrupt
867 fecp
->fec_ievent
= 0xffc0;
869 /* Now enable the transmit and receive processing
871 fecp
->fec_ecntrl
= FEC_ECNTRL_PINMUX
| FEC_ECNTRL_ETHER_EN
;
880 /* Setup the pin configuration of the FEC(s)
882 for (i
= 0; i
< sizeof(ether_fcc_info
) / sizeof(ether_fcc_info
[0]); i
++)
883 fec_pin_init(ether_fcc_info
[i
].ether_index
);
886 /*****************************************************************************
887 * Read and write a MII PHY register, routines used by MII Utilities
889 * FIXME: These routines are expected to return 0 on success, but mii_send
890 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
891 * no PHY connected...
892 * For now always return 0.
893 * FIXME: These routines only work after calling eth_init() at least once!
894 * Otherwise they hang in mii_send() !!! Sorry!
895 *****************************************************************************/
897 int fec8xx_miiphy_read(const char *devname
, unsigned char addr
,
898 unsigned char reg
, unsigned short *value
)
900 short rdreg
; /* register working value */
903 printf ("miiphy_read(0x%x) @ 0x%x = ", reg
, addr
);
905 rdreg
= mii_send(mk_mii_read(addr
, reg
));
909 printf ("0x%04x\n", *value
);
914 int fec8xx_miiphy_write(const char *devname
, unsigned char addr
,
915 unsigned char reg
, unsigned short value
)
918 printf ("miiphy_write(0x%x) @ 0x%x = ", reg
, addr
);
920 (void)mii_send(mk_mii_write(addr
, reg
, value
));
923 printf ("0x%04x\n", value
);