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[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8xx / fec.c
1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <malloc.h>
10 #include <commproc.h>
11 #include <net.h>
12 #include <command.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 #undef ET_DEBUG
17
18 #if defined(CONFIG_CMD_NET) && \
19 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
20
21 /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
22 #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
23 #define CONFIG_ETHER_ON_FEC1 1
24 #endif
25
26 /* define WANT_MII when MII support is required */
27 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
28 #define WANT_MII
29 #else
30 #undef WANT_MII
31 #endif
32
33 #if defined(WANT_MII)
34 #include <miiphy.h>
35
36 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
37 #error "CONFIG_MII has to be defined!"
38 #endif
39
40 #endif
41
42 #if defined(CONFIG_RMII) && !defined(WANT_MII)
43 #error RMII support is unusable without a working PHY.
44 #endif
45
46 #ifdef CONFIG_SYS_DISCOVER_PHY
47 static int mii_discover_phy(struct eth_device *dev);
48 #endif
49
50 int fec8xx_miiphy_read(const char *devname, unsigned char addr,
51 unsigned char reg, unsigned short *value);
52 int fec8xx_miiphy_write(const char *devname, unsigned char addr,
53 unsigned char reg, unsigned short value);
54
55 static struct ether_fcc_info_s
56 {
57 int ether_index;
58 int fecp_offset;
59 int phy_addr;
60 int actual_phy_addr;
61 int initialized;
62 }
63 ether_fcc_info[] = {
64 #if defined(CONFIG_ETHER_ON_FEC1)
65 {
66 0,
67 offsetof(immap_t, im_cpm.cp_fec1),
68 #if defined(CONFIG_FEC1_PHY)
69 CONFIG_FEC1_PHY,
70 #else
71 -1, /* discover */
72 #endif
73 -1,
74 0,
75
76 },
77 #endif
78 #if defined(CONFIG_ETHER_ON_FEC2)
79 {
80 1,
81 offsetof(immap_t, im_cpm.cp_fec2),
82 #if defined(CONFIG_FEC2_PHY)
83 CONFIG_FEC2_PHY,
84 #else
85 -1,
86 #endif
87 -1,
88 0,
89 },
90 #endif
91 };
92
93 /* Ethernet Transmit and Receive Buffers */
94 #define DBUF_LENGTH 1520
95
96 #define TX_BUF_CNT 2
97
98 #define TOUT_LOOP 100
99
100 #define PKT_MAXBUF_SIZE 1518
101 #define PKT_MINBUF_SIZE 64
102 #define PKT_MAXBLR_SIZE 1520
103
104 #ifdef __GNUC__
105 static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
106 #else
107 #error txbuf must be aligned.
108 #endif
109
110 static uint rxIdx; /* index of the current RX buffer */
111 static uint txIdx; /* index of the current TX buffer */
112
113 /*
114 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
115 * immr->udata_bd address on Dual-Port RAM
116 * Provide for Double Buffering
117 */
118
119 typedef volatile struct CommonBufferDescriptor {
120 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
121 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
122 } RTXBD;
123
124 static RTXBD *rtx = NULL;
125
126 static int fec_send(struct eth_device *dev, void *packet, int length);
127 static int fec_recv(struct eth_device* dev);
128 static int fec_init(struct eth_device* dev, bd_t * bd);
129 static void fec_halt(struct eth_device* dev);
130 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
131 static void __mii_init(void);
132 #endif
133
134 int fec_initialize(bd_t *bis)
135 {
136 struct eth_device* dev;
137 struct ether_fcc_info_s *efis;
138 int i;
139
140 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
141
142 dev = malloc(sizeof(*dev));
143 if (dev == NULL)
144 hang();
145
146 memset(dev, 0, sizeof(*dev));
147
148 /* for FEC1 make sure that the name of the interface is the same
149 as the old one for compatibility reasons */
150 if (i == 0) {
151 sprintf (dev->name, "FEC");
152 } else {
153 sprintf (dev->name, "FEC%d",
154 ether_fcc_info[i].ether_index + 1);
155 }
156
157 efis = &ether_fcc_info[i];
158
159 /*
160 * reset actual phy addr
161 */
162 efis->actual_phy_addr = -1;
163
164 dev->priv = efis;
165 dev->init = fec_init;
166 dev->halt = fec_halt;
167 dev->send = fec_send;
168 dev->recv = fec_recv;
169
170 eth_register(dev);
171
172 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
173 miiphy_register(dev->name,
174 fec8xx_miiphy_read, fec8xx_miiphy_write);
175 #endif
176 }
177 return 1;
178 }
179
180 static int fec_send(struct eth_device *dev, void *packet, int length)
181 {
182 int j, rc;
183 struct ether_fcc_info_s *efis = dev->priv;
184 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
185
186 /* section 16.9.23.3
187 * Wait for ready
188 */
189 j = 0;
190 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
191 udelay(1);
192 j++;
193 }
194 if (j>=TOUT_LOOP) {
195 printf("TX not ready\n");
196 }
197
198 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
199 rtx->txbd[txIdx].cbd_datlen = length;
200 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
201 __asm__ ("eieio");
202
203 /* Activate transmit Buffer Descriptor polling */
204 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
205
206 j = 0;
207 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
208 #if defined(CONFIG_ICU862)
209 udelay(10);
210 #else
211 udelay(1);
212 #endif
213 j++;
214 }
215 if (j>=TOUT_LOOP) {
216 printf("TX timeout\n");
217 }
218 #ifdef ET_DEBUG
219 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
220 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
221 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
222 #endif
223 /* return only status bits */;
224 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
225
226 txIdx = (txIdx + 1) % TX_BUF_CNT;
227
228 return rc;
229 }
230
231 static int fec_recv (struct eth_device *dev)
232 {
233 struct ether_fcc_info_s *efis = dev->priv;
234 volatile fec_t *fecp =
235 (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
236 int length;
237
238 for (;;) {
239 /* section 16.9.23.2 */
240 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
241 length = -1;
242 break; /* nothing received - leave for() loop */
243 }
244
245 length = rtx->rxbd[rxIdx].cbd_datlen;
246
247 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
248 #ifdef ET_DEBUG
249 printf ("%s[%d] err: %x\n",
250 __FUNCTION__, __LINE__,
251 rtx->rxbd[rxIdx].cbd_sc);
252 #endif
253 } else {
254 uchar *rx = NetRxPackets[rxIdx];
255
256 length -= 4;
257
258 #if defined(CONFIG_CMD_CDP)
259 if ((rx[0] & 1) != 0
260 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
261 && !is_cdp_packet((uchar *)rx))
262 rx = NULL;
263 #endif
264 /*
265 * Pass the packet up to the protocol layers.
266 */
267 if (rx != NULL)
268 NetReceive (rx, length);
269 }
270
271 /* Give the buffer back to the FEC. */
272 rtx->rxbd[rxIdx].cbd_datlen = 0;
273
274 /* wrap around buffer index when necessary */
275 if ((rxIdx + 1) >= PKTBUFSRX) {
276 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
277 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
278 rxIdx = 0;
279 } else {
280 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
281 rxIdx++;
282 }
283
284 __asm__ ("eieio");
285
286 /* Try to fill Buffer Descriptors */
287 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
288 }
289
290 return length;
291 }
292
293 /**************************************************************
294 *
295 * FEC Ethernet Initialization Routine
296 *
297 *************************************************************/
298
299 #define FEC_ECNTRL_PINMUX 0x00000004
300 #define FEC_ECNTRL_ETHER_EN 0x00000002
301 #define FEC_ECNTRL_RESET 0x00000001
302
303 #define FEC_RCNTRL_BC_REJ 0x00000010
304 #define FEC_RCNTRL_PROM 0x00000008
305 #define FEC_RCNTRL_MII_MODE 0x00000004
306 #define FEC_RCNTRL_DRT 0x00000002
307 #define FEC_RCNTRL_LOOP 0x00000001
308
309 #define FEC_TCNTRL_FDEN 0x00000004
310 #define FEC_TCNTRL_HBC 0x00000002
311 #define FEC_TCNTRL_GTS 0x00000001
312
313 #define FEC_RESET_DELAY 50
314
315 #if defined(CONFIG_RMII)
316
317 static inline void fec_10Mbps(struct eth_device *dev)
318 {
319 struct ether_fcc_info_s *efis = dev->priv;
320 int fecidx = efis->ether_index;
321 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
322
323 if ((unsigned int)fecidx >= 2)
324 hang();
325
326 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
327 }
328
329 static inline void fec_100Mbps(struct eth_device *dev)
330 {
331 struct ether_fcc_info_s *efis = dev->priv;
332 int fecidx = efis->ether_index;
333 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
334
335 if ((unsigned int)fecidx >= 2)
336 hang();
337
338 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
339 }
340
341 #endif
342
343 static inline void fec_full_duplex(struct eth_device *dev)
344 {
345 struct ether_fcc_info_s *efis = dev->priv;
346 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
347
348 fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
349 fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
350 }
351
352 static inline void fec_half_duplex(struct eth_device *dev)
353 {
354 struct ether_fcc_info_s *efis = dev->priv;
355 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
356
357 fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
358 fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
359 }
360
361 static void fec_pin_init(int fecidx)
362 {
363 bd_t *bd = gd->bd;
364 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
365
366 /*
367 * Set MII speed to 2.5 MHz or slightly below.
368 *
369 * According to the MPC860T (Rev. D) Fast ethernet controller user
370 * manual (6.2.14),
371 * the MII management interface clock must be less than or equal
372 * to 2.5 MHz.
373 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
374 * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
375 *
376 * All MII configuration is done via FEC1 registers:
377 */
378 immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
379
380 #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
381 {
382 volatile fec_t *fecp;
383
384 /*
385 * only two FECs please
386 */
387 if ((unsigned int)fecidx >= 2)
388 hang();
389
390 if (fecidx == 0)
391 fecp = &immr->im_cpm.cp_fec1;
392 else
393 fecp = &immr->im_cpm.cp_fec2;
394
395 /* our PHYs are the limit at 2.5 MHz */
396 fecp->fec_mii_speed <<= 1;
397 }
398 #endif
399
400 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
401 /* use MDC for MII */
402 immr->im_ioport.iop_pdpar |= 0x0080;
403 immr->im_ioport.iop_pddir &= ~0x0080;
404 #endif
405
406 if (fecidx == 0) {
407 #if defined(CONFIG_ETHER_ON_FEC1)
408
409 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
410
411 #if !defined(CONFIG_RMII)
412
413 immr->im_ioport.iop_papar |= 0xf830;
414 immr->im_ioport.iop_padir |= 0x0830;
415 immr->im_ioport.iop_padir &= ~0xf000;
416
417 immr->im_cpm.cp_pbpar |= 0x00001001;
418 immr->im_cpm.cp_pbdir &= ~0x00001001;
419
420 immr->im_ioport.iop_pcpar |= 0x000c;
421 immr->im_ioport.iop_pcdir &= ~0x000c;
422
423 immr->im_cpm.cp_pepar |= 0x00000003;
424 immr->im_cpm.cp_pedir |= 0x00000003;
425 immr->im_cpm.cp_peso &= ~0x00000003;
426
427 immr->im_cpm.cp_cptr &= ~0x00000100;
428
429 #else
430
431 #if !defined(CONFIG_FEC1_PHY_NORXERR)
432 immr->im_ioport.iop_papar |= 0x1000;
433 immr->im_ioport.iop_padir &= ~0x1000;
434 #endif
435 immr->im_ioport.iop_papar |= 0xe810;
436 immr->im_ioport.iop_padir |= 0x0810;
437 immr->im_ioport.iop_padir &= ~0xe000;
438
439 immr->im_cpm.cp_pbpar |= 0x00000001;
440 immr->im_cpm.cp_pbdir &= ~0x00000001;
441
442 immr->im_cpm.cp_cptr |= 0x00000100;
443 immr->im_cpm.cp_cptr &= ~0x00000050;
444
445 #endif /* !CONFIG_RMII */
446
447 #elif !defined(CONFIG_ICU862)
448 /*
449 * Configure all of port D for MII.
450 */
451 immr->im_ioport.iop_pdpar = 0x1fff;
452
453 /*
454 * Bits moved from Rev. D onward
455 */
456 if ((get_immr(0) & 0xffff) < 0x0501)
457 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
458 else
459 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
460 #else
461 /*
462 * Configure port A for MII.
463 */
464
465 #if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
466
467 /*
468 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
469 * * of CPU, so for this board we need to configure Utopia and
470 * * enable PD8 to MII-MDC function
471 */
472 immr->im_ioport.iop_pdpar |= 0x4080;
473 #endif
474
475 /*
476 * Has Utopia been configured?
477 */
478 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
479 /*
480 * YES - Use MUXED mode for UTOPIA bus.
481 * This frees Port A for use by MII (see 862UM table 41-6).
482 */
483 immr->im_ioport.utmode &= ~0x80;
484 } else {
485 /*
486 * NO - set SPLIT mode for UTOPIA bus.
487 *
488 * This doesn't really effect UTOPIA (which isn't
489 * enabled anyway) but just tells the 862
490 * to use port A for MII (see 862UM table 41-6).
491 */
492 immr->im_ioport.utmode |= 0x80;
493 }
494 #endif /* !defined(CONFIG_ICU862) */
495
496 #endif /* CONFIG_ETHER_ON_FEC1 */
497 } else if (fecidx == 1) {
498
499 #if defined(CONFIG_ETHER_ON_FEC2)
500
501 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
502
503 #if !defined(CONFIG_RMII)
504 immr->im_cpm.cp_pepar |= 0x0003fffc;
505 immr->im_cpm.cp_pedir |= 0x0003fffc;
506 immr->im_cpm.cp_peso &= ~0x000087fc;
507 immr->im_cpm.cp_peso |= 0x00037800;
508
509 immr->im_cpm.cp_cptr &= ~0x00000080;
510 #else
511
512 #if !defined(CONFIG_FEC2_PHY_NORXERR)
513 immr->im_cpm.cp_pepar |= 0x00000010;
514 immr->im_cpm.cp_pedir |= 0x00000010;
515 immr->im_cpm.cp_peso &= ~0x00000010;
516 #endif
517 immr->im_cpm.cp_pepar |= 0x00039620;
518 immr->im_cpm.cp_pedir |= 0x00039620;
519 immr->im_cpm.cp_peso |= 0x00031000;
520 immr->im_cpm.cp_peso &= ~0x00008620;
521
522 immr->im_cpm.cp_cptr |= 0x00000080;
523 immr->im_cpm.cp_cptr &= ~0x00000028;
524 #endif /* CONFIG_RMII */
525
526 #endif /* CONFIG_MPC885_FAMILY */
527
528 #endif /* CONFIG_ETHER_ON_FEC2 */
529
530 }
531 }
532
533 static int fec_reset(volatile fec_t *fecp)
534 {
535 int i;
536
537 /* Whack a reset.
538 * A delay is required between a reset of the FEC block and
539 * initialization of other FEC registers because the reset takes
540 * some time to complete. If you don't delay, subsequent writes
541 * to FEC registers might get killed by the reset routine which is
542 * still in progress.
543 */
544
545 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
546 for (i = 0;
547 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
548 ++i) {
549 udelay (1);
550 }
551 if (i == FEC_RESET_DELAY)
552 return -1;
553
554 return 0;
555 }
556
557 static int fec_init (struct eth_device *dev, bd_t * bd)
558 {
559 struct ether_fcc_info_s *efis = dev->priv;
560 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
561 volatile fec_t *fecp =
562 (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
563 int i;
564
565 if (efis->ether_index == 0) {
566 #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
567 #if defined(CONFIG_MPC885ADS)
568 *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
569 #else
570 /* configure FADS for fast (FEC) ethernet, half-duplex */
571 /* The LXT970 needs about 50ms to recover from reset, so
572 * wait for it by discovering the PHY before leaving eth_init().
573 */
574 {
575 volatile uint *bcsr4 = (volatile uint *) BCSR4;
576
577 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
578 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
579 BCSR4_FETHRST);
580
581 /* reset the LXT970 PHY */
582 *bcsr4 &= ~BCSR4_FETHRST;
583 udelay (10);
584 *bcsr4 |= BCSR4_FETHRST;
585 udelay (10);
586 }
587 #endif /* CONFIG_MPC885ADS */
588 #endif /* CONFIG_FADS */
589 }
590
591 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
592 /* the MII interface is connected to FEC1
593 * so for the miiphy_xxx function to work we must
594 * call mii_init since fec_halt messes the thing up
595 */
596 if (efis->ether_index != 0)
597 __mii_init();
598 #endif
599
600 if (fec_reset(fecp) < 0)
601 printf ("FEC_RESET_DELAY timeout\n");
602
603 /* We use strictly polling mode only
604 */
605 fecp->fec_imask = 0;
606
607 /* Clear any pending interrupt
608 */
609 fecp->fec_ievent = 0xffc0;
610
611 /* No need to set the IVEC register */
612
613 /* Set station address
614 */
615 #define ea dev->enetaddr
616 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
617 fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
618 #undef ea
619
620 #if defined(CONFIG_CMD_CDP)
621 /*
622 * Turn on multicast address hash table
623 */
624 fecp->fec_hash_table_high = 0xffffffff;
625 fecp->fec_hash_table_low = 0xffffffff;
626 #else
627 /* Clear multicast address hash table
628 */
629 fecp->fec_hash_table_high = 0;
630 fecp->fec_hash_table_low = 0;
631 #endif
632
633 /* Set maximum receive buffer size.
634 */
635 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
636
637 /* Set maximum frame length
638 */
639 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
640
641 /*
642 * Setup Buffers and Buffer Desriptors
643 */
644 rxIdx = 0;
645 txIdx = 0;
646
647 if (!rtx) {
648 #ifdef CONFIG_SYS_ALLOC_DPRAM
649 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
650 dpram_alloc_align (sizeof (RTXBD), 8));
651 #else
652 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
653 #endif
654 }
655 /*
656 * Setup Receiver Buffer Descriptors (13.14.24.18)
657 * Settings:
658 * Empty, Wrap
659 */
660 for (i = 0; i < PKTBUFSRX; i++) {
661 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
662 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
663 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
664 }
665 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
666
667 /*
668 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
669 * Settings:
670 * Last, Tx CRC
671 */
672 for (i = 0; i < TX_BUF_CNT; i++) {
673 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
674 rtx->txbd[i].cbd_datlen = 0; /* Reset */
675 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
676 }
677 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
678
679 /* Set receive and transmit descriptor base
680 */
681 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
682 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
683
684 /* Enable MII mode
685 */
686 #if 0 /* Full duplex mode */
687 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
688 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
689 #else /* Half duplex mode */
690 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
691 fecp->fec_x_cntrl = 0;
692 #endif
693
694 /* Enable big endian and don't care about SDMA FC.
695 */
696 fecp->fec_fun_code = 0x78000000;
697
698 /*
699 * Setup the pin configuration of the FEC
700 */
701 fec_pin_init (efis->ether_index);
702
703 rxIdx = 0;
704 txIdx = 0;
705
706 /*
707 * Now enable the transmit and receive processing
708 */
709 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
710
711 if (efis->phy_addr == -1) {
712 #ifdef CONFIG_SYS_DISCOVER_PHY
713 /*
714 * wait for the PHY to wake up after reset
715 */
716 efis->actual_phy_addr = mii_discover_phy (dev);
717
718 if (efis->actual_phy_addr == -1) {
719 printf ("Unable to discover phy!\n");
720 return -1;
721 }
722 #else
723 efis->actual_phy_addr = -1;
724 #endif
725 } else {
726 efis->actual_phy_addr = efis->phy_addr;
727 }
728
729 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
730 /*
731 * adapt the RMII speed to the speed of the phy
732 */
733 if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
734 fec_100Mbps (dev);
735 } else {
736 fec_10Mbps (dev);
737 }
738 #endif
739
740 #if defined(CONFIG_MII)
741 /*
742 * adapt to the half/full speed settings
743 */
744 if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
745 fec_full_duplex (dev);
746 } else {
747 fec_half_duplex (dev);
748 }
749 #endif
750
751 /* And last, try to fill Rx Buffer Descriptors */
752 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
753
754 efis->initialized = 1;
755
756 return 0;
757 }
758
759
760 static void fec_halt(struct eth_device* dev)
761 {
762 struct ether_fcc_info_s *efis = dev->priv;
763 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
764 int i;
765
766 /* avoid halt if initialized; mii gets stuck otherwise */
767 if (!efis->initialized)
768 return;
769
770 /* Whack a reset.
771 * A delay is required between a reset of the FEC block and
772 * initialization of other FEC registers because the reset takes
773 * some time to complete. If you don't delay, subsequent writes
774 * to FEC registers might get killed by the reset routine which is
775 * still in progress.
776 */
777
778 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
779 for (i = 0;
780 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
781 ++i) {
782 udelay (1);
783 }
784 if (i == FEC_RESET_DELAY) {
785 printf ("FEC_RESET_DELAY timeout\n");
786 return;
787 }
788
789 efis->initialized = 0;
790 }
791
792 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
793
794 /* Make MII read/write commands for the FEC.
795 */
796
797 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
798 (REG & 0x1f) << 18))
799
800 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
801 (REG & 0x1f) << 18) | \
802 (VAL & 0xffff))
803
804 /* Interrupt events/masks.
805 */
806 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
807 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
808 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
809 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
810 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
811 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
812 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
813 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
814 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
815 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
816
817 /* PHY identification
818 */
819 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
820 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
821 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
822 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
823 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
824 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
825 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
826 #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
827 #define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
828
829 /* send command to phy using mii, wait for result */
830 static uint
831 mii_send(uint mii_cmd)
832 {
833 uint mii_reply;
834 volatile fec_t *ep;
835 int cnt;
836
837 ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
838
839 ep->fec_mii_data = mii_cmd; /* command to phy */
840
841 /* wait for mii complete */
842 cnt = 0;
843 while (!(ep->fec_ievent & FEC_ENET_MII)) {
844 if (++cnt > 1000) {
845 printf("mii_send STUCK!\n");
846 break;
847 }
848 }
849 mii_reply = ep->fec_mii_data; /* result from phy */
850 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
851 #if 0
852 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
853 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
854 #endif
855 return (mii_reply & 0xffff); /* data read from phy */
856 }
857 #endif
858
859 #if defined(CONFIG_SYS_DISCOVER_PHY)
860 static int mii_discover_phy(struct eth_device *dev)
861 {
862 #define MAX_PHY_PASSES 11
863 uint phyno;
864 int pass;
865 uint phytype;
866 int phyaddr;
867
868 phyaddr = -1; /* didn't find a PHY yet */
869 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
870 if (pass > 1) {
871 /* PHY may need more time to recover from reset.
872 * The LXT970 needs 50ms typical, no maximum is
873 * specified, so wait 10ms before try again.
874 * With 11 passes this gives it 100ms to wake up.
875 */
876 udelay(10000); /* wait 10ms */
877 }
878 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
879 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
880 #ifdef ET_DEBUG
881 printf("PHY type 0x%x pass %d type ", phytype, pass);
882 #endif
883 if (phytype != 0xffff) {
884 phyaddr = phyno;
885 phytype |= mii_send(mk_mii_read(phyno,
886 MII_PHYSID1)) << 16;
887
888 #ifdef ET_DEBUG
889 printf("PHY @ 0x%x pass %d type ",phyno,pass);
890 switch (phytype & 0xfffffff0) {
891 case PHY_ID_LXT970:
892 printf("LXT970\n");
893 break;
894 case PHY_ID_LXT971:
895 printf("LXT971\n");
896 break;
897 case PHY_ID_82555:
898 printf("82555\n");
899 break;
900 case PHY_ID_QS6612:
901 printf("QS6612\n");
902 break;
903 case PHY_ID_AMD79C784:
904 printf("AMD79C784\n");
905 break;
906 case PHY_ID_LSI80225B:
907 printf("LSI L80225/B\n");
908 break;
909 case PHY_ID_DM9161:
910 printf("Davicom DM9161\n");
911 break;
912 case PHY_ID_KSM8995M:
913 printf("MICREL KS8995M\n");
914 break;
915 default:
916 printf("0x%08x\n", phytype);
917 break;
918 }
919 #endif
920 }
921 }
922 }
923 if (phyaddr < 0) {
924 printf("No PHY device found.\n");
925 }
926 return phyaddr;
927 }
928 #endif /* CONFIG_SYS_DISCOVER_PHY */
929
930 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
931
932 /****************************************************************************
933 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
934 * This function is a subset of eth_init
935 ****************************************************************************
936 */
937 static void __mii_init(void)
938 {
939 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
940 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
941
942 if (fec_reset(fecp) < 0)
943 printf ("FEC_RESET_DELAY timeout\n");
944
945 /* We use strictly polling mode only
946 */
947 fecp->fec_imask = 0;
948
949 /* Clear any pending interrupt
950 */
951 fecp->fec_ievent = 0xffc0;
952
953 /* Now enable the transmit and receive processing
954 */
955 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
956 }
957
958 void mii_init (void)
959 {
960 int i;
961
962 __mii_init();
963
964 /* Setup the pin configuration of the FEC(s)
965 */
966 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
967 fec_pin_init(ether_fcc_info[i].ether_index);
968 }
969
970 /*****************************************************************************
971 * Read and write a MII PHY register, routines used by MII Utilities
972 *
973 * FIXME: These routines are expected to return 0 on success, but mii_send
974 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
975 * no PHY connected...
976 * For now always return 0.
977 * FIXME: These routines only work after calling eth_init() at least once!
978 * Otherwise they hang in mii_send() !!! Sorry!
979 *****************************************************************************/
980
981 int fec8xx_miiphy_read(const char *devname, unsigned char addr,
982 unsigned char reg, unsigned short *value)
983 {
984 short rdreg; /* register working value */
985
986 #ifdef MII_DEBUG
987 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
988 #endif
989 rdreg = mii_send(mk_mii_read(addr, reg));
990
991 *value = rdreg;
992 #ifdef MII_DEBUG
993 printf ("0x%04x\n", *value);
994 #endif
995 return 0;
996 }
997
998 int fec8xx_miiphy_write(const char *devname, unsigned char addr,
999 unsigned char reg, unsigned short value)
1000 {
1001 #ifdef MII_DEBUG
1002 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
1003 #endif
1004 (void)mii_send(mk_mii_write(addr, reg, value));
1005
1006 #ifdef MII_DEBUG
1007 printf ("0x%04x\n", value);
1008 #endif
1009 return 0;
1010 }
1011 #endif
1012
1013 #endif
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