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mpc8xx: remove netta, netta2, netphone board support
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8xx / fec.c
1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <malloc.h>
10 #include <commproc.h>
11 #include <net.h>
12 #include <command.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 #undef ET_DEBUG
17
18 #if defined(CONFIG_CMD_NET) && \
19 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
20
21 /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
22 #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
23 #define CONFIG_ETHER_ON_FEC1 1
24 #endif
25
26 /* define WANT_MII when MII support is required */
27 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
28 #define WANT_MII
29 #else
30 #undef WANT_MII
31 #endif
32
33 #if defined(WANT_MII)
34 #include <miiphy.h>
35
36 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
37 #error "CONFIG_MII has to be defined!"
38 #endif
39
40 #endif
41
42 #if defined(CONFIG_RMII) && !defined(WANT_MII)
43 #error RMII support is unusable without a working PHY.
44 #endif
45
46 #ifdef CONFIG_SYS_DISCOVER_PHY
47 static int mii_discover_phy(struct eth_device *dev);
48 #endif
49
50 int fec8xx_miiphy_read(const char *devname, unsigned char addr,
51 unsigned char reg, unsigned short *value);
52 int fec8xx_miiphy_write(const char *devname, unsigned char addr,
53 unsigned char reg, unsigned short value);
54
55 static struct ether_fcc_info_s
56 {
57 int ether_index;
58 int fecp_offset;
59 int phy_addr;
60 int actual_phy_addr;
61 int initialized;
62 }
63 ether_fcc_info[] = {
64 #if defined(CONFIG_ETHER_ON_FEC1)
65 {
66 0,
67 offsetof(immap_t, im_cpm.cp_fec1),
68 #if defined(CONFIG_FEC1_PHY)
69 CONFIG_FEC1_PHY,
70 #else
71 -1, /* discover */
72 #endif
73 -1,
74 0,
75
76 },
77 #endif
78 #if defined(CONFIG_ETHER_ON_FEC2)
79 {
80 1,
81 offsetof(immap_t, im_cpm.cp_fec2),
82 #if defined(CONFIG_FEC2_PHY)
83 CONFIG_FEC2_PHY,
84 #else
85 -1,
86 #endif
87 -1,
88 0,
89 },
90 #endif
91 };
92
93 /* Ethernet Transmit and Receive Buffers */
94 #define DBUF_LENGTH 1520
95
96 #define TX_BUF_CNT 2
97
98 #define TOUT_LOOP 100
99
100 #define PKT_MAXBUF_SIZE 1518
101 #define PKT_MINBUF_SIZE 64
102 #define PKT_MAXBLR_SIZE 1520
103
104 #ifdef __GNUC__
105 static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
106 #else
107 #error txbuf must be aligned.
108 #endif
109
110 static uint rxIdx; /* index of the current RX buffer */
111 static uint txIdx; /* index of the current TX buffer */
112
113 /*
114 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
115 * immr->udata_bd address on Dual-Port RAM
116 * Provide for Double Buffering
117 */
118
119 typedef volatile struct CommonBufferDescriptor {
120 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
121 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
122 } RTXBD;
123
124 static RTXBD *rtx = NULL;
125
126 static int fec_send(struct eth_device *dev, void *packet, int length);
127 static int fec_recv(struct eth_device* dev);
128 static int fec_init(struct eth_device* dev, bd_t * bd);
129 static void fec_halt(struct eth_device* dev);
130 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
131 static void __mii_init(void);
132 #endif
133
134 int fec_initialize(bd_t *bis)
135 {
136 struct eth_device* dev;
137 struct ether_fcc_info_s *efis;
138 int i;
139
140 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
141
142 dev = malloc(sizeof(*dev));
143 if (dev == NULL)
144 hang();
145
146 memset(dev, 0, sizeof(*dev));
147
148 /* for FEC1 make sure that the name of the interface is the same
149 as the old one for compatibility reasons */
150 if (i == 0) {
151 sprintf (dev->name, "FEC");
152 } else {
153 sprintf (dev->name, "FEC%d",
154 ether_fcc_info[i].ether_index + 1);
155 }
156
157 efis = &ether_fcc_info[i];
158
159 /*
160 * reset actual phy addr
161 */
162 efis->actual_phy_addr = -1;
163
164 dev->priv = efis;
165 dev->init = fec_init;
166 dev->halt = fec_halt;
167 dev->send = fec_send;
168 dev->recv = fec_recv;
169
170 eth_register(dev);
171
172 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
173 miiphy_register(dev->name,
174 fec8xx_miiphy_read, fec8xx_miiphy_write);
175 #endif
176 }
177 return 1;
178 }
179
180 static int fec_send(struct eth_device *dev, void *packet, int length)
181 {
182 int j, rc;
183 struct ether_fcc_info_s *efis = dev->priv;
184 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
185
186 /* section 16.9.23.3
187 * Wait for ready
188 */
189 j = 0;
190 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
191 udelay(1);
192 j++;
193 }
194 if (j>=TOUT_LOOP) {
195 printf("TX not ready\n");
196 }
197
198 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
199 rtx->txbd[txIdx].cbd_datlen = length;
200 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
201 __asm__ ("eieio");
202
203 /* Activate transmit Buffer Descriptor polling */
204 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
205
206 j = 0;
207 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
208 #if defined(CONFIG_ICU862)
209 udelay(10);
210 #else
211 udelay(1);
212 #endif
213 j++;
214 }
215 if (j>=TOUT_LOOP) {
216 printf("TX timeout\n");
217 }
218 #ifdef ET_DEBUG
219 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
220 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
221 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
222 #endif
223 /* return only status bits */;
224 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
225
226 txIdx = (txIdx + 1) % TX_BUF_CNT;
227
228 return rc;
229 }
230
231 static int fec_recv (struct eth_device *dev)
232 {
233 struct ether_fcc_info_s *efis = dev->priv;
234 volatile fec_t *fecp =
235 (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
236 int length;
237
238 for (;;) {
239 /* section 16.9.23.2 */
240 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
241 length = -1;
242 break; /* nothing received - leave for() loop */
243 }
244
245 length = rtx->rxbd[rxIdx].cbd_datlen;
246
247 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
248 #ifdef ET_DEBUG
249 printf ("%s[%d] err: %x\n",
250 __FUNCTION__, __LINE__,
251 rtx->rxbd[rxIdx].cbd_sc);
252 #endif
253 } else {
254 uchar *rx = NetRxPackets[rxIdx];
255
256 length -= 4;
257
258 #if defined(CONFIG_CMD_CDP)
259 if ((rx[0] & 1) != 0
260 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
261 && !is_cdp_packet((uchar *)rx))
262 rx = NULL;
263 #endif
264 /*
265 * Pass the packet up to the protocol layers.
266 */
267 if (rx != NULL)
268 NetReceive (rx, length);
269 }
270
271 /* Give the buffer back to the FEC. */
272 rtx->rxbd[rxIdx].cbd_datlen = 0;
273
274 /* wrap around buffer index when necessary */
275 if ((rxIdx + 1) >= PKTBUFSRX) {
276 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
277 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
278 rxIdx = 0;
279 } else {
280 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
281 rxIdx++;
282 }
283
284 __asm__ ("eieio");
285
286 /* Try to fill Buffer Descriptors */
287 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
288 }
289
290 return length;
291 }
292
293 /**************************************************************
294 *
295 * FEC Ethernet Initialization Routine
296 *
297 *************************************************************/
298
299 #define FEC_ECNTRL_PINMUX 0x00000004
300 #define FEC_ECNTRL_ETHER_EN 0x00000002
301 #define FEC_ECNTRL_RESET 0x00000001
302
303 #define FEC_RCNTRL_BC_REJ 0x00000010
304 #define FEC_RCNTRL_PROM 0x00000008
305 #define FEC_RCNTRL_MII_MODE 0x00000004
306 #define FEC_RCNTRL_DRT 0x00000002
307 #define FEC_RCNTRL_LOOP 0x00000001
308
309 #define FEC_TCNTRL_FDEN 0x00000004
310 #define FEC_TCNTRL_HBC 0x00000002
311 #define FEC_TCNTRL_GTS 0x00000001
312
313 #define FEC_RESET_DELAY 50
314
315 #if defined(CONFIG_RMII)
316
317 static inline void fec_10Mbps(struct eth_device *dev)
318 {
319 struct ether_fcc_info_s *efis = dev->priv;
320 int fecidx = efis->ether_index;
321 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
322
323 if ((unsigned int)fecidx >= 2)
324 hang();
325
326 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
327 }
328
329 static inline void fec_100Mbps(struct eth_device *dev)
330 {
331 struct ether_fcc_info_s *efis = dev->priv;
332 int fecidx = efis->ether_index;
333 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
334
335 if ((unsigned int)fecidx >= 2)
336 hang();
337
338 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
339 }
340
341 #endif
342
343 static inline void fec_full_duplex(struct eth_device *dev)
344 {
345 struct ether_fcc_info_s *efis = dev->priv;
346 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
347
348 fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
349 fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
350 }
351
352 static inline void fec_half_duplex(struct eth_device *dev)
353 {
354 struct ether_fcc_info_s *efis = dev->priv;
355 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
356
357 fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
358 fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
359 }
360
361 static void fec_pin_init(int fecidx)
362 {
363 bd_t *bd = gd->bd;
364 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
365
366 /*
367 * Set MII speed to 2.5 MHz or slightly below.
368 *
369 * According to the MPC860T (Rev. D) Fast ethernet controller user
370 * manual (6.2.14),
371 * the MII management interface clock must be less than or equal
372 * to 2.5 MHz.
373 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
374 * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
375 *
376 * All MII configuration is done via FEC1 registers:
377 */
378 immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
379
380 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
381 /* use MDC for MII */
382 immr->im_ioport.iop_pdpar |= 0x0080;
383 immr->im_ioport.iop_pddir &= ~0x0080;
384 #endif
385
386 if (fecidx == 0) {
387 #if defined(CONFIG_ETHER_ON_FEC1)
388
389 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
390
391 #if !defined(CONFIG_RMII)
392
393 immr->im_ioport.iop_papar |= 0xf830;
394 immr->im_ioport.iop_padir |= 0x0830;
395 immr->im_ioport.iop_padir &= ~0xf000;
396
397 immr->im_cpm.cp_pbpar |= 0x00001001;
398 immr->im_cpm.cp_pbdir &= ~0x00001001;
399
400 immr->im_ioport.iop_pcpar |= 0x000c;
401 immr->im_ioport.iop_pcdir &= ~0x000c;
402
403 immr->im_cpm.cp_pepar |= 0x00000003;
404 immr->im_cpm.cp_pedir |= 0x00000003;
405 immr->im_cpm.cp_peso &= ~0x00000003;
406
407 immr->im_cpm.cp_cptr &= ~0x00000100;
408
409 #else
410
411 #if !defined(CONFIG_FEC1_PHY_NORXERR)
412 immr->im_ioport.iop_papar |= 0x1000;
413 immr->im_ioport.iop_padir &= ~0x1000;
414 #endif
415 immr->im_ioport.iop_papar |= 0xe810;
416 immr->im_ioport.iop_padir |= 0x0810;
417 immr->im_ioport.iop_padir &= ~0xe000;
418
419 immr->im_cpm.cp_pbpar |= 0x00000001;
420 immr->im_cpm.cp_pbdir &= ~0x00000001;
421
422 immr->im_cpm.cp_cptr |= 0x00000100;
423 immr->im_cpm.cp_cptr &= ~0x00000050;
424
425 #endif /* !CONFIG_RMII */
426
427 #elif !defined(CONFIG_ICU862)
428 /*
429 * Configure all of port D for MII.
430 */
431 immr->im_ioport.iop_pdpar = 0x1fff;
432
433 /*
434 * Bits moved from Rev. D onward
435 */
436 if ((get_immr(0) & 0xffff) < 0x0501)
437 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
438 else
439 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
440 #else
441 /*
442 * Configure port A for MII.
443 */
444
445 #if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
446
447 /*
448 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
449 * * of CPU, so for this board we need to configure Utopia and
450 * * enable PD8 to MII-MDC function
451 */
452 immr->im_ioport.iop_pdpar |= 0x4080;
453 #endif
454
455 /*
456 * Has Utopia been configured?
457 */
458 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
459 /*
460 * YES - Use MUXED mode for UTOPIA bus.
461 * This frees Port A for use by MII (see 862UM table 41-6).
462 */
463 immr->im_ioport.utmode &= ~0x80;
464 } else {
465 /*
466 * NO - set SPLIT mode for UTOPIA bus.
467 *
468 * This doesn't really effect UTOPIA (which isn't
469 * enabled anyway) but just tells the 862
470 * to use port A for MII (see 862UM table 41-6).
471 */
472 immr->im_ioport.utmode |= 0x80;
473 }
474 #endif /* !defined(CONFIG_ICU862) */
475
476 #endif /* CONFIG_ETHER_ON_FEC1 */
477 } else if (fecidx == 1) {
478
479 #if defined(CONFIG_ETHER_ON_FEC2)
480
481 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
482
483 #if !defined(CONFIG_RMII)
484 immr->im_cpm.cp_pepar |= 0x0003fffc;
485 immr->im_cpm.cp_pedir |= 0x0003fffc;
486 immr->im_cpm.cp_peso &= ~0x000087fc;
487 immr->im_cpm.cp_peso |= 0x00037800;
488
489 immr->im_cpm.cp_cptr &= ~0x00000080;
490 #else
491
492 #if !defined(CONFIG_FEC2_PHY_NORXERR)
493 immr->im_cpm.cp_pepar |= 0x00000010;
494 immr->im_cpm.cp_pedir |= 0x00000010;
495 immr->im_cpm.cp_peso &= ~0x00000010;
496 #endif
497 immr->im_cpm.cp_pepar |= 0x00039620;
498 immr->im_cpm.cp_pedir |= 0x00039620;
499 immr->im_cpm.cp_peso |= 0x00031000;
500 immr->im_cpm.cp_peso &= ~0x00008620;
501
502 immr->im_cpm.cp_cptr |= 0x00000080;
503 immr->im_cpm.cp_cptr &= ~0x00000028;
504 #endif /* CONFIG_RMII */
505
506 #endif /* CONFIG_MPC885_FAMILY */
507
508 #endif /* CONFIG_ETHER_ON_FEC2 */
509
510 }
511 }
512
513 static int fec_reset(volatile fec_t *fecp)
514 {
515 int i;
516
517 /* Whack a reset.
518 * A delay is required between a reset of the FEC block and
519 * initialization of other FEC registers because the reset takes
520 * some time to complete. If you don't delay, subsequent writes
521 * to FEC registers might get killed by the reset routine which is
522 * still in progress.
523 */
524
525 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
526 for (i = 0;
527 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
528 ++i) {
529 udelay (1);
530 }
531 if (i == FEC_RESET_DELAY)
532 return -1;
533
534 return 0;
535 }
536
537 static int fec_init (struct eth_device *dev, bd_t * bd)
538 {
539 struct ether_fcc_info_s *efis = dev->priv;
540 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
541 volatile fec_t *fecp =
542 (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
543 int i;
544
545 if (efis->ether_index == 0) {
546 #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
547 #if defined(CONFIG_MPC885ADS)
548 *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
549 #else
550 /* configure FADS for fast (FEC) ethernet, half-duplex */
551 /* The LXT970 needs about 50ms to recover from reset, so
552 * wait for it by discovering the PHY before leaving eth_init().
553 */
554 {
555 volatile uint *bcsr4 = (volatile uint *) BCSR4;
556
557 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
558 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
559 BCSR4_FETHRST);
560
561 /* reset the LXT970 PHY */
562 *bcsr4 &= ~BCSR4_FETHRST;
563 udelay (10);
564 *bcsr4 |= BCSR4_FETHRST;
565 udelay (10);
566 }
567 #endif /* CONFIG_MPC885ADS */
568 #endif /* CONFIG_FADS */
569 }
570
571 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
572 /* the MII interface is connected to FEC1
573 * so for the miiphy_xxx function to work we must
574 * call mii_init since fec_halt messes the thing up
575 */
576 if (efis->ether_index != 0)
577 __mii_init();
578 #endif
579
580 if (fec_reset(fecp) < 0)
581 printf ("FEC_RESET_DELAY timeout\n");
582
583 /* We use strictly polling mode only
584 */
585 fecp->fec_imask = 0;
586
587 /* Clear any pending interrupt
588 */
589 fecp->fec_ievent = 0xffc0;
590
591 /* No need to set the IVEC register */
592
593 /* Set station address
594 */
595 #define ea dev->enetaddr
596 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
597 fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
598 #undef ea
599
600 #if defined(CONFIG_CMD_CDP)
601 /*
602 * Turn on multicast address hash table
603 */
604 fecp->fec_hash_table_high = 0xffffffff;
605 fecp->fec_hash_table_low = 0xffffffff;
606 #else
607 /* Clear multicast address hash table
608 */
609 fecp->fec_hash_table_high = 0;
610 fecp->fec_hash_table_low = 0;
611 #endif
612
613 /* Set maximum receive buffer size.
614 */
615 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
616
617 /* Set maximum frame length
618 */
619 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
620
621 /*
622 * Setup Buffers and Buffer Desriptors
623 */
624 rxIdx = 0;
625 txIdx = 0;
626
627 if (!rtx) {
628 #ifdef CONFIG_SYS_ALLOC_DPRAM
629 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
630 dpram_alloc_align (sizeof (RTXBD), 8));
631 #else
632 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
633 #endif
634 }
635 /*
636 * Setup Receiver Buffer Descriptors (13.14.24.18)
637 * Settings:
638 * Empty, Wrap
639 */
640 for (i = 0; i < PKTBUFSRX; i++) {
641 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
642 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
643 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
644 }
645 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
646
647 /*
648 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
649 * Settings:
650 * Last, Tx CRC
651 */
652 for (i = 0; i < TX_BUF_CNT; i++) {
653 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
654 rtx->txbd[i].cbd_datlen = 0; /* Reset */
655 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
656 }
657 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
658
659 /* Set receive and transmit descriptor base
660 */
661 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
662 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
663
664 /* Enable MII mode
665 */
666 #if 0 /* Full duplex mode */
667 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
668 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
669 #else /* Half duplex mode */
670 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
671 fecp->fec_x_cntrl = 0;
672 #endif
673
674 /* Enable big endian and don't care about SDMA FC.
675 */
676 fecp->fec_fun_code = 0x78000000;
677
678 /*
679 * Setup the pin configuration of the FEC
680 */
681 fec_pin_init (efis->ether_index);
682
683 rxIdx = 0;
684 txIdx = 0;
685
686 /*
687 * Now enable the transmit and receive processing
688 */
689 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
690
691 if (efis->phy_addr == -1) {
692 #ifdef CONFIG_SYS_DISCOVER_PHY
693 /*
694 * wait for the PHY to wake up after reset
695 */
696 efis->actual_phy_addr = mii_discover_phy (dev);
697
698 if (efis->actual_phy_addr == -1) {
699 printf ("Unable to discover phy!\n");
700 return -1;
701 }
702 #else
703 efis->actual_phy_addr = -1;
704 #endif
705 } else {
706 efis->actual_phy_addr = efis->phy_addr;
707 }
708
709 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
710 /*
711 * adapt the RMII speed to the speed of the phy
712 */
713 if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
714 fec_100Mbps (dev);
715 } else {
716 fec_10Mbps (dev);
717 }
718 #endif
719
720 #if defined(CONFIG_MII)
721 /*
722 * adapt to the half/full speed settings
723 */
724 if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
725 fec_full_duplex (dev);
726 } else {
727 fec_half_duplex (dev);
728 }
729 #endif
730
731 /* And last, try to fill Rx Buffer Descriptors */
732 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
733
734 efis->initialized = 1;
735
736 return 0;
737 }
738
739
740 static void fec_halt(struct eth_device* dev)
741 {
742 struct ether_fcc_info_s *efis = dev->priv;
743 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
744 int i;
745
746 /* avoid halt if initialized; mii gets stuck otherwise */
747 if (!efis->initialized)
748 return;
749
750 /* Whack a reset.
751 * A delay is required between a reset of the FEC block and
752 * initialization of other FEC registers because the reset takes
753 * some time to complete. If you don't delay, subsequent writes
754 * to FEC registers might get killed by the reset routine which is
755 * still in progress.
756 */
757
758 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
759 for (i = 0;
760 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
761 ++i) {
762 udelay (1);
763 }
764 if (i == FEC_RESET_DELAY) {
765 printf ("FEC_RESET_DELAY timeout\n");
766 return;
767 }
768
769 efis->initialized = 0;
770 }
771
772 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
773
774 /* Make MII read/write commands for the FEC.
775 */
776
777 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
778 (REG & 0x1f) << 18))
779
780 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
781 (REG & 0x1f) << 18) | \
782 (VAL & 0xffff))
783
784 /* Interrupt events/masks.
785 */
786 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
787 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
788 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
789 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
790 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
791 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
792 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
793 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
794 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
795 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
796
797 /* PHY identification
798 */
799 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
800 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
801 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
802 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
803 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
804 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
805 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
806 #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
807 #define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
808
809 /* send command to phy using mii, wait for result */
810 static uint
811 mii_send(uint mii_cmd)
812 {
813 uint mii_reply;
814 volatile fec_t *ep;
815 int cnt;
816
817 ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
818
819 ep->fec_mii_data = mii_cmd; /* command to phy */
820
821 /* wait for mii complete */
822 cnt = 0;
823 while (!(ep->fec_ievent & FEC_ENET_MII)) {
824 if (++cnt > 1000) {
825 printf("mii_send STUCK!\n");
826 break;
827 }
828 }
829 mii_reply = ep->fec_mii_data; /* result from phy */
830 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
831 #if 0
832 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
833 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
834 #endif
835 return (mii_reply & 0xffff); /* data read from phy */
836 }
837 #endif
838
839 #if defined(CONFIG_SYS_DISCOVER_PHY)
840 static int mii_discover_phy(struct eth_device *dev)
841 {
842 #define MAX_PHY_PASSES 11
843 uint phyno;
844 int pass;
845 uint phytype;
846 int phyaddr;
847
848 phyaddr = -1; /* didn't find a PHY yet */
849 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
850 if (pass > 1) {
851 /* PHY may need more time to recover from reset.
852 * The LXT970 needs 50ms typical, no maximum is
853 * specified, so wait 10ms before try again.
854 * With 11 passes this gives it 100ms to wake up.
855 */
856 udelay(10000); /* wait 10ms */
857 }
858 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
859 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
860 #ifdef ET_DEBUG
861 printf("PHY type 0x%x pass %d type ", phytype, pass);
862 #endif
863 if (phytype != 0xffff) {
864 phyaddr = phyno;
865 phytype |= mii_send(mk_mii_read(phyno,
866 MII_PHYSID1)) << 16;
867
868 #ifdef ET_DEBUG
869 printf("PHY @ 0x%x pass %d type ",phyno,pass);
870 switch (phytype & 0xfffffff0) {
871 case PHY_ID_LXT970:
872 printf("LXT970\n");
873 break;
874 case PHY_ID_LXT971:
875 printf("LXT971\n");
876 break;
877 case PHY_ID_82555:
878 printf("82555\n");
879 break;
880 case PHY_ID_QS6612:
881 printf("QS6612\n");
882 break;
883 case PHY_ID_AMD79C784:
884 printf("AMD79C784\n");
885 break;
886 case PHY_ID_LSI80225B:
887 printf("LSI L80225/B\n");
888 break;
889 case PHY_ID_DM9161:
890 printf("Davicom DM9161\n");
891 break;
892 case PHY_ID_KSM8995M:
893 printf("MICREL KS8995M\n");
894 break;
895 default:
896 printf("0x%08x\n", phytype);
897 break;
898 }
899 #endif
900 }
901 }
902 }
903 if (phyaddr < 0) {
904 printf("No PHY device found.\n");
905 }
906 return phyaddr;
907 }
908 #endif /* CONFIG_SYS_DISCOVER_PHY */
909
910 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
911
912 /****************************************************************************
913 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
914 * This function is a subset of eth_init
915 ****************************************************************************
916 */
917 static void __mii_init(void)
918 {
919 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
920 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
921
922 if (fec_reset(fecp) < 0)
923 printf ("FEC_RESET_DELAY timeout\n");
924
925 /* We use strictly polling mode only
926 */
927 fecp->fec_imask = 0;
928
929 /* Clear any pending interrupt
930 */
931 fecp->fec_ievent = 0xffc0;
932
933 /* Now enable the transmit and receive processing
934 */
935 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
936 }
937
938 void mii_init (void)
939 {
940 int i;
941
942 __mii_init();
943
944 /* Setup the pin configuration of the FEC(s)
945 */
946 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
947 fec_pin_init(ether_fcc_info[i].ether_index);
948 }
949
950 /*****************************************************************************
951 * Read and write a MII PHY register, routines used by MII Utilities
952 *
953 * FIXME: These routines are expected to return 0 on success, but mii_send
954 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
955 * no PHY connected...
956 * For now always return 0.
957 * FIXME: These routines only work after calling eth_init() at least once!
958 * Otherwise they hang in mii_send() !!! Sorry!
959 *****************************************************************************/
960
961 int fec8xx_miiphy_read(const char *devname, unsigned char addr,
962 unsigned char reg, unsigned short *value)
963 {
964 short rdreg; /* register working value */
965
966 #ifdef MII_DEBUG
967 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
968 #endif
969 rdreg = mii_send(mk_mii_read(addr, reg));
970
971 *value = rdreg;
972 #ifdef MII_DEBUG
973 printf ("0x%04x\n", *value);
974 #endif
975 return 0;
976 }
977
978 int fec8xx_miiphy_write(const char *devname, unsigned char addr,
979 unsigned char reg, unsigned short value)
980 {
981 #ifdef MII_DEBUG
982 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
983 #endif
984 (void)mii_send(mk_mii_write(addr, reg, value));
985
986 #ifdef MII_DEBUG
987 printf ("0x%04x\n", value);
988 #endif
989 return 0;
990 }
991 #endif
992
993 #endif
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