3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * SPDX-License-Identifier: GPL-2.0+
10 * Back ported to the 8xx platform (from the 8260 platform) by
11 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
16 #ifdef CONFIG_HARD_I2C
21 DECLARE_GLOBAL_DATA_PTR
;
23 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
24 #define TOUT_LOOP 1000000
28 #define MAX_TX_SPACE 256
29 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
31 typedef struct I2C_BD
{
32 unsigned short status
;
33 unsigned short length
;
37 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
39 #define BD_I2C_TX_CL 0x0001 /* collision error */
40 #define BD_I2C_TX_UN 0x0002 /* underflow error */
41 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
42 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
44 #define BD_I2C_RX_ERR BD_SC_OV
46 typedef void (*i2c_ecb_t
) (int, int); /* error callback function */
48 /* This structure keeps track of the bd and buffer space usage. */
49 typedef struct i2c_state
{
50 int rx_idx
; /* index to next free Rx BD */
51 int tx_idx
; /* index to next free Tx BD */
52 void *rxbd
; /* pointer to next free Rx BD */
53 void *txbd
; /* pointer to next free Tx BD */
54 int tx_space
; /* number of Tx bytes left */
55 unsigned char *tx_buf
; /* pointer to free Tx area */
56 i2c_ecb_t err_cb
; /* error callback function */
60 /* flags for i2c_send() and i2c_receive() */
61 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
62 #define I2CF_START_COND 0x02 /* tx: generate start condition */
63 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
66 #define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
67 #define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
68 #define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
69 #define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
71 /* error callback flags */
72 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
73 #define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
74 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
75 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
76 #define I2CECB_TX_CL 0x01 /* transmit collision error */
77 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
78 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
79 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
80 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
83 * Returns the best value of I2BRG to meet desired clock speed of I2C with
84 * input parameters (clock speed, filter, and predivider value).
85 * It returns computer speed value and the difference between it and desired
89 i2c_roundrate(int hz
, int speed
, int filter
, int modval
,
90 int *brgval
, int *totspeed
)
92 int moddiv
= 1 << (5 - (modval
& 3)), brgdiv
, div
;
94 debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
95 hz
, speed
, filter
, modval
);
98 brgdiv
= (hz
+ div
- 1) / div
;
100 debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv
, brgdiv
);
102 *brgval
= ((brgdiv
+ 1) / 2) - 3 - (2 * filter
);
104 if ((*brgval
< 0) || (*brgval
> 255)) {
105 debug("\t\trejected brgval=%d\n", *brgval
);
109 brgdiv
= 2 * (*brgval
+ 3 + (2 * filter
));
110 div
= moddiv
* brgdiv
;
111 *totspeed
= hz
/ div
;
113 debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval
, *totspeed
);
119 * Sets the I2C clock predivider and divider to meet required clock speed.
121 static int i2c_setrate(int hz
, int speed
)
123 immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
124 volatile i2c8xx_t
*i2c
= (i2c8xx_t
*) & immap
->im_i2c
;
127 bestspeed_diff
= speed
,
128 bestspeed_brgval
= 0,
129 bestspeed_modval
= 0,
130 bestspeed_filter
= 0,
132 filter
= 0; /* Use this fixed value */
134 for (modval
= 0; modval
< 4; modval
++) {
136 (hz
, speed
, filter
, modval
, &brgval
, &totspeed
) == 0) {
137 int diff
= speed
- totspeed
;
139 if ((diff
>= 0) && (diff
< bestspeed_diff
)) {
140 bestspeed_diff
= diff
;
141 bestspeed_modval
= modval
;
142 bestspeed_brgval
= brgval
;
143 bestspeed_filter
= filter
;
148 debug("[I2C] Best is:\n");
149 debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
158 ((bestspeed_modval
& 3) << 1) | (bestspeed_filter
<< 3);
159 i2c
->i2c_i2brg
= bestspeed_brgval
& 0xff;
161 debug("[I2C] i2mod=%08x i2brg=%08x\n",
168 void i2c_init(int speed
, int slaveaddr
)
170 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
171 volatile cpm8xx_t
*cp
= (cpm8xx_t
*)&immap
->im_cpm
;
172 volatile i2c8xx_t
*i2c
= (i2c8xx_t
*)&immap
->im_i2c
;
173 volatile iic_t
*iip
= (iic_t
*)&cp
->cp_dparam
[PROFF_IIC
];
175 volatile I2C_BD
*rxbd
, *txbd
;
178 #ifdef CONFIG_SYS_I2C_INIT_BOARD
179 /* call board specific i2c bus reset routine before accessing the */
180 /* environment, which might be in a chip on that bus. For details */
181 /* about this problem see doc/I2C_Edge_Conditions. */
185 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
186 iip
= (iic_t
*)&cp
->cp_dpmem
[iip
->iic_rpbase
];
188 /* Disable relocation */
192 #ifdef CONFIG_SYS_ALLOC_DPRAM
193 dpaddr
= iip
->iic_rbase
;
195 /* need to allocate dual port ram */
196 dpaddr
= dpram_alloc_align((NUM_RX_BDS
* sizeof(I2C_BD
)) +
197 (NUM_TX_BDS
* sizeof(I2C_BD
)) +
201 dpaddr
= CPM_I2C_BASE
;
205 * initialise data in dual port ram:
207 * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
208 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
209 * tx buffer (MAX_TX_SPACE bytes)
213 tbase
= rbase
+ NUM_RX_BDS
* sizeof(I2C_BD
);
215 /* Initialize Port B I2C pins. */
216 cp
->cp_pbpar
|= 0x00000030;
217 cp
->cp_pbdir
|= 0x00000030;
218 cp
->cp_pbodr
|= 0x00000030;
220 /* Disable interrupts */
221 i2c
->i2c_i2mod
= 0x00;
222 i2c
->i2c_i2cmr
= 0x00;
223 i2c
->i2c_i2cer
= 0xff;
224 i2c
->i2c_i2add
= slaveaddr
;
227 * Set the I2C BRG Clock division factor from desired i2c rate
228 * and current CPU rate (we assume sccr dfbgr field is 0;
229 * divide BRGCLK by 1)
231 debug("[I2C] Setting rate...\n");
232 i2c_setrate(gd
->cpu_clk
, CONFIG_SYS_I2C_SPEED
);
234 /* Set I2C controller in master mode */
235 i2c
->i2c_i2com
= 0x01;
237 /* Set SDMA bus arbitration level to 5 (SDCR) */
238 immap
->im_siu_conf
.sc_sdcr
= 0x0001;
240 /* Initialize Tx/Rx parameters */
241 iip
->iic_rbase
= rbase
;
242 iip
->iic_tbase
= tbase
;
243 rxbd
= (I2C_BD
*) ((unsigned char *) &cp
->cp_dpmem
[iip
->iic_rbase
]);
244 txbd
= (I2C_BD
*) ((unsigned char *) &cp
->cp_dpmem
[iip
->iic_tbase
]);
246 debug("[I2C] rbase = %04x\n", iip
->iic_rbase
);
247 debug("[I2C] tbase = %04x\n", iip
->iic_tbase
);
248 debug("[I2C] rxbd = %08x\n", (int)rxbd
);
249 debug("[I2C] txbd = %08x\n", (int)txbd
);
251 /* Set big endian byte order */
252 iip
->iic_tfcr
= 0x10;
253 iip
->iic_rfcr
= 0x10;
255 /* Set maximum receive size. */
256 iip
->iic_mrblr
= I2C_RXTX_LEN
;
258 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
260 * Initialize required parameters if using microcode patch.
262 iip
->iic_rbptr
= iip
->iic_rbase
;
263 iip
->iic_tbptr
= iip
->iic_tbase
;
267 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_CH_I2C
, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
269 __asm__
__volatile__("eieio");
270 } while (cp
->cp_cpcr
& CPM_CR_FLG
);
273 /* Clear events and interrupts */
274 i2c
->i2c_i2cer
= 0xff;
275 i2c
->i2c_i2cmr
= 0x00;
278 static void i2c_newio(i2c_state_t
*state
)
280 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
281 volatile cpm8xx_t
*cp
= (cpm8xx_t
*)&immap
->im_cpm
;
282 volatile iic_t
*iip
= (iic_t
*)&cp
->cp_dparam
[PROFF_IIC
];
284 debug("[I2C] i2c_newio\n");
286 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
287 iip
= (iic_t
*)&cp
->cp_dpmem
[iip
->iic_rpbase
];
291 state
->rxbd
= (void *)&cp
->cp_dpmem
[iip
->iic_rbase
];
292 state
->txbd
= (void *)&cp
->cp_dpmem
[iip
->iic_tbase
];
293 state
->tx_space
= MAX_TX_SPACE
;
294 state
->tx_buf
= (uchar
*)state
->txbd
+ NUM_TX_BDS
* sizeof(I2C_BD
);
295 state
->err_cb
= NULL
;
297 debug("[I2C] rxbd = %08x\n", (int)state
->rxbd
);
298 debug("[I2C] txbd = %08x\n", (int)state
->txbd
);
299 debug("[I2C] tx_buf = %08x\n", (int)state
->tx_buf
);
301 /* clear the buffer memory */
302 memset((char *)state
->tx_buf
, 0, MAX_TX_SPACE
);
306 i2c_send(i2c_state_t
*state
,
307 unsigned char address
,
308 unsigned char secondary_address
,
309 unsigned int flags
, unsigned short size
, unsigned char *dataout
)
311 volatile I2C_BD
*txbd
;
314 debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
315 address
, secondary_address
, flags
, size
);
317 /* trying to send message larger than BD */
318 if (size
> I2C_RXTX_LEN
)
319 return I2CERR_MSG_TOO_LONG
;
321 /* no more free bds */
322 if (state
->tx_idx
>= NUM_TX_BDS
|| state
->tx_space
< (2 + size
))
323 return I2CERR_NO_BUFFERS
;
325 txbd
= (I2C_BD
*) state
->txbd
;
326 txbd
->addr
= state
->tx_buf
;
328 debug("[I2C] txbd = %08x\n", (int)txbd
);
330 if (flags
& I2CF_START_COND
) {
331 debug("[I2C] Formatting addresses...\n");
332 if (flags
& I2CF_ENABLE_SECONDARY
) {
333 /* Length of msg + dest addr */
334 txbd
->length
= size
+ 2;
336 txbd
->addr
[0] = address
<< 1;
337 txbd
->addr
[1] = secondary_address
;
340 /* Length of msg + dest addr */
341 txbd
->length
= size
+ 1;
342 /* Write dest addr to BD */
343 txbd
->addr
[0] = address
<< 1;
347 txbd
->length
= size
; /* Length of message */
352 txbd
->status
= BD_SC_READY
;
353 if (flags
& I2CF_START_COND
)
354 txbd
->status
|= BD_I2C_TX_START
;
355 if (flags
& I2CF_STOP_COND
)
356 txbd
->status
|= BD_SC_LAST
| BD_SC_WRAP
;
358 /* Copy data to send into buffer */
359 debug("[I2C] copy data...\n");
360 for(j
= 0; j
< size
; i
++, j
++)
361 txbd
->addr
[i
] = dataout
[j
];
363 debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
370 state
->tx_buf
+= txbd
->length
;
371 state
->tx_space
-= txbd
->length
;
373 state
->txbd
= (void *) (txbd
+ 1);
379 i2c_receive(i2c_state_t
*state
,
380 unsigned char address
,
381 unsigned char secondary_address
,
383 unsigned short size_to_expect
, unsigned char *datain
)
385 volatile I2C_BD
*rxbd
, *txbd
;
387 debug("[I2C] i2c_receive %02d %02d %02d\n",
388 address
, secondary_address
, flags
);
390 /* Expected to receive too much */
391 if (size_to_expect
> I2C_RXTX_LEN
)
392 return I2CERR_MSG_TOO_LONG
;
394 /* no more free bds */
395 if (state
->tx_idx
>= NUM_TX_BDS
|| state
->rx_idx
>= NUM_RX_BDS
396 || state
->tx_space
< 2)
397 return I2CERR_NO_BUFFERS
;
399 rxbd
= (I2C_BD
*) state
->rxbd
;
400 txbd
= (I2C_BD
*) state
->txbd
;
402 debug("[I2C] rxbd = %08x\n", (int)rxbd
);
403 debug("[I2C] txbd = %08x\n", (int)txbd
);
405 txbd
->addr
= state
->tx_buf
;
407 /* set up TXBD for destination address */
408 if (flags
& I2CF_ENABLE_SECONDARY
) {
410 txbd
->addr
[0] = address
<< 1; /* Write data */
411 txbd
->addr
[1] = secondary_address
; /* Internal address */
412 txbd
->status
= BD_SC_READY
;
414 txbd
->length
= 1 + size_to_expect
;
415 txbd
->addr
[0] = (address
<< 1) | 0x01;
416 txbd
->status
= BD_SC_READY
;
417 memset(&txbd
->addr
[1], 0, txbd
->length
);
420 /* set up rxbd for reception */
421 rxbd
->status
= BD_SC_EMPTY
;
422 rxbd
->length
= size_to_expect
;
425 txbd
->status
|= BD_I2C_TX_START
;
426 if (flags
& I2CF_STOP_COND
) {
427 txbd
->status
|= BD_SC_LAST
| BD_SC_WRAP
;
428 rxbd
->status
|= BD_SC_WRAP
;
431 debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
436 debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
443 state
->tx_buf
+= txbd
->length
;
444 state
->tx_space
-= txbd
->length
;
446 state
->txbd
= (void *) (txbd
+ 1);
448 state
->rxbd
= (void *) (rxbd
+ 1);
454 static int i2c_doio(i2c_state_t
*state
)
456 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
457 volatile cpm8xx_t
*cp
= (cpm8xx_t
*)&immap
->im_cpm
;
458 volatile i2c8xx_t
*i2c
= (i2c8xx_t
*)&immap
->im_i2c
;
459 volatile iic_t
*iip
= (iic_t
*)&cp
->cp_dparam
[PROFF_IIC
];
460 volatile I2C_BD
*txbd
, *rxbd
;
463 debug("[I2C] i2c_doio\n");
465 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
466 iip
= (iic_t
*)&cp
->cp_dpmem
[iip
->iic_rpbase
];
469 if (state
->tx_idx
<= 0 && state
->rx_idx
<= 0) {
470 debug("[I2C] No I/O is queued\n");
471 return I2CERR_QUEUE_EMPTY
;
474 iip
->iic_rbptr
= iip
->iic_rbase
;
475 iip
->iic_tbptr
= iip
->iic_tbase
;
478 debug("[I2C] Enabling I2C...\n");
479 i2c
->i2c_i2mod
|= 0x01;
481 /* Begin transmission */
482 i2c
->i2c_i2com
|= 0x80;
484 /* Loop until transmit & receive completed */
486 if (state
->tx_idx
> 0) {
487 txbd
= ((I2C_BD
*)state
->txbd
) - 1;
489 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
492 while ((txbd
->status
& BD_SC_READY
) && (j
++ < TOUT_LOOP
)) {
496 __asm__
__volatile__("eieio");
500 if ((state
->rx_idx
> 0) && (j
< TOUT_LOOP
)) {
501 rxbd
= ((I2C_BD
*)state
->rxbd
) - 1;
503 debug("[I2C] Receiving...(rxbd=0x%08lx)\n",
506 while ((rxbd
->status
& BD_SC_EMPTY
) && (j
++ < TOUT_LOOP
)) {
510 __asm__
__volatile__("eieio");
515 i2c
->i2c_i2mod
&= ~0x01;
517 if (state
->err_cb
!= NULL
) {
521 * if we have an error callback function, look at the
522 * error bits in the bd status and pass them back
525 if ((n
= state
->tx_idx
) > 0) {
526 for (i
= 0; i
< n
; i
++) {
527 txbd
= ((I2C_BD
*) state
->txbd
) - (n
- i
);
528 if ((b
= txbd
->status
& BD_I2C_TX_ERR
) != 0)
529 (*state
->err_cb
) (I2CECB_TX_ERR
| b
,
534 if ((n
= state
->rx_idx
) > 0) {
535 for (i
= 0; i
< n
; i
++) {
536 rxbd
= ((I2C_BD
*) state
->rxbd
) - (n
- i
);
537 if ((b
= rxbd
->status
& BD_I2C_RX_ERR
) != 0)
538 (*state
->err_cb
) (I2CECB_RX_ERR
| b
,
544 (*state
->err_cb
) (I2CECB_TIMEOUT
, 0);
547 return (j
>= TOUT_LOOP
) ? I2CERR_TIMEOUT
: 0;
550 static int had_tx_nak
;
552 static void i2c_test_callback(int flags
, int xnum
)
554 if ((flags
& I2CECB_TX_ERR
) && (flags
& I2CECB_TX_NAK
))
558 int i2c_probe(uchar chip
)
564 i2c_init(CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
568 state
.err_cb
= i2c_test_callback
;
571 rc
= i2c_receive(&state
, chip
, 0, I2CF_START_COND
| I2CF_STOP_COND
, 1,
577 rc
= i2c_doio(&state
);
579 if ((rc
!= 0) && (rc
!= I2CERR_TIMEOUT
))
585 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
591 xaddr
[0] = (addr
>> 24) & 0xFF;
592 xaddr
[1] = (addr
>> 16) & 0xFF;
593 xaddr
[2] = (addr
>> 8) & 0xFF;
594 xaddr
[3] = addr
& 0xFF;
596 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
598 * EEPROM chips that implement "address overflow" are ones like
599 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
600 * extra bits end up in the "chip address" bit slots. This makes
601 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
603 * Note that we consider the length of the address field to still
604 * be one byte because the extra address bits are hidden in the
607 chip
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
612 rc
= i2c_send(&state
, chip
, 0, I2CF_START_COND
, alen
,
615 printf("i2c_read: i2c_send failed (%d)\n", rc
);
619 rc
= i2c_receive(&state
, chip
, 0, I2CF_STOP_COND
, len
, buffer
);
621 printf("i2c_read: i2c_receive failed (%d)\n", rc
);
625 rc
= i2c_doio(&state
);
627 printf("i2c_read: i2c_doio failed (%d)\n", rc
);
633 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
639 xaddr
[0] = (addr
>> 24) & 0xFF;
640 xaddr
[1] = (addr
>> 16) & 0xFF;
641 xaddr
[2] = (addr
>> 8) & 0xFF;
642 xaddr
[3] = addr
& 0xFF;
644 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
646 * EEPROM chips that implement "address overflow" are ones like
647 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
648 * extra bits end up in the "chip address" bit slots. This makes
649 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
651 * Note that we consider the length of the address field to still
652 * be one byte because the extra address bits are hidden in the
655 chip
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
660 rc
= i2c_send(&state
, chip
, 0, I2CF_START_COND
, alen
,
663 printf("i2c_write: first i2c_send failed (%d)\n", rc
);
667 rc
= i2c_send(&state
, 0, 0, I2CF_STOP_COND
, len
, buffer
);
669 printf("i2c_write: second i2c_send failed (%d)\n", rc
);
673 rc
= i2c_doio(&state
);
675 printf("i2c_write: i2c_doio failed (%d)\n", rc
);
681 #endif /* CONFIG_HARD_I2C */