arch/powerpc/cpu/mpc8xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*  U-Boot - Startup Code for PowerPC based Embedded Boards
  26  *
  27  *
  28  *  The processor starts at 0x00000100 and the code is executed
  29  *  from flash. The code is organized to be at an other address
  30  *  in memory, but as long we don't jump around before relocating,
  31  *  board_init lies at a quite high address and when the cpu has
  32  *  jumped there, everything is ok.
  33  *  This works because the cpu gives the FLASH (CS0) the whole
  34  *  address space at startup, and board_init lies as a echo of
  35  *  the flash somewhere up there in the memory map.
  36  *
  37  *  board_init will change CS0 to be positioned at the correct
  38  *  address and (s)dram will be positioned at address 0
  39  */
  40 #include <asm-offsets.h>
  41 #include <config.h>
  42 #include <mpc8xx.h>
  43 #include <timestamp.h>
  44 #include <version.h>
  45
  46 #define CONFIG_8xx 1            /* needed for Linux kernel header files */
  47 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  48
  49 #include <ppc_asm.tmpl>
  50 #include <ppc_defs.h>
  51
  52 #include <asm/cache.h>
  53 #include <asm/mmu.h>
  54 #include <asm/u-boot.h>
  55
  56 #ifndef  CONFIG_IDENT_STRING
  57 #define  CONFIG_IDENT_STRING ""
  58 #endif
  59
  60 /* We don't want the  MMU yet.
  61 */
  62 #undef  MSR_KERNEL
  63 #define MSR_KERNEL ( MSR_ME | MSR_RI )  /* Machine Check and Recoverable Interr. */
  64
  65 /*
  66  * Set up GOT: Global Offset Table
  67  *
  68  * Use r12 to access the GOT
  69  */
  70         START_GOT
  71         GOT_ENTRY(_GOT2_TABLE_)
  72         GOT_ENTRY(_FIXUP_TABLE_)
  73
  74         GOT_ENTRY(_start)
  75         GOT_ENTRY(_start_of_vectors)
  76         GOT_ENTRY(_end_of_vectors)
  77         GOT_ENTRY(transfer_to_handler)
  78
  79         GOT_ENTRY(__init_end)
  80         GOT_ENTRY(_end)
  81         GOT_ENTRY(__bss_start)
  82         END_GOT
  83
  84 /*
  85  * r3 - 1st arg to board_init(): IMMP pointer
  86  * r4 - 2nd arg to board_init(): boot flag
  87  */
  88         .text
  89         .long   0x27051956              /* U-Boot Magic Number                  */
  90         .globl  version_string
  91 version_string:
  92         .ascii U_BOOT_VERSION
  93         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  94         .ascii CONFIG_IDENT_STRING, "\0"
  95
  96         . = EXC_OFF_SYS_RESET
  97         .globl  _start
  98 _start:
  99         lis     r3, CONFIG_SYS_IMMR@h           /* position IMMR */
 100         mtspr   638, r3
 101
 102         /* Initialize machine status; enable machine check interrupt            */
 103         /*----------------------------------------------------------------------*/
 104         li      r3, MSR_KERNEL          /* Set ME, RI flags */
 105         mtmsr   r3
 106         mtspr   SRR1, r3                /* Make SRR1 match MSR */
 107
 108         mfspr   r3, ICR                 /* clear Interrupt Cause Register */
 109
 110         /* Initialize debug port registers                                      */
 111         /*----------------------------------------------------------------------*/
 112         xor     r0, r0, r0              /* Clear R0 */
 113         mtspr   LCTRL1, r0              /* Initialize debug port regs */
 114         mtspr   LCTRL2, r0
 115         mtspr   COUNTA, r0
 116         mtspr   COUNTB, r0
 117
 118         /* Reset the caches                                                     */
 119         /*----------------------------------------------------------------------*/
 120
 121         mfspr   r3, IC_CST              /* Clear error bits */
 122         mfspr   r3, DC_CST
 123
 124         lis     r3, IDC_UNALL@h         /* Unlock all */
 125         mtspr   IC_CST, r3
 126         mtspr   DC_CST, r3
 127
 128         lis     r3, IDC_INVALL@h        /* Invalidate all */
 129         mtspr   IC_CST, r3
 130         mtspr   DC_CST, r3
 131
 132         lis     r3, IDC_DISABLE@h       /* Disable data cache */
 133         mtspr   DC_CST, r3
 134
 135 #if !defined(CONFIG_SYS_DELAYED_ICACHE)
 136                                         /* On IP860 and PCU E,
 137                                          * we cannot enable IC yet
 138                                          */
 139         lis     r3, IDC_ENABLE@h        /* Enable instruction cache */
 140 #endif
 141         mtspr   IC_CST, r3
 142
 143         /* invalidate all tlb's                                                 */
 144         /*----------------------------------------------------------------------*/
 145
 146         tlbia
 147         isync
 148
 149         /*
 150          * Calculate absolute address in FLASH and jump there
 151          *----------------------------------------------------------------------*/
 152
 153         lis     r3, CONFIG_SYS_MONITOR_BASE@h
 154         ori     r3, r3, CONFIG_SYS_MONITOR_BASE@l
 155         addi    r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 156         mtlr    r3
 157         blr
 158
 159 in_flash:
 160
 161         /* initialize some SPRs that are hard to access from C                  */
 162         /*----------------------------------------------------------------------*/
 163
 164         lis     r3, CONFIG_SYS_IMMR@h           /* pass IMMR as arg1 to C routine */
 165         ori     r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
 166         /* Note: R0 is still 0 here */
 167         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 168         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 169
 170         /*
 171          * Disable serialized ifetch and show cycles
 172          * (i.e. set processor to normal mode).
 173          * This is also a silicon bug workaround, see errata
 174          */
 175
 176         li      r2, 0x0007
 177         mtspr   ICTRL, r2
 178
 179         /* Set up debug mode entry */
 180
 181         lis     r2, CONFIG_SYS_DER@h
 182         ori     r2, r2, CONFIG_SYS_DER@l
 183         mtspr   DER, r2
 184
 185         /* let the C-code set up the rest                                       */
 186         /*                                                                      */
 187         /* Be careful to keep code relocatable !                                */
 188         /*----------------------------------------------------------------------*/
 189
 190         GET_GOT                 /* initialize GOT access                        */
 191
 192         /* r3: IMMR */
 193         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 194
 195         bl      board_init_f    /* run 1st part of board init code (from Flash) */
 196
 197         /* NOTREACHED - board_init_f() does not return */
 198
 199
 200         .globl  _start_of_vectors
 201 _start_of_vectors:
 202
 203 /* Machine check */
 204         STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 205
 206 /* Data Storage exception.  "Never" generated on the 860. */
 207         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 208
 209 /* Instruction Storage exception.  "Never" generated on the 860. */
 210         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 211
 212 /* External Interrupt exception. */
 213         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 214
 215 /* Alignment exception. */
 216         . = 0x600
 217 Alignment:
 218         EXCEPTION_PROLOG(SRR0, SRR1)
 219         mfspr   r4,DAR
 220         stw     r4,_DAR(r21)
 221         mfspr   r5,DSISR
 222         stw     r5,_DSISR(r21)
 223         addi    r3,r1,STACK_FRAME_OVERHEAD
 224         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 225
 226 /* Program check exception */
 227         . = 0x700
 228 ProgramCheck:
 229         EXCEPTION_PROLOG(SRR0, SRR1)
 230         addi    r3,r1,STACK_FRAME_OVERHEAD
 231         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 232                 MSR_KERNEL, COPY_EE)
 233
 234         /* No FPU on MPC8xx.  This exception is not supposed to happen.
 235         */
 236         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 237
 238         /* I guess we could implement decrementer, and may have
 239          * to someday for timekeeping.
 240          */
 241         STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 242         STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 243         STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 244         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 245         STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 246
 247         STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 248         STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 249
 250         /* On the MPC8xx, this is a software emulation interrupt.  It occurs
 251          * for all unimplemented and illegal instructions.
 252          */
 253         STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
 254
 255         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 256         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 257         STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
 258         STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
 259
 260         STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 261         STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 262         STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 263         STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 264         STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 265         STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 266         STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 267
 268         STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
 269         STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
 270         STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
 271         STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
 272
 273
 274         .globl  _end_of_vectors
 275 _end_of_vectors:
 276
 277
 278         . = 0x2000
 279
 280 /*
 281  * This code finishes saving the registers to the exception frame
 282  * and jumps to the appropriate handler for the exception.
 283  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 284  */
 285         .globl  transfer_to_handler
 286 transfer_to_handler:
 287         stw     r22,_NIP(r21)
 288         lis     r22,MSR_POW@h
 289         andc    r23,r23,r22
 290         stw     r23,_MSR(r21)
 291         SAVE_GPR(7, r21)
 292         SAVE_4GPRS(8, r21)
 293         SAVE_8GPRS(12, r21)
 294         SAVE_8GPRS(24, r21)
 295         mflr    r23
 296         andi.   r24,r23,0x3f00          /* get vector offset */
 297         stw     r24,TRAP(r21)
 298         li      r22,0
 299         stw     r22,RESULT(r21)
 300         mtspr   SPRG2,r22               /* r1 is now kernel sp */
 301         lwz     r24,0(r23)              /* virtual address of handler */
 302         lwz     r23,4(r23)              /* where to go when done */
 303         mtspr   SRR0,r24
 304         mtspr   SRR1,r20
 305         mtlr    r23
 306         SYNC
 307         rfi                             /* jump to handler, enable MMU */
 308
 309 int_return:
 310         mfmsr   r28                     /* Disable interrupts */
 311         li      r4,0
 312         ori     r4,r4,MSR_EE
 313         andc    r28,r28,r4
 314         SYNC                            /* Some chip revs need this... */
 315         mtmsr   r28
 316         SYNC
 317         lwz     r2,_CTR(r1)
 318         lwz     r0,_LINK(r1)
 319         mtctr   r2
 320         mtlr    r0
 321         lwz     r2,_XER(r1)
 322         lwz     r0,_CCR(r1)
 323         mtspr   XER,r2
 324         mtcrf   0xFF,r0
 325         REST_10GPRS(3, r1)
 326         REST_10GPRS(13, r1)
 327         REST_8GPRS(23, r1)
 328         REST_GPR(31, r1)
 329         lwz     r2,_NIP(r1)             /* Restore environment */
 330         lwz     r0,_MSR(r1)
 331         mtspr   SRR0,r2
 332         mtspr   SRR1,r0
 333         lwz     r0,GPR0(r1)
 334         lwz     r2,GPR2(r1)
 335         lwz     r1,GPR1(r1)
 336         SYNC
 337         rfi
 338
 339 /* Cache functions.
 340 */
 341         .globl  icache_enable
 342 icache_enable:
 343         SYNC
 344         lis     r3, IDC_INVALL@h
 345         mtspr   IC_CST, r3
 346         lis     r3, IDC_ENABLE@h
 347         mtspr   IC_CST, r3
 348         blr
 349
 350         .globl  icache_disable
 351 icache_disable:
 352         SYNC
 353         lis     r3, IDC_DISABLE@h
 354         mtspr   IC_CST, r3
 355         blr
 356
 357         .globl  icache_status
 358 icache_status:
 359         mfspr   r3, IC_CST
 360         srwi    r3, r3, 31      /* >>31 => select bit 0 */
 361         blr
 362
 363         .globl  dcache_enable
 364 dcache_enable:
 365 #if 0
 366         SYNC
 367 #endif
 368 #if 1
 369         lis     r3, 0x0400              /* Set cache mode with MMU off */
 370         mtspr   MD_CTR, r3
 371 #endif
 372
 373         lis     r3, IDC_INVALL@h
 374         mtspr   DC_CST, r3
 375 #if 0
 376         lis     r3, DC_SFWT@h
 377         mtspr   DC_CST, r3
 378 #endif
 379         lis     r3, IDC_ENABLE@h
 380         mtspr   DC_CST, r3
 381         blr
 382
 383         .globl  dcache_disable
 384 dcache_disable:
 385         SYNC
 386         lis     r3, IDC_DISABLE@h
 387         mtspr   DC_CST, r3
 388         lis     r3, IDC_INVALL@h
 389         mtspr   DC_CST, r3
 390         blr
 391
 392         .globl  dcache_status
 393 dcache_status:
 394         mfspr   r3, DC_CST
 395         srwi    r3, r3, 31      /* >>31 => select bit 0 */
 396         blr
 397
 398         .globl  dc_read
 399 dc_read:
 400         mtspr   DC_ADR, r3
 401         mfspr   r3, DC_DAT
 402         blr
 403
 404 /*
 405  * unsigned int get_immr (unsigned int mask)
 406  *
 407  * return (mask ? (IMMR & mask) : IMMR);
 408  */
 409         .globl  get_immr
 410 get_immr:
 411         mr      r4,r3           /* save mask */
 412         mfspr   r3, IMMR        /* IMMR */
 413         cmpwi   0,r4,0          /* mask != 0 ? */
 414         beq     4f
 415         and     r3,r3,r4        /* IMMR & mask */
 416 4:
 417         blr
 418
 419         .globl get_pvr
 420 get_pvr:
 421         mfspr   r3, PVR
 422         blr
 423
 424
 425         .globl wr_ic_cst
 426 wr_ic_cst:
 427         mtspr   IC_CST, r3
 428         blr
 429
 430         .globl rd_ic_cst
 431 rd_ic_cst:
 432         mfspr   r3, IC_CST
 433         blr
 434
 435         .globl wr_ic_adr
 436 wr_ic_adr:
 437         mtspr   IC_ADR, r3
 438         blr
 439
 440
 441         .globl wr_dc_cst
 442 wr_dc_cst:
 443         mtspr   DC_CST, r3
 444         blr
 445
 446         .globl rd_dc_cst
 447 rd_dc_cst:
 448         mfspr   r3, DC_CST
 449         blr
 450
 451         .globl wr_dc_adr
 452 wr_dc_adr:
 453         mtspr   DC_ADR, r3
 454         blr
 455
 456 /*------------------------------------------------------------------------------*/
 457
 458 /*
 459  * void relocate_code (addr_sp, gd, addr_moni)
 460  *
 461  * This "function" does not return, instead it continues in RAM
 462  * after relocating the monitor code.
 463  *
 464  * r3 = dest
 465  * r4 = src
 466  * r5 = length in bytes
 467  * r6 = cachelinesize
 468  */
 469         .globl  relocate_code
 470 relocate_code:
 471         mr      r1,  r3         /* Set new stack pointer                */
 472         mr      r9,  r4         /* Save copy of Global Data pointer     */
 473         mr      r10, r5         /* Save copy of Destination Address     */
 474
 475         GET_GOT
 476         mr      r3,  r5                         /* Destination Address  */
 477         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
 478         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 479         lwz     r5, GOT(__init_end)
 480         sub     r5, r5, r4
 481         li      r6, CONFIG_SYS_CACHELINE_SIZE           /* Cache Line Size      */
 482
 483         /*
 484          * Fix GOT pointer:
 485          *
 486          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 487          *
 488          * Offset:
 489          */
 490         sub     r15, r10, r4
 491
 492         /* First our own GOT */
 493         add     r12, r12, r15
 494         /* then the one used by the C code */
 495         add     r30, r30, r15
 496
 497         /*
 498          * Now relocate code
 499          */
 500
 501         cmplw   cr1,r3,r4
 502         addi    r0,r5,3
 503         srwi.   r0,r0,2
 504         beq     cr1,4f          /* In place copy is not necessary       */
 505         beq     7f              /* Protect against 0 count              */
 506         mtctr   r0
 507         bge     cr1,2f
 508
 509         la      r8,-4(r4)
 510         la      r7,-4(r3)
 511 1:      lwzu    r0,4(r8)
 512         stwu    r0,4(r7)
 513         bdnz    1b
 514         b       4f
 515
 516 2:      slwi    r0,r0,2
 517         add     r8,r4,r0
 518         add     r7,r3,r0
 519 3:      lwzu    r0,-4(r8)
 520         stwu    r0,-4(r7)
 521         bdnz    3b
 522
 523 /*
 524  * Now flush the cache: note that we must start from a cache aligned
 525  * address. Otherwise we might miss one cache line.
 526  */
 527 4:      cmpwi   r6,0
 528         add     r5,r3,r5
 529         beq     7f              /* Always flush prefetch queue in any case */
 530         subi    r0,r6,1
 531         andc    r3,r3,r0
 532         mr      r4,r3
 533 5:      dcbst   0,r4
 534         add     r4,r4,r6
 535         cmplw   r4,r5
 536         blt     5b
 537         sync                    /* Wait for all dcbst to complete on bus */
 538         mr      r4,r3
 539 6:      icbi    0,r4
 540         add     r4,r4,r6
 541         cmplw   r4,r5
 542         blt     6b
 543 7:      sync                    /* Wait for all icbi to complete on bus */
 544         isync
 545
 546 /*
 547  * We are done. Do not return, instead branch to second part of board
 548  * initialization, now running from RAM.
 549  */
 550
 551         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 552         mtlr    r0
 553         blr
 554
 555 in_ram:
 556
 557         /*
 558          * Relocation Function, r12 point to got2+0x8000
 559          *
 560          * Adjust got2 pointers, no need to check for 0, this code
 561          * already puts a few entries in the table.
 562          */
 563         li      r0,__got2_entries@sectoff@l
 564         la      r3,GOT(_GOT2_TABLE_)
 565         lwz     r11,GOT(_GOT2_TABLE_)
 566         mtctr   r0
 567         sub     r11,r3,r11
 568         addi    r3,r3,-4
 569 1:      lwzu    r0,4(r3)
 570         cmpwi   r0,0
 571         beq-    2f
 572         add     r0,r0,r11
 573         stw     r0,0(r3)
 574 2:      bdnz    1b
 575
 576         /*
 577          * Now adjust the fixups and the pointers to the fixups
 578          * in case we need to move ourselves again.
 579          */
 580         li      r0,__fixup_entries@sectoff@l
 581         lwz     r3,GOT(_FIXUP_TABLE_)
 582         cmpwi   r0,0
 583         mtctr   r0
 584         addi    r3,r3,-4
 585         beq     4f
 586 3:      lwzu    r4,4(r3)
 587         lwzux   r0,r4,r11
 588         cmpwi   r0,0
 589         add     r0,r0,r11
 590         stw     r4,0(r3)
 591         beq-    5f
 592         stw     r0,0(r4)
 593 5:      bdnz    3b
 594 4:
 595 clear_bss:
 596         /*
 597          * Now clear BSS segment
 598          */
 599         lwz     r3,GOT(__bss_start)
 600         lwz     r4,GOT(_end)
 601
 602         cmplw   0, r3, r4
 603         beq     6f
 604
 605         li      r0, 0
 606 5:
 607         stw     r0, 0(r3)
 608         addi    r3, r3, 4
 609         cmplw   0, r3, r4
 610         bne     5b
 611 6:
 612
 613         mr      r3, r9          /* Global Data pointer          */
 614         mr      r4, r10         /* Destination Address          */
 615         bl      board_init_r
 616
 617         /*
 618          * Copy exception vector code to low memory
 619          *
 620          * r3: dest_addr
 621          * r7: source address, r8: end address, r9: target address
 622          */
 623         .globl  trap_init
 624 trap_init:
 625         mflr    r4                      /* save link register           */
 626         GET_GOT
 627         lwz     r7, GOT(_start)
 628         lwz     r8, GOT(_end_of_vectors)
 629
 630         li      r9, 0x100               /* reset vector always at 0x100 */
 631
 632         cmplw   0, r7, r8
 633         bgelr                           /* return if r7>=r8 - just in case */
 634 1:
 635         lwz     r0, 0(r7)
 636         stw     r0, 0(r9)
 637         addi    r7, r7, 4
 638         addi    r9, r9, 4
 639         cmplw   0, r7, r8
 640         bne     1b
 641
 642         /*
 643          * relocate `hdlr' and `int_return' entries
 644          */
 645         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 646         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
 647 2:
 648         bl      trap_reloc
 649         addi    r7, r7, 0x100           /* next exception vector        */
 650         cmplw   0, r7, r8
 651         blt     2b
 652
 653         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 654         bl      trap_reloc
 655
 656         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 657         bl      trap_reloc
 658
 659         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 660         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
 661 3:
 662         bl      trap_reloc
 663         addi    r7, r7, 0x100           /* next exception vector        */
 664         cmplw   0, r7, r8
 665         blt     3b
 666
 667         li      r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 668         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 669 4:
 670         bl      trap_reloc
 671         addi    r7, r7, 0x100           /* next exception vector        */
 672         cmplw   0, r7, r8
 673         blt     4b
 674
 675         mtlr    r4                      /* restore link register        */
 676         blr