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[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c
1 /*
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 */
9
10 /*
11 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12 * Based on code from spd_sdram.c
13 * Author: James Yang [at freescale.com]
14 */
15
16 #include <common.h>
17 #include <asm/fsl_ddr_sdram.h>
18
19 #include "ddr.h"
20
21 #ifdef CONFIG_MPC83xx
22 #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
23 #elif defined(CONFIG_MPC85xx)
24 #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
25 #elif defined(CONFIG_MPC86xx)
26 #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
27 #else
28 #error "Undefined _DDR_ADDR"
29 #endif
30
31 u32 fsl_ddr_get_version(void)
32 {
33 ccsr_ddr_t *ddr;
34 u32 ver_major_minor_errata;
35
36 ddr = (void *)_DDR_ADDR;
37 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
38 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
39
40 return ver_major_minor_errata;
41 }
42
43 unsigned int picos_to_mclk(unsigned int picos);
44
45 /*
46 * Determine Rtt value.
47 *
48 * This should likely be either board or controller specific.
49 *
50 * Rtt(nominal) - DDR2:
51 * 0 = Rtt disabled
52 * 1 = 75 ohm
53 * 2 = 150 ohm
54 * 3 = 50 ohm
55 * Rtt(nominal) - DDR3:
56 * 0 = Rtt disabled
57 * 1 = 60 ohm
58 * 2 = 120 ohm
59 * 3 = 40 ohm
60 * 4 = 20 ohm
61 * 5 = 30 ohm
62 *
63 * FIXME: Apparently 8641 needs a value of 2
64 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
65 *
66 * FIXME: There was some effort down this line earlier:
67 *
68 * unsigned int i;
69 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
70 * if (popts->dimmslot[i].num_valid_cs
71 * && (popts->cs_local_opts[2*i].odt_rd_cfg
72 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
73 * rtt = 2;
74 * break;
75 * }
76 * }
77 */
78 static inline int fsl_ddr_get_rtt(void)
79 {
80 int rtt;
81
82 #if defined(CONFIG_FSL_DDR1)
83 rtt = 0;
84 #elif defined(CONFIG_FSL_DDR2)
85 rtt = 3;
86 #else
87 rtt = 0;
88 #endif
89
90 return rtt;
91 }
92
93 /*
94 * compute the CAS write latency according to DDR3 spec
95 * CWL = 5 if tCK >= 2.5ns
96 * 6 if 2.5ns > tCK >= 1.875ns
97 * 7 if 1.875ns > tCK >= 1.5ns
98 * 8 if 1.5ns > tCK >= 1.25ns
99 * 9 if 1.25ns > tCK >= 1.07ns
100 * 10 if 1.07ns > tCK >= 0.935ns
101 * 11 if 0.935ns > tCK >= 0.833ns
102 * 12 if 0.833ns > tCK >= 0.75ns
103 */
104 static inline unsigned int compute_cas_write_latency(void)
105 {
106 unsigned int cwl;
107 const unsigned int mclk_ps = get_memory_clk_period_ps();
108
109 if (mclk_ps >= 2500)
110 cwl = 5;
111 else if (mclk_ps >= 1875)
112 cwl = 6;
113 else if (mclk_ps >= 1500)
114 cwl = 7;
115 else if (mclk_ps >= 1250)
116 cwl = 8;
117 else if (mclk_ps >= 1070)
118 cwl = 9;
119 else if (mclk_ps >= 935)
120 cwl = 10;
121 else if (mclk_ps >= 833)
122 cwl = 11;
123 else if (mclk_ps >= 750)
124 cwl = 12;
125 else {
126 cwl = 12;
127 printf("Warning: CWL is out of range\n");
128 }
129 return cwl;
130 }
131
132 /* Chip Select Configuration (CSn_CONFIG) */
133 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
134 const memctl_options_t *popts,
135 const dimm_params_t *dimm_params)
136 {
137 unsigned int cs_n_en = 0; /* Chip Select enable */
138 unsigned int intlv_en = 0; /* Memory controller interleave enable */
139 unsigned int intlv_ctl = 0; /* Interleaving control */
140 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
141 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
142 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
143 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
144 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
145 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
146 int go_config = 0;
147
148 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
149 switch (i) {
150 case 0:
151 if (dimm_params[dimm_number].n_ranks > 0) {
152 go_config = 1;
153 /* These fields only available in CS0_CONFIG */
154 intlv_en = popts->memctl_interleaving;
155 intlv_ctl = popts->memctl_interleaving_mode;
156 }
157 break;
158 case 1:
159 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
160 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
161 go_config = 1;
162 break;
163 case 2:
164 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
165 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
166 go_config = 1;
167 break;
168 case 3:
169 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
170 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
171 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
172 go_config = 1;
173 break;
174 default:
175 break;
176 }
177 if (go_config) {
178 unsigned int n_banks_per_sdram_device;
179 cs_n_en = 1;
180 ap_n_en = popts->cs_local_opts[i].auto_precharge;
181 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
182 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
183 n_banks_per_sdram_device
184 = dimm_params[dimm_number].n_banks_per_sdram_device;
185 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
186 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
187 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
188 }
189 ddr->cs[i].config = (0
190 | ((cs_n_en & 0x1) << 31)
191 | ((intlv_en & 0x3) << 29)
192 | ((intlv_ctl & 0xf) << 24)
193 | ((ap_n_en & 0x1) << 23)
194
195 /* XXX: some implementation only have 1 bit starting at left */
196 | ((odt_rd_cfg & 0x7) << 20)
197
198 /* XXX: Some implementation only have 1 bit starting at left */
199 | ((odt_wr_cfg & 0x7) << 16)
200
201 | ((ba_bits_cs_n & 0x3) << 14)
202 | ((row_bits_cs_n & 0x7) << 8)
203 | ((col_bits_cs_n & 0x7) << 0)
204 );
205 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
206 }
207
208 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
209 /* FIXME: 8572 */
210 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
211 {
212 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
213
214 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
215 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
216 }
217
218 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
219
220 #if !defined(CONFIG_FSL_DDR1)
221 /*
222 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
223 *
224 * Avoid writing for DDR I. The new PQ38 DDR controller
225 * dreams up non-zero default values to be backwards compatible.
226 */
227 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
228 const memctl_options_t *popts)
229 {
230 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
231 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
232 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
233 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
234 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
235
236 /* Active powerdown exit timing (tXARD and tXARDS). */
237 unsigned char act_pd_exit_mclk;
238 /* Precharge powerdown exit timing (tXP). */
239 unsigned char pre_pd_exit_mclk;
240 /* ODT powerdown exit timing (tAXPD). */
241 unsigned char taxpd_mclk;
242 /* Mode register set cycle time (tMRD). */
243 unsigned char tmrd_mclk;
244
245 #ifdef CONFIG_FSL_DDR3
246 /*
247 * (tXARD and tXARDS). Empirical?
248 * The DDR3 spec has not tXARD,
249 * we use the tXP instead of it.
250 * tXP=max(3nCK, 7.5ns) for DDR3.
251 * spec has not the tAXPD, we use
252 * tAXPD=1, need design to confirm.
253 */
254 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
255 unsigned int data_rate = get_ddr_freq(0);
256 tmrd_mclk = 4;
257 /* set the turnaround time */
258 trwt_mclk = 1;
259 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
260 twrt_mclk = 1;
261
262 if (popts->dynamic_power == 0) { /* powerdown is not used */
263 act_pd_exit_mclk = 1;
264 pre_pd_exit_mclk = 1;
265 taxpd_mclk = 1;
266 } else {
267 /* act_pd_exit_mclk = tXARD, see above */
268 act_pd_exit_mclk = picos_to_mclk(tXP);
269 /* Mode register MR0[A12] is '1' - fast exit */
270 pre_pd_exit_mclk = act_pd_exit_mclk;
271 taxpd_mclk = 1;
272 }
273 #else /* CONFIG_FSL_DDR2 */
274 /*
275 * (tXARD and tXARDS). Empirical?
276 * tXARD = 2 for DDR2
277 * tXP=2
278 * tAXPD=8
279 */
280 act_pd_exit_mclk = 2;
281 pre_pd_exit_mclk = 2;
282 taxpd_mclk = 8;
283 tmrd_mclk = 2;
284 #endif
285
286 if (popts->trwt_override)
287 trwt_mclk = popts->trwt;
288
289 ddr->timing_cfg_0 = (0
290 | ((trwt_mclk & 0x3) << 30) /* RWT */
291 | ((twrt_mclk & 0x3) << 28) /* WRT */
292 | ((trrt_mclk & 0x3) << 26) /* RRT */
293 | ((twwt_mclk & 0x3) << 24) /* WWT */
294 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
295 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
296 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
297 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
298 );
299 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
300 }
301 #endif /* defined(CONFIG_FSL_DDR2) */
302
303 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
304 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
305 const common_timing_params_t *common_dimm,
306 unsigned int cas_latency)
307 {
308 /* Extended Activate to precharge interval (tRAS) */
309 unsigned int ext_acttopre = 0;
310 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
311 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
312 unsigned int cntl_adj = 0; /* Control Adjust */
313
314 /* If the tRAS > 19 MCLK, we use the ext mode */
315 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
316 ext_acttopre = 1;
317
318 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
319
320 /* If the CAS latency more than 8, use the ext mode */
321 if (cas_latency > 8)
322 ext_caslat = 1;
323
324 ddr->timing_cfg_3 = (0
325 | ((ext_acttopre & 0x1) << 24)
326 | ((ext_refrec & 0xF) << 16)
327 | ((ext_caslat & 0x1) << 12)
328 | ((cntl_adj & 0x7) << 0)
329 );
330 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
331 }
332
333 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
334 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
335 const memctl_options_t *popts,
336 const common_timing_params_t *common_dimm,
337 unsigned int cas_latency)
338 {
339 /* Precharge-to-activate interval (tRP) */
340 unsigned char pretoact_mclk;
341 /* Activate to precharge interval (tRAS) */
342 unsigned char acttopre_mclk;
343 /* Activate to read/write interval (tRCD) */
344 unsigned char acttorw_mclk;
345 /* CASLAT */
346 unsigned char caslat_ctrl;
347 /* Refresh recovery time (tRFC) ; trfc_low */
348 unsigned char refrec_ctrl;
349 /* Last data to precharge minimum interval (tWR) */
350 unsigned char wrrec_mclk;
351 /* Activate-to-activate interval (tRRD) */
352 unsigned char acttoact_mclk;
353 /* Last write data pair to read command issue interval (tWTR) */
354 unsigned char wrtord_mclk;
355 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
356 static const u8 wrrec_table[] = {
357 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
358
359 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
360 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
361 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
362
363 /*
364 * Translate CAS Latency to a DDR controller field value:
365 *
366 * CAS Lat DDR I DDR II Ctrl
367 * Clocks SPD Bit SPD Bit Value
368 * ------- ------- ------- -----
369 * 1.0 0 0001
370 * 1.5 1 0010
371 * 2.0 2 2 0011
372 * 2.5 3 0100
373 * 3.0 4 3 0101
374 * 3.5 5 0110
375 * 4.0 4 0111
376 * 4.5 1000
377 * 5.0 5 1001
378 */
379 #if defined(CONFIG_FSL_DDR1)
380 caslat_ctrl = (cas_latency + 1) & 0x07;
381 #elif defined(CONFIG_FSL_DDR2)
382 caslat_ctrl = 2 * cas_latency - 1;
383 #else
384 /*
385 * if the CAS latency more than 8 cycle,
386 * we need set extend bit for it at
387 * TIMING_CFG_3[EXT_CASLAT]
388 */
389 if (cas_latency > 8)
390 cas_latency -= 8;
391 caslat_ctrl = 2 * cas_latency - 1;
392 #endif
393
394 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
395 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
396
397 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
398 if (popts->OTF_burst_chop_en)
399 wrrec_mclk += 2;
400
401 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
402 /*
403 * JEDEC has min requirement for tRRD
404 */
405 #if defined(CONFIG_FSL_DDR3)
406 if (acttoact_mclk < 4)
407 acttoact_mclk = 4;
408 #endif
409 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
410 /*
411 * JEDEC has some min requirements for tWTR
412 */
413 #if defined(CONFIG_FSL_DDR2)
414 if (wrtord_mclk < 2)
415 wrtord_mclk = 2;
416 #elif defined(CONFIG_FSL_DDR3)
417 if (wrtord_mclk < 4)
418 wrtord_mclk = 4;
419 #endif
420 if (popts->OTF_burst_chop_en)
421 wrtord_mclk += 2;
422
423 ddr->timing_cfg_1 = (0
424 | ((pretoact_mclk & 0x0F) << 28)
425 | ((acttopre_mclk & 0x0F) << 24)
426 | ((acttorw_mclk & 0xF) << 20)
427 | ((caslat_ctrl & 0xF) << 16)
428 | ((refrec_ctrl & 0xF) << 12)
429 | ((wrrec_mclk & 0x0F) << 8)
430 | ((acttoact_mclk & 0x07) << 4)
431 | ((wrtord_mclk & 0x07) << 0)
432 );
433 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
434 }
435
436 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
437 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
438 const memctl_options_t *popts,
439 const common_timing_params_t *common_dimm,
440 unsigned int cas_latency,
441 unsigned int additive_latency)
442 {
443 /* Additive latency */
444 unsigned char add_lat_mclk;
445 /* CAS-to-preamble override */
446 unsigned short cpo;
447 /* Write latency */
448 unsigned char wr_lat;
449 /* Read to precharge (tRTP) */
450 unsigned char rd_to_pre;
451 /* Write command to write data strobe timing adjustment */
452 unsigned char wr_data_delay;
453 /* Minimum CKE pulse width (tCKE) */
454 unsigned char cke_pls;
455 /* Window for four activates (tFAW) */
456 unsigned short four_act;
457
458 /* FIXME add check that this must be less than acttorw_mclk */
459 add_lat_mclk = additive_latency;
460 cpo = popts->cpo_override;
461
462 #if defined(CONFIG_FSL_DDR1)
463 /*
464 * This is a lie. It should really be 1, but if it is
465 * set to 1, bits overlap into the old controller's
466 * otherwise unused ACSM field. If we leave it 0, then
467 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
468 */
469 wr_lat = 0;
470 #elif defined(CONFIG_FSL_DDR2)
471 wr_lat = cas_latency - 1;
472 #else
473 wr_lat = compute_cas_write_latency();
474 #endif
475
476 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
477 /*
478 * JEDEC has some min requirements for tRTP
479 */
480 #if defined(CONFIG_FSL_DDR2)
481 if (rd_to_pre < 2)
482 rd_to_pre = 2;
483 #elif defined(CONFIG_FSL_DDR3)
484 if (rd_to_pre < 4)
485 rd_to_pre = 4;
486 #endif
487 if (additive_latency)
488 rd_to_pre += additive_latency;
489 if (popts->OTF_burst_chop_en)
490 rd_to_pre += 2; /* according to UM */
491
492 wr_data_delay = popts->write_data_delay;
493 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
494 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
495
496 ddr->timing_cfg_2 = (0
497 | ((add_lat_mclk & 0xf) << 28)
498 | ((cpo & 0x1f) << 23)
499 | ((wr_lat & 0xf) << 19)
500 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
501 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
502 | ((cke_pls & 0x7) << 6)
503 | ((four_act & 0x3f) << 0)
504 );
505 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
506 }
507
508 /* DDR SDRAM Register Control Word */
509 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
510 const memctl_options_t *popts,
511 const common_timing_params_t *common_dimm)
512 {
513 if (common_dimm->all_DIMMs_registered
514 && !common_dimm->all_DIMMs_unbuffered) {
515 if (popts->rcw_override) {
516 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
517 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
518 } else {
519 ddr->ddr_sdram_rcw_1 =
520 common_dimm->rcw[0] << 28 | \
521 common_dimm->rcw[1] << 24 | \
522 common_dimm->rcw[2] << 20 | \
523 common_dimm->rcw[3] << 16 | \
524 common_dimm->rcw[4] << 12 | \
525 common_dimm->rcw[5] << 8 | \
526 common_dimm->rcw[6] << 4 | \
527 common_dimm->rcw[7];
528 ddr->ddr_sdram_rcw_2 =
529 common_dimm->rcw[8] << 28 | \
530 common_dimm->rcw[9] << 24 | \
531 common_dimm->rcw[10] << 20 | \
532 common_dimm->rcw[11] << 16 | \
533 common_dimm->rcw[12] << 12 | \
534 common_dimm->rcw[13] << 8 | \
535 common_dimm->rcw[14] << 4 | \
536 common_dimm->rcw[15];
537 }
538 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
539 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
540 }
541 }
542
543 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
544 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
545 const memctl_options_t *popts,
546 const common_timing_params_t *common_dimm)
547 {
548 unsigned int mem_en; /* DDR SDRAM interface logic enable */
549 unsigned int sren; /* Self refresh enable (during sleep) */
550 unsigned int ecc_en; /* ECC enable. */
551 unsigned int rd_en; /* Registered DIMM enable */
552 unsigned int sdram_type; /* Type of SDRAM */
553 unsigned int dyn_pwr; /* Dynamic power management mode */
554 unsigned int dbw; /* DRAM dta bus width */
555 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
556 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
557 unsigned int threeT_en; /* Enable 3T timing */
558 unsigned int twoT_en; /* Enable 2T timing */
559 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
560 unsigned int x32_en = 0; /* x32 enable */
561 unsigned int pchb8 = 0; /* precharge bit 8 enable */
562 unsigned int hse; /* Global half strength override */
563 unsigned int mem_halt = 0; /* memory controller halt */
564 unsigned int bi = 0; /* Bypass initialization */
565
566 mem_en = 1;
567 sren = popts->self_refresh_in_sleep;
568 if (common_dimm->all_DIMMs_ECC_capable) {
569 /* Allow setting of ECC only if all DIMMs are ECC. */
570 ecc_en = popts->ECC_mode;
571 } else {
572 ecc_en = 0;
573 }
574
575 if (common_dimm->all_DIMMs_registered
576 && !common_dimm->all_DIMMs_unbuffered) {
577 rd_en = 1;
578 twoT_en = 0;
579 } else {
580 rd_en = 0;
581 twoT_en = popts->twoT_en;
582 }
583
584 sdram_type = CONFIG_FSL_SDRAM_TYPE;
585
586 dyn_pwr = popts->dynamic_power;
587 dbw = popts->data_bus_width;
588 /* 8-beat burst enable DDR-III case
589 * we must clear it when use the on-the-fly mode,
590 * must set it when use the 32-bits bus mode.
591 */
592 if (sdram_type == SDRAM_TYPE_DDR3) {
593 if (popts->burst_length == DDR_BL8)
594 eight_be = 1;
595 if (popts->burst_length == DDR_OTF)
596 eight_be = 0;
597 if (dbw == 0x1)
598 eight_be = 1;
599 }
600
601 threeT_en = popts->threeT_en;
602 ba_intlv_ctl = popts->ba_intlv_ctl;
603 hse = popts->half_strength_driver_enable;
604
605 ddr->ddr_sdram_cfg = (0
606 | ((mem_en & 0x1) << 31)
607 | ((sren & 0x1) << 30)
608 | ((ecc_en & 0x1) << 29)
609 | ((rd_en & 0x1) << 28)
610 | ((sdram_type & 0x7) << 24)
611 | ((dyn_pwr & 0x1) << 21)
612 | ((dbw & 0x3) << 19)
613 | ((eight_be & 0x1) << 18)
614 | ((ncap & 0x1) << 17)
615 | ((threeT_en & 0x1) << 16)
616 | ((twoT_en & 0x1) << 15)
617 | ((ba_intlv_ctl & 0x7F) << 8)
618 | ((x32_en & 0x1) << 5)
619 | ((pchb8 & 0x1) << 4)
620 | ((hse & 0x1) << 3)
621 | ((mem_halt & 0x1) << 1)
622 | ((bi & 0x1) << 0)
623 );
624 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
625 }
626
627 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
628 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
629 const memctl_options_t *popts,
630 const unsigned int unq_mrs_en)
631 {
632 unsigned int frc_sr = 0; /* Force self refresh */
633 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
634 unsigned int dll_rst_dis; /* DLL reset disable */
635 unsigned int dqs_cfg; /* DQS configuration */
636 unsigned int odt_cfg = 0; /* ODT configuration */
637 unsigned int num_pr; /* Number of posted refreshes */
638 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
639 unsigned int ap_en; /* Address Parity Enable */
640 unsigned int d_init; /* DRAM data initialization */
641 unsigned int rcw_en = 0; /* Register Control Word Enable */
642 unsigned int md_en = 0; /* Mirrored DIMM Enable */
643 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
644 int i;
645
646 dll_rst_dis = 1; /* Make this configurable */
647 dqs_cfg = popts->DQS_config;
648 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
649 if (popts->cs_local_opts[i].odt_rd_cfg
650 || popts->cs_local_opts[i].odt_wr_cfg) {
651 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
652 break;
653 }
654 }
655
656 num_pr = 1; /* Make this configurable */
657
658 /*
659 * 8572 manual says
660 * {TIMING_CFG_1[PRETOACT]
661 * + [DDR_SDRAM_CFG_2[NUM_PR]
662 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
663 * << DDR_SDRAM_INTERVAL[REFINT]
664 */
665 #if defined(CONFIG_FSL_DDR3)
666 obc_cfg = popts->OTF_burst_chop_en;
667 #else
668 obc_cfg = 0;
669 #endif
670
671 if (popts->registered_dimm_en) {
672 rcw_en = 1;
673 ap_en = popts->ap_en;
674 } else {
675 ap_en = 0;
676 }
677
678 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
679 /* Use the DDR controller to auto initialize memory. */
680 d_init = popts->ECC_init_using_memctl;
681 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
682 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
683 #else
684 /* Memory will be initialized via DMA, or not at all. */
685 d_init = 0;
686 #endif
687
688 #if defined(CONFIG_FSL_DDR3)
689 md_en = popts->mirrored_dimm;
690 #endif
691 qd_en = popts->quad_rank_present ? 1 : 0;
692 ddr->ddr_sdram_cfg_2 = (0
693 | ((frc_sr & 0x1) << 31)
694 | ((sr_ie & 0x1) << 30)
695 | ((dll_rst_dis & 0x1) << 29)
696 | ((dqs_cfg & 0x3) << 26)
697 | ((odt_cfg & 0x3) << 21)
698 | ((num_pr & 0xf) << 12)
699 | (qd_en << 9)
700 | (unq_mrs_en << 8)
701 | ((obc_cfg & 0x1) << 6)
702 | ((ap_en & 0x1) << 5)
703 | ((d_init & 0x1) << 4)
704 | ((rcw_en & 0x1) << 2)
705 | ((md_en & 0x1) << 0)
706 );
707 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
708 }
709
710 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
711 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
712 const memctl_options_t *popts,
713 const unsigned int unq_mrs_en)
714 {
715 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
716 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
717
718 #if defined(CONFIG_FSL_DDR3)
719 int i;
720 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
721 unsigned int srt = 0; /* self-refresh temerature, normal range */
722 unsigned int asr = 0; /* auto self-refresh disable */
723 unsigned int cwl = compute_cas_write_latency() - 5;
724 unsigned int pasr = 0; /* partial array self refresh disable */
725
726 if (popts->rtt_override)
727 rtt_wr = popts->rtt_wr_override_value;
728 else
729 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
730 esdmode2 = (0
731 | ((rtt_wr & 0x3) << 9)
732 | ((srt & 0x1) << 7)
733 | ((asr & 0x1) << 6)
734 | ((cwl & 0x7) << 3)
735 | ((pasr & 0x7) << 0));
736 #endif
737 ddr->ddr_sdram_mode_2 = (0
738 | ((esdmode2 & 0xFFFF) << 16)
739 | ((esdmode3 & 0xFFFF) << 0)
740 );
741 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
742
743 #ifdef CONFIG_FSL_DDR3
744 if (unq_mrs_en) { /* unique mode registers are supported */
745 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
746 if (popts->rtt_override)
747 rtt_wr = popts->rtt_wr_override_value;
748 else
749 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
750
751 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
752 esdmode2 |= (rtt_wr & 0x3) << 9;
753 switch (i) {
754 case 1:
755 ddr->ddr_sdram_mode_4 = (0
756 | ((esdmode2 & 0xFFFF) << 16)
757 | ((esdmode3 & 0xFFFF) << 0)
758 );
759 break;
760 case 2:
761 ddr->ddr_sdram_mode_6 = (0
762 | ((esdmode2 & 0xFFFF) << 16)
763 | ((esdmode3 & 0xFFFF) << 0)
764 );
765 break;
766 case 3:
767 ddr->ddr_sdram_mode_8 = (0
768 | ((esdmode2 & 0xFFFF) << 16)
769 | ((esdmode3 & 0xFFFF) << 0)
770 );
771 break;
772 }
773 }
774 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
775 ddr->ddr_sdram_mode_4);
776 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
777 ddr->ddr_sdram_mode_6);
778 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
779 ddr->ddr_sdram_mode_8);
780 }
781 #endif
782 }
783
784 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
785 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
786 const memctl_options_t *popts,
787 const common_timing_params_t *common_dimm)
788 {
789 unsigned int refint; /* Refresh interval */
790 unsigned int bstopre; /* Precharge interval */
791
792 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
793
794 bstopre = popts->bstopre;
795
796 /* refint field used 0x3FFF in earlier controllers */
797 ddr->ddr_sdram_interval = (0
798 | ((refint & 0xFFFF) << 16)
799 | ((bstopre & 0x3FFF) << 0)
800 );
801 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
802 }
803
804 #if defined(CONFIG_FSL_DDR3)
805 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
806 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
807 const memctl_options_t *popts,
808 const common_timing_params_t *common_dimm,
809 unsigned int cas_latency,
810 unsigned int additive_latency,
811 const unsigned int unq_mrs_en)
812 {
813 unsigned short esdmode; /* Extended SDRAM mode */
814 unsigned short sdmode; /* SDRAM mode */
815
816 /* Mode Register - MR1 */
817 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
818 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
819 unsigned int rtt;
820 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
821 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
822 unsigned int dic = 0; /* Output driver impedance, 40ohm */
823 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
824 1=Disable (Test/Debug) */
825
826 /* Mode Register - MR0 */
827 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
828 unsigned int wr = 0; /* Write Recovery */
829 unsigned int dll_rst; /* DLL Reset */
830 unsigned int mode; /* Normal=0 or Test=1 */
831 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
832 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
833 unsigned int bt;
834 unsigned int bl; /* BL: Burst Length */
835
836 unsigned int wr_mclk;
837 /*
838 * DDR_SDRAM_MODE doesn't support 9,11,13,15
839 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
840 * for this table
841 */
842 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
843
844 const unsigned int mclk_ps = get_memory_clk_period_ps();
845 int i;
846
847 if (popts->rtt_override)
848 rtt = popts->rtt_override_value;
849 else
850 rtt = popts->cs_local_opts[0].odt_rtt_norm;
851
852 if (additive_latency == (cas_latency - 1))
853 al = 1;
854 if (additive_latency == (cas_latency - 2))
855 al = 2;
856
857 if (popts->quad_rank_present)
858 dic = 1; /* output driver impedance 240/7 ohm */
859
860 /*
861 * The esdmode value will also be used for writing
862 * MR1 during write leveling for DDR3, although the
863 * bits specifically related to the write leveling
864 * scheme will be handled automatically by the DDR
865 * controller. so we set the wrlvl_en = 0 here.
866 */
867 esdmode = (0
868 | ((qoff & 0x1) << 12)
869 | ((tdqs_en & 0x1) << 11)
870 | ((rtt & 0x4) << 7) /* rtt field is split */
871 | ((wrlvl_en & 0x1) << 7)
872 | ((rtt & 0x2) << 5) /* rtt field is split */
873 | ((dic & 0x2) << 4) /* DIC field is split */
874 | ((al & 0x3) << 3)
875 | ((rtt & 0x1) << 2) /* rtt field is split */
876 | ((dic & 0x1) << 1) /* DIC field is split */
877 | ((dll_en & 0x1) << 0)
878 );
879
880 /*
881 * DLL control for precharge PD
882 * 0=slow exit DLL off (tXPDLL)
883 * 1=fast exit DLL on (tXP)
884 */
885 dll_on = 1;
886
887 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
888 if (wr_mclk <= 16) {
889 wr = wr_table[wr_mclk - 5];
890 } else {
891 printf("Error: unsupported write recovery for mode register "
892 "wr_mclk = %d\n", wr_mclk);
893 }
894
895 dll_rst = 0; /* dll no reset */
896 mode = 0; /* normal mode */
897
898 /* look up table to get the cas latency bits */
899 if (cas_latency >= 5 && cas_latency <= 16) {
900 unsigned char cas_latency_table[] = {
901 0x2, /* 5 clocks */
902 0x4, /* 6 clocks */
903 0x6, /* 7 clocks */
904 0x8, /* 8 clocks */
905 0xa, /* 9 clocks */
906 0xc, /* 10 clocks */
907 0xe, /* 11 clocks */
908 0x1, /* 12 clocks */
909 0x3, /* 13 clocks */
910 0x5, /* 14 clocks */
911 0x7, /* 15 clocks */
912 0x9, /* 16 clocks */
913 };
914 caslat = cas_latency_table[cas_latency - 5];
915 } else {
916 printf("Error: unsupported cas latency for mode register\n");
917 }
918
919 bt = 0; /* Nibble sequential */
920
921 switch (popts->burst_length) {
922 case DDR_BL8:
923 bl = 0;
924 break;
925 case DDR_OTF:
926 bl = 1;
927 break;
928 case DDR_BC4:
929 bl = 2;
930 break;
931 default:
932 printf("Error: invalid burst length of %u specified. "
933 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
934 popts->burst_length);
935 bl = 1;
936 break;
937 }
938
939 sdmode = (0
940 | ((dll_on & 0x1) << 12)
941 | ((wr & 0x7) << 9)
942 | ((dll_rst & 0x1) << 8)
943 | ((mode & 0x1) << 7)
944 | (((caslat >> 1) & 0x7) << 4)
945 | ((bt & 0x1) << 3)
946 | ((caslat & 1) << 2)
947 | ((bl & 0x3) << 0)
948 );
949
950 ddr->ddr_sdram_mode = (0
951 | ((esdmode & 0xFFFF) << 16)
952 | ((sdmode & 0xFFFF) << 0)
953 );
954
955 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
956
957 if (unq_mrs_en) { /* unique mode registers are supported */
958 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
959 if (popts->rtt_override)
960 rtt = popts->rtt_override_value;
961 else
962 rtt = popts->cs_local_opts[i].odt_rtt_norm;
963
964 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
965 esdmode |= (0
966 | ((rtt & 0x4) << 7) /* rtt field is split */
967 | ((rtt & 0x2) << 5) /* rtt field is split */
968 | ((rtt & 0x1) << 2) /* rtt field is split */
969 );
970 switch (i) {
971 case 1:
972 ddr->ddr_sdram_mode_3 = (0
973 | ((esdmode & 0xFFFF) << 16)
974 | ((sdmode & 0xFFFF) << 0)
975 );
976 break;
977 case 2:
978 ddr->ddr_sdram_mode_5 = (0
979 | ((esdmode & 0xFFFF) << 16)
980 | ((sdmode & 0xFFFF) << 0)
981 );
982 break;
983 case 3:
984 ddr->ddr_sdram_mode_7 = (0
985 | ((esdmode & 0xFFFF) << 16)
986 | ((sdmode & 0xFFFF) << 0)
987 );
988 break;
989 }
990 }
991 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
992 ddr->ddr_sdram_mode_3);
993 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
994 ddr->ddr_sdram_mode_5);
995 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
996 ddr->ddr_sdram_mode_5);
997 }
998 }
999
1000 #else /* !CONFIG_FSL_DDR3 */
1001
1002 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1003 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1004 const memctl_options_t *popts,
1005 const common_timing_params_t *common_dimm,
1006 unsigned int cas_latency,
1007 unsigned int additive_latency,
1008 const unsigned int unq_mrs_en)
1009 {
1010 unsigned short esdmode; /* Extended SDRAM mode */
1011 unsigned short sdmode; /* SDRAM mode */
1012
1013 /*
1014 * FIXME: This ought to be pre-calculated in a
1015 * technology-specific routine,
1016 * e.g. compute_DDR2_mode_register(), and then the
1017 * sdmode and esdmode passed in as part of common_dimm.
1018 */
1019
1020 /* Extended Mode Register */
1021 unsigned int mrs = 0; /* Mode Register Set */
1022 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1023 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1024 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1025 unsigned int ocd = 0; /* 0x0=OCD not supported,
1026 0x7=OCD default state */
1027 unsigned int rtt;
1028 unsigned int al; /* Posted CAS# additive latency (AL) */
1029 unsigned int ods = 0; /* Output Drive Strength:
1030 0 = Full strength (18ohm)
1031 1 = Reduced strength (4ohm) */
1032 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1033 1=Disable (Test/Debug) */
1034
1035 /* Mode Register (MR) */
1036 unsigned int mr; /* Mode Register Definition */
1037 unsigned int pd; /* Power-Down Mode */
1038 unsigned int wr; /* Write Recovery */
1039 unsigned int dll_res; /* DLL Reset */
1040 unsigned int mode; /* Normal=0 or Test=1 */
1041 unsigned int caslat = 0;/* CAS# latency */
1042 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1043 unsigned int bt;
1044 unsigned int bl; /* BL: Burst Length */
1045
1046 #if defined(CONFIG_FSL_DDR2)
1047 const unsigned int mclk_ps = get_memory_clk_period_ps();
1048 #endif
1049 dqs_en = !popts->DQS_config;
1050 rtt = fsl_ddr_get_rtt();
1051
1052 al = additive_latency;
1053
1054 esdmode = (0
1055 | ((mrs & 0x3) << 14)
1056 | ((outputs & 0x1) << 12)
1057 | ((rdqs_en & 0x1) << 11)
1058 | ((dqs_en & 0x1) << 10)
1059 | ((ocd & 0x7) << 7)
1060 | ((rtt & 0x2) << 5) /* rtt field is split */
1061 | ((al & 0x7) << 3)
1062 | ((rtt & 0x1) << 2) /* rtt field is split */
1063 | ((ods & 0x1) << 1)
1064 | ((dll_en & 0x1) << 0)
1065 );
1066
1067 mr = 0; /* FIXME: CHECKME */
1068
1069 /*
1070 * 0 = Fast Exit (Normal)
1071 * 1 = Slow Exit (Low Power)
1072 */
1073 pd = 0;
1074
1075 #if defined(CONFIG_FSL_DDR1)
1076 wr = 0; /* Historical */
1077 #elif defined(CONFIG_FSL_DDR2)
1078 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1079 #endif
1080 dll_res = 0;
1081 mode = 0;
1082
1083 #if defined(CONFIG_FSL_DDR1)
1084 if (1 <= cas_latency && cas_latency <= 4) {
1085 unsigned char mode_caslat_table[4] = {
1086 0x5, /* 1.5 clocks */
1087 0x2, /* 2.0 clocks */
1088 0x6, /* 2.5 clocks */
1089 0x3 /* 3.0 clocks */
1090 };
1091 caslat = mode_caslat_table[cas_latency - 1];
1092 } else {
1093 printf("Warning: unknown cas_latency %d\n", cas_latency);
1094 }
1095 #elif defined(CONFIG_FSL_DDR2)
1096 caslat = cas_latency;
1097 #endif
1098 bt = 0;
1099
1100 switch (popts->burst_length) {
1101 case DDR_BL4:
1102 bl = 2;
1103 break;
1104 case DDR_BL8:
1105 bl = 3;
1106 break;
1107 default:
1108 printf("Error: invalid burst length of %u specified. "
1109 " Defaulting to 4 beats.\n",
1110 popts->burst_length);
1111 bl = 2;
1112 break;
1113 }
1114
1115 sdmode = (0
1116 | ((mr & 0x3) << 14)
1117 | ((pd & 0x1) << 12)
1118 | ((wr & 0x7) << 9)
1119 | ((dll_res & 0x1) << 8)
1120 | ((mode & 0x1) << 7)
1121 | ((caslat & 0x7) << 4)
1122 | ((bt & 0x1) << 3)
1123 | ((bl & 0x7) << 0)
1124 );
1125
1126 ddr->ddr_sdram_mode = (0
1127 | ((esdmode & 0xFFFF) << 16)
1128 | ((sdmode & 0xFFFF) << 0)
1129 );
1130 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1131 }
1132 #endif
1133
1134 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1135 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1136 {
1137 unsigned int init_value; /* Initialization value */
1138
1139 init_value = 0xDEADBEEF;
1140 ddr->ddr_data_init = init_value;
1141 }
1142
1143 /*
1144 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1145 * The old controller on the 8540/60 doesn't have this register.
1146 * Hope it's OK to set it (to 0) anyway.
1147 */
1148 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1149 const memctl_options_t *popts)
1150 {
1151 unsigned int clk_adjust; /* Clock adjust */
1152
1153 clk_adjust = popts->clk_adjust;
1154 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1155 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1156 }
1157
1158 /* DDR Initialization Address (DDR_INIT_ADDR) */
1159 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1160 {
1161 unsigned int init_addr = 0; /* Initialization address */
1162
1163 ddr->ddr_init_addr = init_addr;
1164 }
1165
1166 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1167 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1168 {
1169 unsigned int uia = 0; /* Use initialization address */
1170 unsigned int init_ext_addr = 0; /* Initialization address */
1171
1172 ddr->ddr_init_ext_addr = (0
1173 | ((uia & 0x1) << 31)
1174 | (init_ext_addr & 0xF)
1175 );
1176 }
1177
1178 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1179 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1180 const memctl_options_t *popts)
1181 {
1182 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1183 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1184 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1185 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1186 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1187
1188 #if defined(CONFIG_FSL_DDR3)
1189 if (popts->burst_length == DDR_BL8) {
1190 /* We set BL/2 for fixed BL8 */
1191 rrt = 0; /* BL/2 clocks */
1192 wwt = 0; /* BL/2 clocks */
1193 } else {
1194 /* We need to set BL/2 + 2 to BC4 and OTF */
1195 rrt = 2; /* BL/2 + 2 clocks */
1196 wwt = 2; /* BL/2 + 2 clocks */
1197 }
1198 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1199 #endif
1200 ddr->timing_cfg_4 = (0
1201 | ((rwt & 0xf) << 28)
1202 | ((wrt & 0xf) << 24)
1203 | ((rrt & 0xf) << 20)
1204 | ((wwt & 0xf) << 16)
1205 | (dll_lock & 0x3)
1206 );
1207 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1208 }
1209
1210 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1211 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1212 {
1213 unsigned int rodt_on = 0; /* Read to ODT on */
1214 unsigned int rodt_off = 0; /* Read to ODT off */
1215 unsigned int wodt_on = 0; /* Write to ODT on */
1216 unsigned int wodt_off = 0; /* Write to ODT off */
1217
1218 #if defined(CONFIG_FSL_DDR3)
1219 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1220 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1221 rodt_off = 4; /* 4 clocks */
1222 wodt_on = 1; /* 1 clocks */
1223 wodt_off = 4; /* 4 clocks */
1224 #endif
1225
1226 ddr->timing_cfg_5 = (0
1227 | ((rodt_on & 0x1f) << 24)
1228 | ((rodt_off & 0x7) << 20)
1229 | ((wodt_on & 0x1f) << 12)
1230 | ((wodt_off & 0x7) << 8)
1231 );
1232 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1233 }
1234
1235 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1236 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1237 {
1238 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1239 /* Normal Operation Full Calibration Time (tZQoper) */
1240 unsigned int zqoper = 0;
1241 /* Normal Operation Short Calibration Time (tZQCS) */
1242 unsigned int zqcs = 0;
1243
1244 if (zq_en) {
1245 zqinit = 9; /* 512 clocks */
1246 zqoper = 8; /* 256 clocks */
1247 zqcs = 6; /* 64 clocks */
1248 }
1249
1250 ddr->ddr_zq_cntl = (0
1251 | ((zq_en & 0x1) << 31)
1252 | ((zqinit & 0xF) << 24)
1253 | ((zqoper & 0xF) << 16)
1254 | ((zqcs & 0xF) << 8)
1255 );
1256 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1257 }
1258
1259 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1260 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1261 const memctl_options_t *popts)
1262 {
1263 /*
1264 * First DQS pulse rising edge after margining mode
1265 * is programmed (tWL_MRD)
1266 */
1267 unsigned int wrlvl_mrd = 0;
1268 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1269 unsigned int wrlvl_odten = 0;
1270 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1271 unsigned int wrlvl_dqsen = 0;
1272 /* WRLVL_SMPL: Write leveling sample time */
1273 unsigned int wrlvl_smpl = 0;
1274 /* WRLVL_WLR: Write leveling repeition time */
1275 unsigned int wrlvl_wlr = 0;
1276 /* WRLVL_START: Write leveling start time */
1277 unsigned int wrlvl_start = 0;
1278
1279 /* suggest enable write leveling for DDR3 due to fly-by topology */
1280 if (wrlvl_en) {
1281 /* tWL_MRD min = 40 nCK, we set it 64 */
1282 wrlvl_mrd = 0x6;
1283 /* tWL_ODTEN 128 */
1284 wrlvl_odten = 0x7;
1285 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1286 wrlvl_dqsen = 0x5;
1287 /*
1288 * Write leveling sample time at least need 6 clocks
1289 * higher than tWLO to allow enough time for progagation
1290 * delay and sampling the prime data bits.
1291 */
1292 wrlvl_smpl = 0xf;
1293 /*
1294 * Write leveling repetition time
1295 * at least tWLO + 6 clocks clocks
1296 * we set it 64
1297 */
1298 wrlvl_wlr = 0x6;
1299 /*
1300 * Write leveling start time
1301 * The value use for the DQS_ADJUST for the first sample
1302 * when write leveling is enabled. It probably needs to be
1303 * overriden per platform.
1304 */
1305 wrlvl_start = 0x8;
1306 /*
1307 * Override the write leveling sample and start time
1308 * according to specific board
1309 */
1310 if (popts->wrlvl_override) {
1311 wrlvl_smpl = popts->wrlvl_sample;
1312 wrlvl_start = popts->wrlvl_start;
1313 }
1314 }
1315
1316 ddr->ddr_wrlvl_cntl = (0
1317 | ((wrlvl_en & 0x1) << 31)
1318 | ((wrlvl_mrd & 0x7) << 24)
1319 | ((wrlvl_odten & 0x7) << 20)
1320 | ((wrlvl_dqsen & 0x7) << 16)
1321 | ((wrlvl_smpl & 0xf) << 12)
1322 | ((wrlvl_wlr & 0x7) << 8)
1323 | ((wrlvl_start & 0x1F) << 0)
1324 );
1325 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1326 }
1327
1328 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1329 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1330 {
1331 /* Self Refresh Idle Threshold */
1332 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1333 }
1334
1335 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1336 {
1337 if (popts->addr_hash) {
1338 ddr->ddr_eor = 0x40000000; /* address hash enable */
1339 puts("Address hashing enabled.\n");
1340 }
1341 }
1342
1343 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1344 {
1345 ddr->ddr_cdr1 = popts->ddr_cdr1;
1346 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1347 }
1348
1349 unsigned int
1350 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1351 {
1352 unsigned int res = 0;
1353
1354 /*
1355 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1356 * not set at the same time.
1357 */
1358 if (ddr->ddr_sdram_cfg & 0x10000000
1359 && ddr->ddr_sdram_cfg & 0x00008000) {
1360 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1361 " should not be set at the same time.\n");
1362 res++;
1363 }
1364
1365 return res;
1366 }
1367
1368 unsigned int
1369 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1370 fsl_ddr_cfg_regs_t *ddr,
1371 const common_timing_params_t *common_dimm,
1372 const dimm_params_t *dimm_params,
1373 unsigned int dbw_cap_adj,
1374 unsigned int size_only)
1375 {
1376 unsigned int i;
1377 unsigned int cas_latency;
1378 unsigned int additive_latency;
1379 unsigned int sr_it;
1380 unsigned int zq_en;
1381 unsigned int wrlvl_en;
1382 unsigned int ip_rev = 0;
1383 unsigned int unq_mrs_en = 0;
1384 int cs_en = 1;
1385
1386 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1387
1388 if (common_dimm == NULL) {
1389 printf("Error: subset DIMM params struct null pointer\n");
1390 return 1;
1391 }
1392
1393 /*
1394 * Process overrides first.
1395 *
1396 * FIXME: somehow add dereated caslat to this
1397 */
1398 cas_latency = (popts->cas_latency_override)
1399 ? popts->cas_latency_override_value
1400 : common_dimm->lowest_common_SPD_caslat;
1401
1402 additive_latency = (popts->additive_latency_override)
1403 ? popts->additive_latency_override_value
1404 : common_dimm->additive_latency;
1405
1406 sr_it = (popts->auto_self_refresh_en)
1407 ? popts->sr_it
1408 : 0;
1409 /* ZQ calibration */
1410 zq_en = (popts->zq_en) ? 1 : 0;
1411 /* write leveling */
1412 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1413
1414 /* Chip Select Memory Bounds (CSn_BNDS) */
1415 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1416 unsigned long long ea = 0, sa = 0;
1417 unsigned int cs_per_dimm
1418 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1419 unsigned int dimm_number
1420 = i / cs_per_dimm;
1421 unsigned long long rank_density
1422 = dimm_params[dimm_number].rank_density;
1423
1424 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1425 ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1426 ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1427 /*
1428 * Don't set up boundaries for unused CS
1429 * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1430 * cs2 for cs0_cs1_cs2_cs3
1431 * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1432 * But we need to set the ODT_RD_CFG and
1433 * ODT_WR_CFG for CS1_CONFIG here.
1434 */
1435 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1436 continue;
1437 }
1438 if (dimm_params[dimm_number].n_ranks == 0) {
1439 debug("Skipping setup of CS%u "
1440 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1441 continue;
1442 }
1443 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1444 /*
1445 * This works superbank 2CS
1446 * There are 2 or more memory controllers configured
1447 * identically, memory is interleaved between them,
1448 * and each controller uses rank interleaving within
1449 * itself. Therefore the starting and ending address
1450 * on each controller is twice the amount present on
1451 * each controller. If any CS is not included in the
1452 * interleaving, the memory on that CS is not accssible
1453 * and the total memory size is reduced. The CS is also
1454 * disabled.
1455 */
1456 unsigned long long ctlr_density = 0;
1457 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1458 case FSL_DDR_CS0_CS1:
1459 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1460 ctlr_density = dimm_params[0].rank_density * 2;
1461 if (i > 1)
1462 cs_en = 0;
1463 break;
1464 case FSL_DDR_CS2_CS3:
1465 ctlr_density = dimm_params[0].rank_density;
1466 if (i > 0)
1467 cs_en = 0;
1468 break;
1469 case FSL_DDR_CS0_CS1_CS2_CS3:
1470 /*
1471 * The four CS interleaving should have been verified by
1472 * populate_memctl_options()
1473 */
1474 ctlr_density = dimm_params[0].rank_density * 4;
1475 break;
1476 default:
1477 break;
1478 }
1479 ea = (CONFIG_NUM_DDR_CONTROLLERS *
1480 (ctlr_density >> dbw_cap_adj)) - 1;
1481 }
1482 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1483 /*
1484 * If memory interleaving between controllers is NOT
1485 * enabled, the starting address for each memory
1486 * controller is distinct. However, because rank
1487 * interleaving is enabled, the starting and ending
1488 * addresses of the total memory on that memory
1489 * controller needs to be programmed into its
1490 * respective CS0_BNDS.
1491 */
1492 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1493 case FSL_DDR_CS0_CS1_CS2_CS3:
1494 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1495 * needs to be set.
1496 */
1497 sa = common_dimm->base_address;
1498 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1499 break;
1500 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1501 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1502 * and CS2_CNDS need to be set.
1503 */
1504 if ((i == 2) && (dimm_number == 0)) {
1505 sa = dimm_params[dimm_number].base_address +
1506 2 * (rank_density >> dbw_cap_adj);
1507 ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1508 } else {
1509 sa = dimm_params[dimm_number].base_address;
1510 ea = sa + (2 * (rank_density >>
1511 dbw_cap_adj)) - 1;
1512 }
1513 break;
1514 case FSL_DDR_CS0_CS1:
1515 /* CS0+CS1 interleaving, CS0_CNDS needs
1516 * to be set
1517 */
1518 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1519 sa = dimm_params[dimm_number].base_address;
1520 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1521 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1522 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1523 } else {
1524 sa = 0;
1525 ea = 0;
1526 }
1527 if (i == 0)
1528 ea += (rank_density >> dbw_cap_adj);
1529 break;
1530 case FSL_DDR_CS2_CS3:
1531 /* CS2+CS3 interleaving*/
1532 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1533 sa = dimm_params[dimm_number].base_address;
1534 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1535 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1536 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1537 } else {
1538 sa = 0;
1539 ea = 0;
1540 }
1541 if (i == 2)
1542 ea += (rank_density >> dbw_cap_adj);
1543 break;
1544 default: /* No bank(chip-select) interleaving */
1545 break;
1546 }
1547 }
1548 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1549 /*
1550 * Only the rank on CS0 of each memory controller may
1551 * be used if memory controller interleaving is used
1552 * without rank interleaving within each memory
1553 * controller. However, the ending address programmed
1554 * into each CS0 must be the sum of the amount of
1555 * memory in the two CS0 ranks.
1556 */
1557 if (i == 0) {
1558 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1559 }
1560
1561 }
1562 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1563 /*
1564 * No rank interleaving and no memory controller
1565 * interleaving.
1566 */
1567 sa = dimm_params[dimm_number].base_address;
1568 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1569 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1570 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1571 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1572 } else {
1573 sa = 0;
1574 ea = 0;
1575 }
1576 }
1577
1578 sa >>= 24;
1579 ea >>= 24;
1580
1581 ddr->cs[i].bnds = (0
1582 | ((sa & 0xFFF) << 16) /* starting address MSB */
1583 | ((ea & 0xFFF) << 0) /* ending address MSB */
1584 );
1585
1586 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1587 if (cs_en) {
1588 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1589 set_csn_config_2(i, ddr);
1590 } else
1591 debug("CS%d is disabled.\n", i);
1592 }
1593
1594 /*
1595 * In the case we only need to compute the ddr sdram size, we only need
1596 * to set csn registers, so return from here.
1597 */
1598 if (size_only)
1599 return 0;
1600
1601 set_ddr_eor(ddr, popts);
1602
1603 #if !defined(CONFIG_FSL_DDR1)
1604 set_timing_cfg_0(ddr, popts);
1605 #endif
1606
1607 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1608 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1609 set_timing_cfg_2(ddr, popts, common_dimm,
1610 cas_latency, additive_latency);
1611
1612 set_ddr_cdr1(ddr, popts);
1613 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1614 ip_rev = fsl_ddr_get_version();
1615 if (ip_rev > 0x40400)
1616 unq_mrs_en = 1;
1617
1618 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1619 set_ddr_sdram_mode(ddr, popts, common_dimm,
1620 cas_latency, additive_latency, unq_mrs_en);
1621 set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1622 set_ddr_sdram_interval(ddr, popts, common_dimm);
1623 set_ddr_data_init(ddr);
1624 set_ddr_sdram_clk_cntl(ddr, popts);
1625 set_ddr_init_addr(ddr);
1626 set_ddr_init_ext_addr(ddr);
1627 set_timing_cfg_4(ddr, popts);
1628 set_timing_cfg_5(ddr, cas_latency);
1629
1630 set_ddr_zq_cntl(ddr, zq_en);
1631 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1632
1633 set_ddr_sr_cntr(ddr, sr_it);
1634
1635 set_ddr_sdram_rcw(ddr, popts, common_dimm);
1636
1637 return check_fsl_memctl_config_regs(ddr);
1638 }
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