2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
16 #include <asm/fsl_ddr_sdram.h>
20 extern void fsl_ddr_set_lawbar(
21 const common_timing_params_t
*memctl_common_params
,
22 unsigned int memctl_interleaved
,
23 unsigned int ctrl_num
);
25 /* processor specific function */
26 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs
,
27 unsigned int ctrl_num
);
29 /* Board-specific functions defined in each board's ddr.c */
30 extern void fsl_ddr_get_spd(generic_spd_eeprom_t
*ctrl_dimms_spd
,
31 unsigned int ctrl_num
);
35 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
36 * - Same memory data bus width on all controllers
40 * The memory controller and associated documentation use confusing
41 * terminology when referring to the orgranization of DRAM.
43 * Here is a terminology translation table:
45 * memory controller/documention |industry |this code |signals
46 * -------------------------------|-----------|-----------|-----------------
47 * physical bank/bank |rank |rank |chip select (CS)
48 * logical bank/sub-bank |bank |bank |bank address (BA)
49 * page/row |row |page |row address
50 * ??? |column |column |column address
52 * The naming confusion is further exacerbated by the descriptions of the
53 * memory controller interleaving feature, where accesses are interleaved
54 * _BETWEEN_ two seperate memory controllers. This is configured only in
55 * CS0_CONFIG[INTLV_CTL] of each memory controller.
57 * memory controller documentation | number of chip selects
58 * | per memory controller supported
59 * --------------------------------|-----------------------------------------
60 * cache line interleaving | 1 (CS0 only)
61 * page interleaving | 1 (CS0 only)
62 * bank interleaving | 1 (CS0 only)
63 * superbank interleraving | depends on bank (chip select)
64 * | interleraving [rank interleaving]
65 * | mode used on every memory controller
67 * Even further confusing is the existence of the interleaving feature
68 * _WITHIN_ each memory controller. The feature is referred to in
69 * documentation as chip select interleaving or bank interleaving,
70 * although it is configured in the DDR_SDRAM_CFG field.
72 * Name of field | documentation name | this code
73 * -----------------------------|-----------------------|------------------
74 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
79 const char *step_string_tbl
[] = {
81 "STEP_COMPUTE_DIMM_PARMS",
82 "STEP_COMPUTE_COMMON_PARMS",
84 "STEP_ASSIGN_ADDRESSES",
90 const char * step_to_string(unsigned int step
) {
92 unsigned int s
= __ilog2(step
);
95 return step_string_tbl
[7];
97 return step_string_tbl
[s
];
101 int step_assign_addresses(fsl_ddr_info_t
*pinfo
,
102 unsigned int dbw_cap_adj
[],
103 unsigned int *memctl_interleaving
,
104 unsigned int *rank_interleaving
)
109 * If a reduced data width is requested, but the SPD
110 * specifies a physically wider device, adjust the
111 * computed dimm capacities accordingly before
112 * assigning addresses.
114 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
115 unsigned int found
= 0;
117 switch (pinfo
->memctl_opts
[i
].data_bus_width
) {
120 printf("can't handle 16-bit mode yet\n");
125 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
127 dw
= pinfo
->dimm_params
[i
][j
].data_width
;
128 if (pinfo
->dimm_params
[i
][j
].n_ranks
129 && (dw
== 72 || dw
== 64)) {
131 * FIXME: can't really do it
132 * like this because this just
133 * further reduces the memory
149 printf("unexpected data bus width "
150 "specified controller %u\n", i
);
156 * Check if all controllers are configured for memory
157 * controller interleaving.
160 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
161 if (pinfo
->memctl_opts
[i
].memctl_interleaving
) {
166 *memctl_interleaving
= 1;
168 /* Check that all controllers are rank interleaving. */
170 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
171 if (pinfo
->memctl_opts
[i
].ba_intlv_ctl
) {
176 *rank_interleaving
= 1;
178 if (*memctl_interleaving
) {
179 unsigned long long addr
, total_mem_per_ctlr
= 0;
181 * If interleaving between memory controllers,
182 * make each controller start at a base address
185 * Also, if bank interleaving (chip select
186 * interleaving) is enabled on each memory
187 * controller, CS0 needs to be programmed to
188 * cover the entire memory range on that memory
191 * Bank interleaving also implies that each
192 * addressed chip select is identical in size.
195 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
197 pinfo
->common_timing_params
[i
].base_address
= 0ull;
198 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
199 unsigned long long cap
200 = pinfo
->dimm_params
[i
][j
].capacity
;
202 pinfo
->dimm_params
[i
][j
].base_address
= addr
;
203 addr
+= cap
>> dbw_cap_adj
[i
];
204 total_mem_per_ctlr
+= cap
>> dbw_cap_adj
[i
];
207 pinfo
->common_timing_params
[0].total_mem
= total_mem_per_ctlr
;
210 * Simple linear assignment if memory
211 * controllers are not interleaved.
213 unsigned long long cur_memsize
= 0;
214 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
215 u64 total_mem_per_ctlr
= 0;
216 pinfo
->common_timing_params
[i
].base_address
=
218 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
219 /* Compute DIMM base addresses. */
220 unsigned long long cap
=
221 pinfo
->dimm_params
[i
][j
].capacity
;
222 pinfo
->dimm_params
[i
][j
].base_address
=
224 cur_memsize
+= cap
>> dbw_cap_adj
[i
];
225 total_mem_per_ctlr
+= cap
>> dbw_cap_adj
[i
];
227 pinfo
->common_timing_params
[i
].total_mem
=
236 fsl_ddr_compute(fsl_ddr_info_t
*pinfo
, unsigned int start_step
)
239 unsigned int all_controllers_memctl_interleaving
= 0;
240 unsigned int all_controllers_rank_interleaving
= 0;
241 unsigned long long total_mem
= 0;
243 fsl_ddr_cfg_regs_t
*ddr_reg
= pinfo
->fsl_ddr_config_reg
;
244 common_timing_params_t
*timing_params
= pinfo
->common_timing_params
;
246 /* data bus width capacity adjust shift amount */
247 unsigned int dbw_capacity_adjust
[CONFIG_NUM_DDR_CONTROLLERS
];
249 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
250 dbw_capacity_adjust
[i
] = 0;
253 debug("starting at step %u (%s)\n",
254 start_step
, step_to_string(start_step
));
256 switch (start_step
) {
258 /* STEP 1: Gather all DIMM SPD data */
259 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
260 fsl_ddr_get_spd(pinfo
->spd_installed_dimms
[i
], i
);
263 case STEP_COMPUTE_DIMM_PARMS
:
264 /* STEP 2: Compute DIMM parameters from SPD data */
266 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
267 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
269 generic_spd_eeprom_t
*spd
=
270 &(pinfo
->spd_installed_dimms
[i
][j
]);
271 dimm_params_t
*pdimm
=
272 &(pinfo
->dimm_params
[i
][j
]);
274 retval
= compute_dimm_parameters(spd
, pdimm
, i
);
276 printf("Error: compute_dimm_parameters"
277 " non-zero returned FATAL value "
278 "for memctl=%u dimm=%u\n", i
, j
);
282 debug("Warning: compute_dimm_parameters"
283 " non-zero return value for memctl=%u "
289 case STEP_COMPUTE_COMMON_PARMS
:
291 * STEP 3: Compute a common set of timing parameters
292 * suitable for all of the DIMMs on each memory controller
294 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
295 debug("Computing lowest common DIMM"
296 " parameters for memctl=%u\n", i
);
297 compute_lowest_common_dimm_parameters(
298 pinfo
->dimm_params
[i
],
300 CONFIG_DIMM_SLOTS_PER_CTLR
);
303 case STEP_GATHER_OPTS
:
304 /* STEP 4: Gather configuration requirements from user */
305 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
306 debug("Reloading memory controller "
307 "configuration options for memctl=%u\n", i
);
309 * This "reloads" the memory controller options
310 * to defaults. If the user "edits" an option,
311 * next_step points to the step after this,
312 * which is currently STEP_ASSIGN_ADDRESSES.
314 populate_memctl_options(
315 timing_params
[i
].all_DIMMs_registered
,
316 &pinfo
->memctl_opts
[i
],
317 pinfo
->dimm_params
[i
], i
);
320 case STEP_ASSIGN_ADDRESSES
:
321 /* STEP 5: Assign addresses to chip selects */
322 step_assign_addresses(pinfo
,
324 &all_controllers_memctl_interleaving
,
325 &all_controllers_rank_interleaving
);
327 case STEP_COMPUTE_REGS
:
328 /* STEP 6: compute controller register values */
329 debug("FSL Memory ctrl cg register computation\n");
330 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
331 if (timing_params
[i
].ndimms_present
== 0) {
332 memset(&ddr_reg
[i
], 0,
333 sizeof(fsl_ddr_cfg_regs_t
));
337 compute_fsl_memctl_config_regs(
338 &pinfo
->memctl_opts
[i
],
339 &ddr_reg
[i
], &timing_params
[i
],
340 pinfo
->dimm_params
[i
],
341 dbw_capacity_adjust
[i
]);
348 /* Compute the total amount of memory. */
351 * If bank interleaving but NOT memory controller interleaving
352 * CS_BNDS describe the quantity of memory on each memory
353 * controller, so the total is the sum across.
355 if (!all_controllers_memctl_interleaving
356 && all_controllers_rank_interleaving
) {
358 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
359 total_mem
+= timing_params
[i
].total_mem
;
364 * Compute the amount of memory available just by
365 * looking for the highest valid CSn_BNDS value.
366 * This allows us to also experiment with using
367 * only CS0 when using dual-rank DIMMs.
369 unsigned int max_end
= 0;
371 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
372 for (j
= 0; j
< CONFIG_CHIP_SELECTS_PER_CTRL
; j
++) {
373 fsl_ddr_cfg_regs_t
*reg
= &ddr_reg
[i
];
374 if (reg
->cs
[j
].config
& 0x80000000) {
376 end
= reg
->cs
[j
].bnds
& 0xFFF;
384 total_mem
= 1 + (((unsigned long long)max_end
<< 24ULL)
392 * fsl_ddr_sdram() -- this is the main function to be called by
393 * initdram() in the board file.
395 * It returns amount of memory configured in bytes.
397 phys_size_t
fsl_ddr_sdram(void)
400 unsigned int memctl_interleaved
;
401 unsigned long long total_memory
;
404 /* Reset info structure. */
405 memset(&info
, 0, sizeof(fsl_ddr_info_t
));
407 /* Compute it once normally. */
408 total_memory
= fsl_ddr_compute(&info
, STEP_GET_SPD
);
410 /* Check for memory controller interleaving. */
411 memctl_interleaved
= 0;
412 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
413 memctl_interleaved
+=
414 info
.memctl_opts
[i
].memctl_interleaving
;
417 if (memctl_interleaved
) {
418 if (memctl_interleaved
== CONFIG_NUM_DDR_CONTROLLERS
) {
419 debug("memctl interleaving\n");
421 * Change the meaning of memctl_interleaved
424 memctl_interleaved
= 1;
426 printf("Warning: memctl interleaving not "
427 "properly configured on all controllers\n");
428 memctl_interleaved
= 0;
429 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++)
430 info
.memctl_opts
[i
].memctl_interleaving
= 0;
431 debug("Recomputing with memctl_interleaving off.\n");
432 total_memory
= fsl_ddr_compute(&info
,
433 STEP_ASSIGN_ADDRESSES
);
437 /* Program configuration registers. */
438 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
439 debug("Programming controller %u\n", i
);
440 if (info
.common_timing_params
[i
].ndimms_present
== 0) {
441 debug("No dimms present on controller %u; "
442 "skipping programming\n", i
);
446 fsl_ddr_set_memctl_regs(&(info
.fsl_ddr_config_reg
[i
]), i
);
449 if (memctl_interleaved
) {
450 const unsigned int ctrl_num
= 0;
452 /* Only set LAWBAR1 if memory controller interleaving is on. */
453 fsl_ddr_set_lawbar(&info
.common_timing_params
[0],
454 memctl_interleaved
, ctrl_num
);
457 * Memory controller interleaving is NOT on;
458 * set each lawbar individually.
460 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
461 fsl_ddr_set_lawbar(&info
.common_timing_params
[i
],
466 debug("total_memory = %llu\n", total_memory
);
468 #if !defined(CONFIG_PHYS_64BIT)
469 /* Check for 4G or more. Bad. */
470 if (total_memory
>= (1ull << 32)) {
471 printf("Detected %lld MB of memory\n", total_memory
>> 20);
472 printf("This U-Boot only supports < 4G of DDR\n");
473 printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
474 total_memory
= CONFIG_MAX_MEM_MAPPED
;