2 * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/fsl_ddr_sdram.h>
14 * Use our own stack based buffer before relocation to allow accessing longer
15 * hwconfig strings that might be in the environment before we've relocated.
16 * This is pretty fragile on both the use of stack and if the buffer is big
17 * enough. However we will get a warning from getenv_f for the later.
20 /* Board-specific functions defined in each board's ddr.c */
21 extern void fsl_ddr_board_options(memctl_options_t
*popts
,
23 unsigned int ctrl_num
);
26 unsigned int odt_rd_cfg
;
27 unsigned int odt_wr_cfg
;
28 unsigned int odt_rtt_norm
;
29 unsigned int odt_rtt_wr
;
32 #ifdef CONFIG_FSL_DDR3
33 static const struct dynamic_odt single_Q
[4] = {
36 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
42 FSL_DDR_ODT_NEVER
, /* tied high */
48 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
54 FSL_DDR_ODT_NEVER
, /* tied high */
60 static const struct dynamic_odt single_D
[4] = {
77 static const struct dynamic_odt single_S
[4] = {
89 static const struct dynamic_odt dual_DD
[4] = {
92 FSL_DDR_ODT_SAME_DIMM
,
97 FSL_DDR_ODT_OTHER_DIMM
,
98 FSL_DDR_ODT_OTHER_DIMM
,
104 FSL_DDR_ODT_SAME_DIMM
,
109 FSL_DDR_ODT_OTHER_DIMM
,
110 FSL_DDR_ODT_OTHER_DIMM
,
116 static const struct dynamic_odt dual_DS
[4] = {
119 FSL_DDR_ODT_SAME_DIMM
,
124 FSL_DDR_ODT_OTHER_DIMM
,
125 FSL_DDR_ODT_OTHER_DIMM
,
130 FSL_DDR_ODT_OTHER_DIMM
,
137 static const struct dynamic_odt dual_SD
[4] = {
139 FSL_DDR_ODT_OTHER_DIMM
,
147 FSL_DDR_ODT_SAME_DIMM
,
152 FSL_DDR_ODT_OTHER_DIMM
,
153 FSL_DDR_ODT_OTHER_DIMM
,
159 static const struct dynamic_odt dual_SS
[4] = {
161 FSL_DDR_ODT_OTHER_DIMM
,
168 FSL_DDR_ODT_OTHER_DIMM
,
176 static const struct dynamic_odt dual_D0
[4] = {
179 FSL_DDR_ODT_SAME_DIMM
,
193 static const struct dynamic_odt dual_0D
[4] = {
198 FSL_DDR_ODT_SAME_DIMM
,
210 static const struct dynamic_odt dual_S0
[4] = {
223 static const struct dynamic_odt dual_0S
[4] = {
236 static const struct dynamic_odt odt_unknown
[4] = {
262 #else /* CONFIG_FSL_DDR3 */
263 static const struct dynamic_odt single_Q
[4] = {
270 static const struct dynamic_odt single_D
[4] = {
287 static const struct dynamic_odt single_S
[4] = {
299 static const struct dynamic_odt dual_DD
[4] = {
301 FSL_DDR_ODT_OTHER_DIMM
,
302 FSL_DDR_ODT_OTHER_DIMM
,
313 FSL_DDR_ODT_OTHER_DIMM
,
314 FSL_DDR_ODT_OTHER_DIMM
,
326 static const struct dynamic_odt dual_DS
[4] = {
328 FSL_DDR_ODT_OTHER_DIMM
,
329 FSL_DDR_ODT_OTHER_DIMM
,
340 FSL_DDR_ODT_OTHER_DIMM
,
341 FSL_DDR_ODT_OTHER_DIMM
,
348 static const struct dynamic_odt dual_SD
[4] = {
350 FSL_DDR_ODT_OTHER_DIMM
,
351 FSL_DDR_ODT_OTHER_DIMM
,
357 FSL_DDR_ODT_OTHER_DIMM
,
358 FSL_DDR_ODT_OTHER_DIMM
,
370 static const struct dynamic_odt dual_SS
[4] = {
372 FSL_DDR_ODT_OTHER_DIMM
,
373 FSL_DDR_ODT_OTHER_DIMM
,
379 FSL_DDR_ODT_OTHER_DIMM
,
380 FSL_DDR_ODT_OTHER_DIMM
,
387 static const struct dynamic_odt dual_D0
[4] = {
404 static const struct dynamic_odt dual_0D
[4] = {
421 static const struct dynamic_odt dual_S0
[4] = {
434 static const struct dynamic_odt dual_0S
[4] = {
447 static const struct dynamic_odt odt_unknown
[4] = {
476 * Automatically seleect bank interleaving mode based on DIMMs
477 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
478 * This function only deal with one or two slots per controller.
480 static inline unsigned int auto_bank_intlv(dimm_params_t
*pdimm
)
482 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
483 if (pdimm
[0].n_ranks
== 4)
484 return FSL_DDR_CS0_CS1_CS2_CS3
;
485 else if (pdimm
[0].n_ranks
== 2)
486 return FSL_DDR_CS0_CS1
;
487 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
488 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
489 if (pdimm
[0].n_ranks
== 4)
490 return FSL_DDR_CS0_CS1_CS2_CS3
;
492 if (pdimm
[0].n_ranks
== 2) {
493 if (pdimm
[1].n_ranks
== 2)
494 return FSL_DDR_CS0_CS1_CS2_CS3
;
496 return FSL_DDR_CS0_CS1
;
502 unsigned int populate_memctl_options(int all_DIMMs_registered
,
503 memctl_options_t
*popts
,
504 dimm_params_t
*pdimm
,
505 unsigned int ctrl_num
)
508 char buffer
[HWCONFIG_BUFFER_SIZE
];
510 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
511 const struct dynamic_odt
*pdodt
= odt_unknown
;
516 * Extract hwconfig from environment since we have not properly setup
517 * the environment but need it for ddr config params
519 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
522 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
523 /* Chip select options. */
524 if (CONFIG_DIMM_SLOTS_PER_CTLR
== 1) {
525 switch (pdimm
[0].n_ranks
) {
536 } else if (CONFIG_DIMM_SLOTS_PER_CTLR
== 2) {
537 switch (pdimm
[0].n_ranks
) {
538 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
541 if (pdimm
[1].n_ranks
)
542 printf("Error: Quad- and Dual-rank DIMMs "
543 "cannot be used together\n");
547 switch (pdimm
[1].n_ranks
) {
560 switch (pdimm
[1].n_ranks
) {
573 switch (pdimm
[1].n_ranks
) {
586 /* Pick chip-select local options. */
587 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
588 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
589 popts
->cs_local_opts
[i
].odt_rd_cfg
= pdodt
[i
].odt_rd_cfg
;
590 popts
->cs_local_opts
[i
].odt_wr_cfg
= pdodt
[i
].odt_wr_cfg
;
591 popts
->cs_local_opts
[i
].odt_rtt_norm
= pdodt
[i
].odt_rtt_norm
;
592 popts
->cs_local_opts
[i
].odt_rtt_wr
= pdodt
[i
].odt_rtt_wr
;
594 popts
->cs_local_opts
[i
].odt_rd_cfg
= FSL_DDR_ODT_NEVER
;
595 popts
->cs_local_opts
[i
].odt_wr_cfg
= FSL_DDR_ODT_CS
;
597 popts
->cs_local_opts
[i
].auto_precharge
= 0;
600 /* Pick interleaving mode. */
603 * 0 = no interleaving
604 * 1 = interleaving between 2 controllers
606 popts
->memctl_interleaving
= 0;
612 * 3 = superbank (only if CS interleaving is enabled)
614 popts
->memctl_interleaving_mode
= 0;
617 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
618 * 1: page: bit to the left of the column bits selects the memctl
619 * 2: bank: bit to the left of the bank bits selects the memctl
620 * 3: superbank: bit to the left of the chip select selects the memctl
622 * NOTE: ba_intlv (rank interleaving) is independent of memory
623 * controller interleaving; it is only within a memory controller.
624 * Must use superbank interleaving if rank interleaving is used and
625 * memory controller interleaving is enabled.
632 * 0x60 = CS0,CS1 + CS2,CS3
633 * 0x04 = CS0,CS1,CS2,CS3
635 popts
->ba_intlv_ctl
= 0;
637 /* Memory Organization Parameters */
638 popts
->registered_dimm_en
= all_DIMMs_registered
;
640 /* Operational Mode Paramters */
643 popts
->ECC_mode
= 0; /* 0 = disabled, 1 = enabled */
644 #ifdef CONFIG_DDR_ECC
645 if (hwconfig_sub_f("fsl_ddr", "ecc", buf
)) {
646 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf
))
651 popts
->ECC_init_using_memctl
= 1; /* 0 = use DMA, 1 = use memctl */
658 #if defined(CONFIG_FSL_DDR1)
659 popts
->DQS_config
= 0;
660 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
661 popts
->DQS_config
= 1;
664 /* Choose self-refresh during sleep. */
665 popts
->self_refresh_in_sleep
= 1;
667 /* Choose dynamic power management mode. */
668 popts
->dynamic_power
= 0;
671 * check first dimm for primary sdram width
672 * presuming all dimms are similar
673 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
675 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
676 if (pdimm
[0].n_ranks
!= 0) {
677 if ((pdimm
[0].data_width
>= 64) && \
678 (pdimm
[0].data_width
<= 72))
679 popts
->data_bus_width
= 0;
680 else if ((pdimm
[0].data_width
>= 32) || \
681 (pdimm
[0].data_width
<= 40))
682 popts
->data_bus_width
= 1;
684 panic("Error: data width %u is invalid!\n",
685 pdimm
[0].data_width
);
689 if (pdimm
[0].n_ranks
!= 0) {
690 if (pdimm
[0].primary_sdram_width
== 64)
691 popts
->data_bus_width
= 0;
692 else if (pdimm
[0].primary_sdram_width
== 32)
693 popts
->data_bus_width
= 1;
694 else if (pdimm
[0].primary_sdram_width
== 16)
695 popts
->data_bus_width
= 2;
697 panic("Error: primary sdram width %u is invalid!\n",
698 pdimm
[0].primary_sdram_width
);
703 /* Choose burst length. */
704 #if defined(CONFIG_FSL_DDR3)
705 #if defined(CONFIG_E500MC)
706 popts
->OTF_burst_chop_en
= 0; /* on-the-fly burst chop disable */
707 popts
->burst_length
= DDR_BL8
; /* Fixed 8-beat burst len */
709 if ((popts
->data_bus_width
== 1) || (popts
->data_bus_width
== 2)) {
710 /* 32-bit or 16-bit bus */
711 popts
->OTF_burst_chop_en
= 0;
712 popts
->burst_length
= DDR_BL8
;
714 popts
->OTF_burst_chop_en
= 1; /* on-the-fly burst chop */
715 popts
->burst_length
= DDR_OTF
; /* on-the-fly BC4 and BL8 */
719 popts
->burst_length
= DDR_BL4
; /* has to be 4 for DDR2 */
722 /* Choose ddr controller address mirror mode */
723 #if defined(CONFIG_FSL_DDR3)
724 popts
->mirrored_dimm
= pdimm
[0].mirrored_dimm
;
727 /* Global Timing Parameters. */
728 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
730 /* Pick a caslat override. */
731 popts
->cas_latency_override
= 0;
732 popts
->cas_latency_override_value
= 3;
733 if (popts
->cas_latency_override
) {
734 debug("using caslat override value = %u\n",
735 popts
->cas_latency_override_value
);
738 /* Decide whether to use the computed derated latency */
739 popts
->use_derated_caslat
= 0;
741 /* Choose an additive latency. */
742 popts
->additive_latency_override
= 0;
743 popts
->additive_latency_override_value
= 3;
744 if (popts
->additive_latency_override
) {
745 debug("using additive latency override value = %u\n",
746 popts
->additive_latency_override_value
);
752 * Factors to consider for 2T_EN:
753 * - number of DIMMs installed
754 * - number of components, number of active ranks
755 * - how much time you want to spend playing around
758 popts
->threeT_en
= 0;
760 /* for RDIMM, address parity enable */
764 * BSTTOPRE precharge interval
766 * Set this to 0 for global auto precharge
768 * FIXME: Should this be configured in picoseconds?
769 * Why it should be in ps: better understanding of this
770 * relative to actual DRAM timing parameters such as tRAS.
771 * e.g. tRAS(min) = 40 ns
773 popts
->bstopre
= 0x100;
775 /* Minimum CKE pulse width -- tCKE(MIN) */
776 popts
->tCKE_clock_pulse_width_ps
777 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR
);
780 * Window for four activates -- tFAW
782 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
783 * FIXME: varies depending upon number of column addresses or data
784 * FIXME: width, was considering looking at pdimm->primary_sdram_width
786 #if defined(CONFIG_FSL_DDR1)
787 popts
->tFAW_window_four_activates_ps
= mclk_to_picos(1);
789 #elif defined(CONFIG_FSL_DDR2)
791 * x4/x8; some datasheets have 35000
792 * x16 wide columns only? Use 50000?
794 popts
->tFAW_window_four_activates_ps
= 37500;
796 #elif defined(CONFIG_FSL_DDR3)
797 popts
->tFAW_window_four_activates_ps
= pdimm
[0].tFAW_ps
;
801 #if defined(CONFIG_FSL_DDR3)
803 * due to ddr3 dimm is fly-by topology
804 * we suggest to enable write leveling to
805 * meet the tQDSS under different loading.
809 popts
->wrlvl_override
= 0;
813 * Check interleaving configuration from environment.
814 * Please refer to doc/README.fsl-ddr for the detail.
816 * If memory controller interleaving is enabled, then the data
817 * bus widths must be programmed identically for all memory controllers.
819 * XXX: Attempt to set all controllers to the same chip select
820 * interleaving mode. It will do a best effort to get the
821 * requested ranks interleaved together such that the result
822 * should be a subset of the requested configuration.
824 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
825 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf
))
828 if (pdimm
[0].n_ranks
== 0) {
829 printf("There is no rank on CS0 for controller %d.\n", ctrl_num
);
830 popts
->memctl_interleaving
= 0;
833 popts
->memctl_interleaving
= 1;
835 * test null first. if CONFIG_HWCONFIG is not defined
836 * hwconfig_arg_cmp returns non-zero
838 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
840 popts
->memctl_interleaving
= 0;
841 debug("memory controller interleaving disabled.\n");
842 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
845 popts
->memctl_interleaving_mode
=
846 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
847 0 : FSL_DDR_CACHE_LINE_INTERLEAVING
;
848 popts
->memctl_interleaving
=
849 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
851 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
854 popts
->memctl_interleaving_mode
=
855 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
856 0 : FSL_DDR_PAGE_INTERLEAVING
;
857 popts
->memctl_interleaving
=
858 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
860 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
863 popts
->memctl_interleaving_mode
=
864 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
865 0 : FSL_DDR_BANK_INTERLEAVING
;
866 popts
->memctl_interleaving
=
867 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
869 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
872 popts
->memctl_interleaving_mode
=
873 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
874 0 : FSL_DDR_SUPERBANK_INTERLEAVING
;
875 popts
->memctl_interleaving
=
876 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
878 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
879 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
882 popts
->memctl_interleaving_mode
=
883 FSL_DDR_3WAY_1KB_INTERLEAVING
;
884 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
887 popts
->memctl_interleaving_mode
=
888 FSL_DDR_3WAY_4KB_INTERLEAVING
;
889 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
892 popts
->memctl_interleaving_mode
=
893 FSL_DDR_3WAY_8KB_INTERLEAVING
;
894 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
895 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
898 popts
->memctl_interleaving_mode
=
899 FSL_DDR_4WAY_1KB_INTERLEAVING
;
900 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
903 popts
->memctl_interleaving_mode
=
904 FSL_DDR_4WAY_4KB_INTERLEAVING
;
905 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
908 popts
->memctl_interleaving_mode
=
909 FSL_DDR_4WAY_8KB_INTERLEAVING
;
912 popts
->memctl_interleaving
= 0;
913 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
917 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf
)) &&
918 (CONFIG_CHIP_SELECTS_PER_CTRL
> 1)) {
919 /* test null first. if CONFIG_HWCONFIG is not defined,
920 * hwconfig_subarg_cmp_f returns non-zero */
921 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
923 debug("bank interleaving disabled.\n");
924 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
926 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1
;
927 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
929 popts
->ba_intlv_ctl
= FSL_DDR_CS2_CS3
;
930 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
931 "cs0_cs1_and_cs2_cs3", buf
))
932 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_AND_CS2_CS3
;
933 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
934 "cs0_cs1_cs2_cs3", buf
))
935 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_CS2_CS3
;
936 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
938 popts
->ba_intlv_ctl
= auto_bank_intlv(pdimm
);
940 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
941 switch (popts
->ba_intlv_ctl
& FSL_DDR_CS0_CS1_CS2_CS3
) {
942 case FSL_DDR_CS0_CS1_CS2_CS3
:
943 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
944 if (pdimm
[0].n_ranks
< 4) {
945 popts
->ba_intlv_ctl
= 0;
946 printf("Not enough bank(chip-select) for "
947 "CS0+CS1+CS2+CS3 on controller %d, "
948 "interleaving disabled!\n", ctrl_num
);
950 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
951 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
952 if (pdimm
[0].n_ranks
== 4)
955 if ((pdimm
[0].n_ranks
< 2) && (pdimm
[1].n_ranks
< 2)) {
956 popts
->ba_intlv_ctl
= 0;
957 printf("Not enough bank(chip-select) for "
958 "CS0+CS1+CS2+CS3 on controller %d, "
959 "interleaving disabled!\n", ctrl_num
);
961 if (pdimm
[0].capacity
!= pdimm
[1].capacity
) {
962 popts
->ba_intlv_ctl
= 0;
963 printf("Not identical DIMM size for "
964 "CS0+CS1+CS2+CS3 on controller %d, "
965 "interleaving disabled!\n", ctrl_num
);
969 case FSL_DDR_CS0_CS1
:
970 if (pdimm
[0].n_ranks
< 2) {
971 popts
->ba_intlv_ctl
= 0;
972 printf("Not enough bank(chip-select) for "
973 "CS0+CS1 on controller %d, "
974 "interleaving disabled!\n", ctrl_num
);
977 case FSL_DDR_CS2_CS3
:
978 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
979 if (pdimm
[0].n_ranks
< 4) {
980 popts
->ba_intlv_ctl
= 0;
981 printf("Not enough bank(chip-select) for CS2+CS3 "
982 "on controller %d, interleaving disabled!\n", ctrl_num
);
984 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
985 if (pdimm
[1].n_ranks
< 2) {
986 popts
->ba_intlv_ctl
= 0;
987 printf("Not enough bank(chip-select) for CS2+CS3 "
988 "on controller %d, interleaving disabled!\n", ctrl_num
);
992 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
993 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
994 if (pdimm
[0].n_ranks
< 4) {
995 popts
->ba_intlv_ctl
= 0;
996 printf("Not enough bank(CS) for CS0+CS1 and "
997 "CS2+CS3 on controller %d, "
998 "interleaving disabled!\n", ctrl_num
);
1000 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1001 if ((pdimm
[0].n_ranks
< 2) || (pdimm
[1].n_ranks
< 2)) {
1002 popts
->ba_intlv_ctl
= 0;
1003 printf("Not enough bank(CS) for CS0+CS1 and "
1004 "CS2+CS3 on controller %d, "
1005 "interleaving disabled!\n", ctrl_num
);
1010 popts
->ba_intlv_ctl
= 0;
1015 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf
)) {
1016 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf
))
1017 popts
->addr_hash
= 0;
1018 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1020 popts
->addr_hash
= 1;
1023 if (pdimm
[0].n_ranks
== 4)
1024 popts
->quad_rank_present
= 1;
1026 ddr_freq
= get_ddr_freq(0) / 1000000;
1027 if (popts
->registered_dimm_en
) {
1028 popts
->rcw_override
= 1;
1029 popts
->rcw_1
= 0x000a5a00;
1030 if (ddr_freq
<= 800)
1031 popts
->rcw_2
= 0x00000000;
1032 else if (ddr_freq
<= 1066)
1033 popts
->rcw_2
= 0x00100000;
1034 else if (ddr_freq
<= 1333)
1035 popts
->rcw_2
= 0x00200000;
1037 popts
->rcw_2
= 0x00300000;
1040 fsl_ddr_board_options(popts
, pdimm
, ctrl_num
);
1045 void check_interleaving_options(fsl_ddr_info_t
*pinfo
)
1047 int i
, j
, k
, check_n_ranks
, intlv_invalid
= 0;
1048 unsigned int check_intlv
, check_n_row_addr
, check_n_col_addr
;
1049 unsigned long long check_rank_density
;
1050 struct dimm_params_s
*dimm
;
1052 * Check if all controllers are configured for memory
1053 * controller interleaving. Identical dimms are recommended. At least
1054 * the size, row and col address should be checked.
1057 check_n_ranks
= pinfo
->dimm_params
[0][0].n_ranks
;
1058 check_rank_density
= pinfo
->dimm_params
[0][0].rank_density
;
1059 check_n_row_addr
= pinfo
->dimm_params
[0][0].n_row_addr
;
1060 check_n_col_addr
= pinfo
->dimm_params
[0][0].n_col_addr
;
1061 check_intlv
= pinfo
->memctl_opts
[0].memctl_interleaving_mode
;
1062 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
1063 dimm
= &pinfo
->dimm_params
[i
][0];
1064 if (!pinfo
->memctl_opts
[i
].memctl_interleaving
) {
1066 } else if (((check_rank_density
!= dimm
->rank_density
) ||
1067 (check_n_ranks
!= dimm
->n_ranks
) ||
1068 (check_n_row_addr
!= dimm
->n_row_addr
) ||
1069 (check_n_col_addr
!= dimm
->n_col_addr
) ||
1071 pinfo
->memctl_opts
[i
].memctl_interleaving_mode
))){
1079 if (intlv_invalid
) {
1080 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++)
1081 pinfo
->memctl_opts
[i
].memctl_interleaving
= 0;
1082 printf("Not all DIMMs are identical. "
1083 "Memory controller interleaving disabled.\n");
1085 switch (check_intlv
) {
1086 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
1087 case FSL_DDR_PAGE_INTERLEAVING
:
1088 case FSL_DDR_BANK_INTERLEAVING
:
1089 case FSL_DDR_SUPERBANK_INTERLEAVING
:
1090 if (3 == CONFIG_NUM_DDR_CONTROLLERS
)
1093 k
= CONFIG_NUM_DDR_CONTROLLERS
;
1095 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
1096 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
1097 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
1098 case FSL_DDR_4WAY_1KB_INTERLEAVING
:
1099 case FSL_DDR_4WAY_4KB_INTERLEAVING
:
1100 case FSL_DDR_4WAY_8KB_INTERLEAVING
:
1102 k
= CONFIG_NUM_DDR_CONTROLLERS
;
1105 debug("%d of %d controllers are interleaving.\n", j
, k
);
1106 if (j
&& (j
!= k
)) {
1107 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++)
1108 pinfo
->memctl_opts
[i
].memctl_interleaving
= 0;
1109 printf("Not all controllers have compatible "
1110 "interleaving mode. All disabled.\n");
1113 debug("Checking interleaving options completed\n");
1116 int fsl_use_spd(void)
1120 #ifdef CONFIG_DDR_SPD
1121 char buffer
[HWCONFIG_BUFFER_SIZE
];
1125 * Extract hwconfig from environment since we have not properly setup
1126 * the environment but need it for ddr config params
1128 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
1131 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1132 if (hwconfig_sub_f("fsl_ddr", "sdram", buf
)) {
1133 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf
))
1135 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",