arch/powerpc/cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <hwconfig.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14 #include "ddr.h"
  15
  16 /*
  17  * Use our own stack based buffer before relocation to allow accessing longer
  18  * hwconfig strings that might be in the environment before we've relocated.
  19  * This is pretty fragile on both the use of stack and if the buffer is big
  20  * enough. However we will get a warning from getenv_f for the later.
  21  */
  22 #define HWCONFIG_BUFFER_SIZE    128
  23
  24 /* Board-specific functions defined in each board's ddr.c */
  25 extern void fsl_ddr_board_options(memctl_options_t *popts,
  26                 dimm_params_t *pdimm,
  27                 unsigned int ctrl_num);
  28
  29 struct dynamic_odt {
  30         unsigned int odt_rd_cfg;
  31         unsigned int odt_wr_cfg;
  32         unsigned int odt_rtt_norm;
  33         unsigned int odt_rtt_wr;
  34 };
  35
  36 #ifdef CONFIG_FSL_DDR3
  37 static const struct dynamic_odt single_Q[4] = {
  38         {       /* cs0 */
  39                 FSL_DDR_ODT_NEVER,
  40                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  41                 DDR3_RTT_20_OHM,
  42                 DDR3_RTT_120_OHM
  43         },
  44         {       /* cs1 */
  45                 FSL_DDR_ODT_NEVER,
  46                 FSL_DDR_ODT_NEVER,      /* tied high */
  47                 DDR3_RTT_OFF,
  48                 DDR3_RTT_120_OHM
  49         },
  50         {       /* cs2 */
  51                 FSL_DDR_ODT_NEVER,
  52                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  53                 DDR3_RTT_20_OHM,
  54                 DDR3_RTT_120_OHM
  55         },
  56         {       /* cs3 */
  57                 FSL_DDR_ODT_NEVER,
  58                 FSL_DDR_ODT_NEVER,      /* tied high */
  59                 DDR3_RTT_OFF,
  60                 DDR3_RTT_120_OHM
  61         }
  62 };
  63
  64 static const struct dynamic_odt single_D[4] = {
  65         {       /* cs0 */
  66                 FSL_DDR_ODT_NEVER,
  67                 FSL_DDR_ODT_ALL,
  68                 DDR3_RTT_40_OHM,
  69                 DDR3_RTT_OFF
  70         },
  71         {       /* cs1 */
  72                 FSL_DDR_ODT_NEVER,
  73                 FSL_DDR_ODT_NEVER,
  74                 DDR3_RTT_OFF,
  75                 DDR3_RTT_OFF
  76         },
  77         {0, 0, 0, 0},
  78         {0, 0, 0, 0}
  79 };
  80
  81 static const struct dynamic_odt single_S[4] = {
  82         {       /* cs0 */
  83                 FSL_DDR_ODT_NEVER,
  84                 FSL_DDR_ODT_ALL,
  85                 DDR3_RTT_40_OHM,
  86                 DDR3_RTT_OFF
  87         },
  88         {0, 0, 0, 0},
  89         {0, 0, 0, 0},
  90         {0, 0, 0, 0},
  91 };
  92
  93 static const struct dynamic_odt dual_DD[4] = {
  94         {       /* cs0 */
  95                 FSL_DDR_ODT_NEVER,
  96                 FSL_DDR_ODT_SAME_DIMM,
  97                 DDR3_RTT_120_OHM,
  98                 DDR3_RTT_OFF
  99         },
 100         {       /* cs1 */
 101                 FSL_DDR_ODT_OTHER_DIMM,
 102                 FSL_DDR_ODT_OTHER_DIMM,
 103                 DDR3_RTT_30_OHM,
 104                 DDR3_RTT_OFF
 105         },
 106         {       /* cs2 */
 107                 FSL_DDR_ODT_NEVER,
 108                 FSL_DDR_ODT_SAME_DIMM,
 109                 DDR3_RTT_120_OHM,
 110                 DDR3_RTT_OFF
 111         },
 112         {       /* cs3 */
 113                 FSL_DDR_ODT_OTHER_DIMM,
 114                 FSL_DDR_ODT_OTHER_DIMM,
 115                 DDR3_RTT_30_OHM,
 116                 DDR3_RTT_OFF
 117         }
 118 };
 119
 120 static const struct dynamic_odt dual_DS[4] = {
 121         {       /* cs0 */
 122                 FSL_DDR_ODT_NEVER,
 123                 FSL_DDR_ODT_SAME_DIMM,
 124                 DDR3_RTT_120_OHM,
 125                 DDR3_RTT_OFF
 126         },
 127         {       /* cs1 */
 128                 FSL_DDR_ODT_OTHER_DIMM,
 129                 FSL_DDR_ODT_OTHER_DIMM,
 130                 DDR3_RTT_30_OHM,
 131                 DDR3_RTT_OFF
 132         },
 133         {       /* cs2 */
 134                 FSL_DDR_ODT_OTHER_DIMM,
 135                 FSL_DDR_ODT_ALL,
 136                 DDR3_RTT_20_OHM,
 137                 DDR3_RTT_120_OHM
 138         },
 139         {0, 0, 0, 0}
 140 };
 141 static const struct dynamic_odt dual_SD[4] = {
 142         {       /* cs0 */
 143                 FSL_DDR_ODT_OTHER_DIMM,
 144                 FSL_DDR_ODT_ALL,
 145                 DDR3_RTT_20_OHM,
 146                 DDR3_RTT_120_OHM
 147         },
 148         {0, 0, 0, 0},
 149         {       /* cs2 */
 150                 FSL_DDR_ODT_NEVER,
 151                 FSL_DDR_ODT_SAME_DIMM,
 152                 DDR3_RTT_120_OHM,
 153                 DDR3_RTT_OFF
 154         },
 155         {       /* cs3 */
 156                 FSL_DDR_ODT_OTHER_DIMM,
 157                 FSL_DDR_ODT_OTHER_DIMM,
 158                 DDR3_RTT_20_OHM,
 159                 DDR3_RTT_OFF
 160         }
 161 };
 162
 163 static const struct dynamic_odt dual_SS[4] = {
 164         {       /* cs0 */
 165                 FSL_DDR_ODT_OTHER_DIMM,
 166                 FSL_DDR_ODT_ALL,
 167                 DDR3_RTT_30_OHM,
 168                 DDR3_RTT_120_OHM
 169         },
 170         {0, 0, 0, 0},
 171         {       /* cs2 */
 172                 FSL_DDR_ODT_OTHER_DIMM,
 173                 FSL_DDR_ODT_ALL,
 174                 DDR3_RTT_30_OHM,
 175                 DDR3_RTT_120_OHM
 176         },
 177         {0, 0, 0, 0}
 178 };
 179
 180 static const struct dynamic_odt dual_D0[4] = {
 181         {       /* cs0 */
 182                 FSL_DDR_ODT_NEVER,
 183                 FSL_DDR_ODT_SAME_DIMM,
 184                 DDR3_RTT_40_OHM,
 185                 DDR3_RTT_OFF
 186         },
 187         {       /* cs1 */
 188                 FSL_DDR_ODT_NEVER,
 189                 FSL_DDR_ODT_NEVER,
 190                 DDR3_RTT_OFF,
 191                 DDR3_RTT_OFF
 192         },
 193         {0, 0, 0, 0},
 194         {0, 0, 0, 0}
 195 };
 196
 197 static const struct dynamic_odt dual_0D[4] = {
 198         {0, 0, 0, 0},
 199         {0, 0, 0, 0},
 200         {       /* cs2 */
 201                 FSL_DDR_ODT_NEVER,
 202                 FSL_DDR_ODT_SAME_DIMM,
 203                 DDR3_RTT_40_OHM,
 204                 DDR3_RTT_OFF
 205         },
 206         {       /* cs3 */
 207                 FSL_DDR_ODT_NEVER,
 208                 FSL_DDR_ODT_NEVER,
 209                 DDR3_RTT_OFF,
 210                 DDR3_RTT_OFF
 211         }
 212 };
 213
 214 static const struct dynamic_odt dual_S0[4] = {
 215         {       /* cs0 */
 216                 FSL_DDR_ODT_NEVER,
 217                 FSL_DDR_ODT_CS,
 218                 DDR3_RTT_40_OHM,
 219                 DDR3_RTT_OFF
 220         },
 221         {0, 0, 0, 0},
 222         {0, 0, 0, 0},
 223         {0, 0, 0, 0}
 224
 225 };
 226
 227 static const struct dynamic_odt dual_0S[4] = {
 228         {0, 0, 0, 0},
 229         {0, 0, 0, 0},
 230         {       /* cs2 */
 231                 FSL_DDR_ODT_NEVER,
 232                 FSL_DDR_ODT_CS,
 233                 DDR3_RTT_40_OHM,
 234                 DDR3_RTT_OFF
 235         },
 236         {0, 0, 0, 0}
 237
 238 };
 239
 240 static const struct dynamic_odt odt_unknown[4] = {
 241         {       /* cs0 */
 242                 FSL_DDR_ODT_NEVER,
 243                 FSL_DDR_ODT_CS,
 244                 DDR3_RTT_120_OHM,
 245                 DDR3_RTT_OFF
 246         },
 247         {       /* cs1 */
 248                 FSL_DDR_ODT_NEVER,
 249                 FSL_DDR_ODT_CS,
 250                 DDR3_RTT_120_OHM,
 251                 DDR3_RTT_OFF
 252         },
 253         {       /* cs2 */
 254                 FSL_DDR_ODT_NEVER,
 255                 FSL_DDR_ODT_CS,
 256                 DDR3_RTT_120_OHM,
 257                 DDR3_RTT_OFF
 258         },
 259         {       /* cs3 */
 260                 FSL_DDR_ODT_NEVER,
 261                 FSL_DDR_ODT_CS,
 262                 DDR3_RTT_120_OHM,
 263                 DDR3_RTT_OFF
 264         }
 265 };
 266 #else   /* CONFIG_FSL_DDR3 */
 267 static const struct dynamic_odt single_Q[4] = {
 268         {0, 0, 0, 0},
 269         {0, 0, 0, 0},
 270         {0, 0, 0, 0},
 271         {0, 0, 0, 0}
 272 };
 273
 274 static const struct dynamic_odt single_D[4] = {
 275         {       /* cs0 */
 276                 FSL_DDR_ODT_NEVER,
 277                 FSL_DDR_ODT_ALL,
 278                 DDR2_RTT_150_OHM,
 279                 DDR2_RTT_OFF
 280         },
 281         {       /* cs1 */
 282                 FSL_DDR_ODT_NEVER,
 283                 FSL_DDR_ODT_NEVER,
 284                 DDR2_RTT_OFF,
 285                 DDR2_RTT_OFF
 286         },
 287         {0, 0, 0, 0},
 288         {0, 0, 0, 0}
 289 };
 290
 291 static const struct dynamic_odt single_S[4] = {
 292         {       /* cs0 */
 293                 FSL_DDR_ODT_NEVER,
 294                 FSL_DDR_ODT_ALL,
 295                 DDR2_RTT_150_OHM,
 296                 DDR2_RTT_OFF
 297         },
 298         {0, 0, 0, 0},
 299         {0, 0, 0, 0},
 300         {0, 0, 0, 0},
 301 };
 302
 303 static const struct dynamic_odt dual_DD[4] = {
 304         {       /* cs0 */
 305                 FSL_DDR_ODT_OTHER_DIMM,
 306                 FSL_DDR_ODT_OTHER_DIMM,
 307                 DDR2_RTT_75_OHM,
 308                 DDR2_RTT_OFF
 309         },
 310         {       /* cs1 */
 311                 FSL_DDR_ODT_NEVER,
 312                 FSL_DDR_ODT_NEVER,
 313                 DDR2_RTT_OFF,
 314                 DDR2_RTT_OFF
 315         },
 316         {       /* cs2 */
 317                 FSL_DDR_ODT_OTHER_DIMM,
 318                 FSL_DDR_ODT_OTHER_DIMM,
 319                 DDR2_RTT_75_OHM,
 320                 DDR2_RTT_OFF
 321         },
 322         {       /* cs3 */
 323                 FSL_DDR_ODT_NEVER,
 324                 FSL_DDR_ODT_NEVER,
 325                 DDR2_RTT_OFF,
 326                 DDR2_RTT_OFF
 327         }
 328 };
 329
 330 static const struct dynamic_odt dual_DS[4] = {
 331         {       /* cs0 */
 332                 FSL_DDR_ODT_OTHER_DIMM,
 333                 FSL_DDR_ODT_OTHER_DIMM,
 334                 DDR2_RTT_75_OHM,
 335                 DDR2_RTT_OFF
 336         },
 337         {       /* cs1 */
 338                 FSL_DDR_ODT_NEVER,
 339                 FSL_DDR_ODT_NEVER,
 340                 DDR2_RTT_OFF,
 341                 DDR2_RTT_OFF
 342         },
 343         {       /* cs2 */
 344                 FSL_DDR_ODT_OTHER_DIMM,
 345                 FSL_DDR_ODT_OTHER_DIMM,
 346                 DDR2_RTT_75_OHM,
 347                 DDR2_RTT_OFF
 348         },
 349         {0, 0, 0, 0}
 350 };
 351
 352 static const struct dynamic_odt dual_SD[4] = {
 353         {       /* cs0 */
 354                 FSL_DDR_ODT_OTHER_DIMM,
 355                 FSL_DDR_ODT_OTHER_DIMM,
 356                 DDR2_RTT_75_OHM,
 357                 DDR2_RTT_OFF
 358         },
 359         {0, 0, 0, 0},
 360         {       /* cs2 */
 361                 FSL_DDR_ODT_OTHER_DIMM,
 362                 FSL_DDR_ODT_OTHER_DIMM,
 363                 DDR2_RTT_75_OHM,
 364                 DDR2_RTT_OFF
 365         },
 366         {       /* cs3 */
 367                 FSL_DDR_ODT_NEVER,
 368                 FSL_DDR_ODT_NEVER,
 369                 DDR2_RTT_OFF,
 370                 DDR2_RTT_OFF
 371         }
 372 };
 373
 374 static const struct dynamic_odt dual_SS[4] = {
 375         {       /* cs0 */
 376                 FSL_DDR_ODT_OTHER_DIMM,
 377                 FSL_DDR_ODT_OTHER_DIMM,
 378                 DDR2_RTT_75_OHM,
 379                 DDR2_RTT_OFF
 380         },
 381         {0, 0, 0, 0},
 382         {       /* cs2 */
 383                 FSL_DDR_ODT_OTHER_DIMM,
 384                 FSL_DDR_ODT_OTHER_DIMM,
 385                 DDR2_RTT_75_OHM,
 386                 DDR2_RTT_OFF
 387         },
 388         {0, 0, 0, 0}
 389 };
 390
 391 static const struct dynamic_odt dual_D0[4] = {
 392         {       /* cs0 */
 393                 FSL_DDR_ODT_NEVER,
 394                 FSL_DDR_ODT_ALL,
 395                 DDR2_RTT_150_OHM,
 396                 DDR2_RTT_OFF
 397         },
 398         {       /* cs1 */
 399                 FSL_DDR_ODT_NEVER,
 400                 FSL_DDR_ODT_NEVER,
 401                 DDR2_RTT_OFF,
 402                 DDR2_RTT_OFF
 403         },
 404         {0, 0, 0, 0},
 405         {0, 0, 0, 0}
 406 };
 407
 408 static const struct dynamic_odt dual_0D[4] = {
 409         {0, 0, 0, 0},
 410         {0, 0, 0, 0},
 411         {       /* cs2 */
 412                 FSL_DDR_ODT_NEVER,
 413                 FSL_DDR_ODT_ALL,
 414                 DDR2_RTT_150_OHM,
 415                 DDR2_RTT_OFF
 416         },
 417         {       /* cs3 */
 418                 FSL_DDR_ODT_NEVER,
 419                 FSL_DDR_ODT_NEVER,
 420                 DDR2_RTT_OFF,
 421                 DDR2_RTT_OFF
 422         }
 423 };
 424
 425 static const struct dynamic_odt dual_S0[4] = {
 426         {       /* cs0 */
 427                 FSL_DDR_ODT_NEVER,
 428                 FSL_DDR_ODT_CS,
 429                 DDR2_RTT_150_OHM,
 430                 DDR2_RTT_OFF
 431         },
 432         {0, 0, 0, 0},
 433         {0, 0, 0, 0},
 434         {0, 0, 0, 0}
 435
 436 };
 437
 438 static const struct dynamic_odt dual_0S[4] = {
 439         {0, 0, 0, 0},
 440         {0, 0, 0, 0},
 441         {       /* cs2 */
 442                 FSL_DDR_ODT_NEVER,
 443                 FSL_DDR_ODT_CS,
 444                 DDR2_RTT_150_OHM,
 445                 DDR2_RTT_OFF
 446         },
 447         {0, 0, 0, 0}
 448
 449 };
 450
 451 static const struct dynamic_odt odt_unknown[4] = {
 452         {       /* cs0 */
 453                 FSL_DDR_ODT_NEVER,
 454                 FSL_DDR_ODT_CS,
 455                 DDR2_RTT_75_OHM,
 456                 DDR2_RTT_OFF
 457         },
 458         {       /* cs1 */
 459                 FSL_DDR_ODT_NEVER,
 460                 FSL_DDR_ODT_NEVER,
 461                 DDR2_RTT_OFF,
 462                 DDR2_RTT_OFF
 463         },
 464         {       /* cs2 */
 465                 FSL_DDR_ODT_NEVER,
 466                 FSL_DDR_ODT_CS,
 467                 DDR2_RTT_75_OHM,
 468                 DDR2_RTT_OFF
 469         },
 470         {       /* cs3 */
 471                 FSL_DDR_ODT_NEVER,
 472                 FSL_DDR_ODT_NEVER,
 473                 DDR2_RTT_OFF,
 474                 DDR2_RTT_OFF
 475         }
 476 };
 477 #endif
 478 unsigned int populate_memctl_options(int all_DIMMs_registered,
 479                         memctl_options_t *popts,
 480                         dimm_params_t *pdimm,
 481                         unsigned int ctrl_num)
 482 {
 483         unsigned int i;
 484         char buffer[HWCONFIG_BUFFER_SIZE];
 485         char *buf = NULL;
 486 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 487         const struct dynamic_odt *pdodt = odt_unknown;
 488 #endif
 489         ulong ddr_freq;
 490
 491         /*
 492          * Extract hwconfig from environment since we have not properly setup
 493          * the environment but need it for ddr config params
 494          */
 495         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 496                 buf = buffer;
 497
 498 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 499         /* Chip select options. */
 500         if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 501                 switch (pdimm[0].n_ranks) {
 502                 case 1:
 503                         pdodt = single_S;
 504                         break;
 505                 case 2:
 506                         pdodt = single_D;
 507                         break;
 508                 case 4:
 509                         pdodt = single_Q;
 510                         break;
 511                 }
 512         } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 513                 switch (pdimm[0].n_ranks) {
 514                 case 2:
 515                         switch (pdimm[1].n_ranks) {
 516                         case 2:
 517                                 pdodt = dual_DD;
 518                                 break;
 519                         case 1:
 520                                 pdodt = dual_DS;
 521                                 break;
 522                         case 0:
 523                                 pdodt = dual_D0;
 524                                 break;
 525                         }
 526                         break;
 527                 case 1:
 528                         switch (pdimm[1].n_ranks) {
 529                         case 2:
 530                                 pdodt = dual_SD;
 531                                 break;
 532                         case 1:
 533                                 pdodt = dual_SS;
 534                                 break;
 535                         case 0:
 536                                 pdodt = dual_S0;
 537                                 break;
 538                         }
 539                         break;
 540                 case 0:
 541                         switch (pdimm[1].n_ranks) {
 542                         case 2:
 543                                 pdodt = dual_0D;
 544                                 break;
 545                         case 1:
 546                                 pdodt = dual_0S;
 547                                 break;
 548                         }
 549                         break;
 550                 }
 551         }
 552 #endif
 553
 554         /* Pick chip-select local options. */
 555         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 556 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 557                 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
 558                 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
 559                 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
 560                 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
 561 #else
 562                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 563                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 564 #endif
 565                 popts->cs_local_opts[i].auto_precharge = 0;
 566         }
 567
 568         /* Pick interleaving mode. */
 569
 570         /*
 571          * 0 = no interleaving
 572          * 1 = interleaving between 2 controllers
 573          */
 574         popts->memctl_interleaving = 0;
 575
 576         /*
 577          * 0 = cacheline
 578          * 1 = page
 579          * 2 = (logical) bank
 580          * 3 = superbank (only if CS interleaving is enabled)
 581          */
 582         popts->memctl_interleaving_mode = 0;
 583
 584         /*
 585          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
 586          * 1: page:      bit to the left of the column bits selects the memctl
 587          * 2: bank:      bit to the left of the bank bits selects the memctl
 588          * 3: superbank: bit to the left of the chip select selects the memctl
 589          *
 590          * NOTE: ba_intlv (rank interleaving) is independent of memory
 591          * controller interleaving; it is only within a memory controller.
 592          * Must use superbank interleaving if rank interleaving is used and
 593          * memory controller interleaving is enabled.
 594          */
 595
 596         /*
 597          * 0 = no
 598          * 0x40 = CS0,CS1
 599          * 0x20 = CS2,CS3
 600          * 0x60 = CS0,CS1 + CS2,CS3
 601          * 0x04 = CS0,CS1,CS2,CS3
 602          */
 603         popts->ba_intlv_ctl = 0;
 604
 605         /* Memory Organization Parameters */
 606         popts->registered_dimm_en = all_DIMMs_registered;
 607
 608         /* Operational Mode Paramters */
 609
 610         /* Pick ECC modes */
 611         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
 612 #ifdef CONFIG_DDR_ECC
 613         if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 614                 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
 615                         popts->ECC_mode = 1;
 616         } else
 617                 popts->ECC_mode = 1;
 618 #endif
 619         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 620
 621         /*
 622          * Choose DQS config
 623          * 0 for DDR1
 624          * 1 for DDR2
 625          */
 626 #if defined(CONFIG_FSL_DDR1)
 627         popts->DQS_config = 0;
 628 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
 629         popts->DQS_config = 1;
 630 #endif
 631
 632         /* Choose self-refresh during sleep. */
 633         popts->self_refresh_in_sleep = 1;
 634
 635         /* Choose dynamic power management mode. */
 636         popts->dynamic_power = 0;
 637
 638         /*
 639          * check first dimm for primary sdram width
 640          * presuming all dimms are similar
 641          * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
 642          */
 643 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
 644         if (pdimm[0].n_ranks != 0) {
 645                 if ((pdimm[0].data_width >= 64) && \
 646                         (pdimm[0].data_width <= 72))
 647                         popts->data_bus_width = 0;
 648                 else if ((pdimm[0].data_width >= 32) || \
 649                         (pdimm[0].data_width <= 40))
 650                         popts->data_bus_width = 1;
 651                 else {
 652                         panic("Error: data width %u is invalid!\n",
 653                                 pdimm[0].data_width);
 654                 }
 655         }
 656 #else
 657         if (pdimm[0].n_ranks != 0) {
 658                 if (pdimm[0].primary_sdram_width == 64)
 659                         popts->data_bus_width = 0;
 660                 else if (pdimm[0].primary_sdram_width == 32)
 661                         popts->data_bus_width = 1;
 662                 else if (pdimm[0].primary_sdram_width == 16)
 663                         popts->data_bus_width = 2;
 664                 else {
 665                         panic("Error: primary sdram width %u is invalid!\n",
 666                                 pdimm[0].primary_sdram_width);
 667                 }
 668         }
 669 #endif
 670
 671         /* Choose burst length. */
 672 #if defined(CONFIG_FSL_DDR3)
 673 #if defined(CONFIG_E500MC)
 674         popts->OTF_burst_chop_en = 0;   /* on-the-fly burst chop disable */
 675         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
 676 #else
 677         if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
 678                 /* 32-bit or 16-bit bus */
 679                 popts->OTF_burst_chop_en = 0;
 680                 popts->burst_length = DDR_BL8;
 681         } else {
 682                 popts->OTF_burst_chop_en = 1;   /* on-the-fly burst chop */
 683                 popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 684         }
 685 #endif
 686 #else
 687         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 688 #endif
 689
 690         /* Choose ddr controller address mirror mode */
 691 #if defined(CONFIG_FSL_DDR3)
 692         popts->mirrored_dimm = pdimm[0].mirrored_dimm;
 693 #endif
 694
 695         /* Global Timing Parameters. */
 696         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 697
 698         /* Pick a caslat override. */
 699         popts->cas_latency_override = 0;
 700         popts->cas_latency_override_value = 3;
 701         if (popts->cas_latency_override) {
 702                 debug("using caslat override value = %u\n",
 703                        popts->cas_latency_override_value);
 704         }
 705
 706         /* Decide whether to use the computed derated latency */
 707         popts->use_derated_caslat = 0;
 708
 709         /* Choose an additive latency. */
 710         popts->additive_latency_override = 0;
 711         popts->additive_latency_override_value = 3;
 712         if (popts->additive_latency_override) {
 713                 debug("using additive latency override value = %u\n",
 714                        popts->additive_latency_override_value);
 715         }
 716
 717         /*
 718          * 2T_EN setting
 719          *
 720          * Factors to consider for 2T_EN:
 721          *      - number of DIMMs installed
 722          *      - number of components, number of active ranks
 723          *      - how much time you want to spend playing around
 724          */
 725         popts->twoT_en = 0;
 726         popts->threeT_en = 0;
 727
 728         /* for RDIMM, address parity enable */
 729         popts->ap_en = 1;
 730
 731         /*
 732          * BSTTOPRE precharge interval
 733          *
 734          * Set this to 0 for global auto precharge
 735          *
 736          * FIXME: Should this be configured in picoseconds?
 737          * Why it should be in ps:  better understanding of this
 738          * relative to actual DRAM timing parameters such as tRAS.
 739          * e.g. tRAS(min) = 40 ns
 740          */
 741         popts->bstopre = 0x100;
 742
 743         /* Minimum CKE pulse width -- tCKE(MIN) */
 744         popts->tCKE_clock_pulse_width_ps
 745                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 746
 747         /*
 748          * Window for four activates -- tFAW
 749          *
 750          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 751          * FIXME: varies depending upon number of column addresses or data
 752          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 753          */
 754 #if defined(CONFIG_FSL_DDR1)
 755         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 756
 757 #elif defined(CONFIG_FSL_DDR2)
 758         /*
 759          * x4/x8;  some datasheets have 35000
 760          * x16 wide columns only?  Use 50000?
 761          */
 762         popts->tFAW_window_four_activates_ps = 37500;
 763
 764 #elif defined(CONFIG_FSL_DDR3)
 765         popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
 766 #endif
 767         popts->zq_en = 0;
 768         popts->wrlvl_en = 0;
 769 #if defined(CONFIG_FSL_DDR3)
 770         /*
 771          * due to ddr3 dimm is fly-by topology
 772          * we suggest to enable write leveling to
 773          * meet the tQDSS under different loading.
 774          */
 775         popts->wrlvl_en = 1;
 776         popts->zq_en = 1;
 777         popts->wrlvl_override = 0;
 778 #endif
 779
 780         /*
 781          * Check interleaving configuration from environment.
 782          * Please refer to doc/README.fsl-ddr for the detail.
 783          *
 784          * If memory controller interleaving is enabled, then the data
 785          * bus widths must be programmed identically for all memory controllers.
 786          *
 787          * XXX: Attempt to set all controllers to the same chip select
 788          * interleaving mode. It will do a best effort to get the
 789          * requested ranks interleaved together such that the result
 790          * should be a subset of the requested configuration.
 791          */
 792 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 793         if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
 794                 goto done;
 795
 796         if (pdimm[0].n_ranks == 0) {
 797                 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
 798                 popts->memctl_interleaving = 0;
 799                 goto done;
 800         }
 801         popts->memctl_interleaving = 1;
 802         /*
 803          * test null first. if CONFIG_HWCONFIG is not defined
 804          * hwconfig_arg_cmp returns non-zero
 805          */
 806         if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 807                                     "null", buf)) {
 808                 popts->memctl_interleaving = 0;
 809                 debug("memory controller interleaving disabled.\n");
 810         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 811                                         "ctlr_intlv",
 812                                         "cacheline", buf)) {
 813                 popts->memctl_interleaving_mode =
 814                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 815                         0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
 816                 popts->memctl_interleaving =
 817                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 818                         0 : 1;
 819         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 820                                         "ctlr_intlv",
 821                                         "page", buf)) {
 822                 popts->memctl_interleaving_mode =
 823                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 824                         0 : FSL_DDR_PAGE_INTERLEAVING;
 825                 popts->memctl_interleaving =
 826                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 827                         0 : 1;
 828         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 829                                         "ctlr_intlv",
 830                                         "bank", buf)) {
 831                 popts->memctl_interleaving_mode =
 832                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 833                         0 : FSL_DDR_BANK_INTERLEAVING;
 834                 popts->memctl_interleaving =
 835                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 836                         0 : 1;
 837         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 838                                         "ctlr_intlv",
 839                                         "superbank", buf)) {
 840                 popts->memctl_interleaving_mode =
 841                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 842                         0 : FSL_DDR_SUPERBANK_INTERLEAVING;
 843                 popts->memctl_interleaving =
 844                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 845                         0 : 1;
 846 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
 847         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 848                                         "ctlr_intlv",
 849                                         "3way_1KB", buf)) {
 850                 popts->memctl_interleaving_mode =
 851                         FSL_DDR_3WAY_1KB_INTERLEAVING;
 852         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 853                                         "ctlr_intlv",
 854                                         "3way_4KB", buf)) {
 855                 popts->memctl_interleaving_mode =
 856                         FSL_DDR_3WAY_4KB_INTERLEAVING;
 857         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 858                                         "ctlr_intlv",
 859                                         "3way_8KB", buf)) {
 860                 popts->memctl_interleaving_mode =
 861                         FSL_DDR_3WAY_8KB_INTERLEAVING;
 862 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
 863         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 864                                         "ctlr_intlv",
 865                                         "4way_1KB", buf)) {
 866                 popts->memctl_interleaving_mode =
 867                         FSL_DDR_4WAY_1KB_INTERLEAVING;
 868         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 869                                         "ctlr_intlv",
 870                                         "4way_4KB", buf)) {
 871                 popts->memctl_interleaving_mode =
 872                         FSL_DDR_4WAY_4KB_INTERLEAVING;
 873         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 874                                         "ctlr_intlv",
 875                                         "4way_8KB", buf)) {
 876                 popts->memctl_interleaving_mode =
 877                         FSL_DDR_4WAY_8KB_INTERLEAVING;
 878 #endif
 879         } else {
 880                 popts->memctl_interleaving = 0;
 881                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
 882         }
 883 done:
 884 #endif
 885         if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
 886                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 887                 /* test null first. if CONFIG_HWCONFIG is not defined,
 888                  * hwconfig_subarg_cmp_f returns non-zero */
 889                 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 890                                             "null", buf))
 891                         debug("bank interleaving disabled.\n");
 892                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 893                                                  "cs0_cs1", buf))
 894                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 895                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 896                                                  "cs2_cs3", buf))
 897                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 898                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 899                                                  "cs0_cs1_and_cs2_cs3", buf))
 900                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 901                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 902                                                  "cs0_cs1_cs2_cs3", buf))
 903                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 904                 else
 905                         printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 906                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 907                 case FSL_DDR_CS0_CS1_CS2_CS3:
 908 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 909                         if (pdimm[0].n_ranks < 4) {
 910                                 popts->ba_intlv_ctl = 0;
 911                                 printf("Not enough bank(chip-select) for "
 912                                         "CS0+CS1+CS2+CS3 on controller %d, "
 913                                         "interleaving disabled!\n", ctrl_num);
 914                         }
 915 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 916                         if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 917                                 popts->ba_intlv_ctl = 0;
 918                                 printf("Not enough bank(chip-select) for "
 919                                         "CS0+CS1+CS2+CS3 on controller %d, "
 920                                         "interleaving disabled!\n", ctrl_num);
 921                         }
 922                         if (pdimm[0].capacity != pdimm[1].capacity) {
 923                                 popts->ba_intlv_ctl = 0;
 924                                 printf("Not identical DIMM size for "
 925                                         "CS0+CS1+CS2+CS3 on controller %d, "
 926                                         "interleaving disabled!\n", ctrl_num);
 927                         }
 928 #endif
 929                         break;
 930                 case FSL_DDR_CS0_CS1:
 931                         if (pdimm[0].n_ranks < 2) {
 932                                 popts->ba_intlv_ctl = 0;
 933                                 printf("Not enough bank(chip-select) for "
 934                                         "CS0+CS1 on controller %d, "
 935                                         "interleaving disabled!\n", ctrl_num);
 936                         }
 937                         break;
 938                 case FSL_DDR_CS2_CS3:
 939 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 940                         if (pdimm[0].n_ranks < 4) {
 941                                 popts->ba_intlv_ctl = 0;
 942                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 943                                         "on controller %d, interleaving disabled!\n", ctrl_num);
 944                         }
 945 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 946                         if (pdimm[1].n_ranks < 2) {
 947                                 popts->ba_intlv_ctl = 0;
 948                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 949                                         "on controller %d, interleaving disabled!\n", ctrl_num);
 950                         }
 951 #endif
 952                         break;
 953                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 954 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 955                         if (pdimm[0].n_ranks < 4) {
 956                                 popts->ba_intlv_ctl = 0;
 957                                 printf("Not enough bank(CS) for CS0+CS1 and "
 958                                         "CS2+CS3 on controller %d, "
 959                                         "interleaving disabled!\n", ctrl_num);
 960                         }
 961 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 962                         if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
 963                                 popts->ba_intlv_ctl = 0;
 964                                 printf("Not enough bank(CS) for CS0+CS1 and "
 965                                         "CS2+CS3 on controller %d, "
 966                                         "interleaving disabled!\n", ctrl_num);
 967                         }
 968 #endif
 969                         break;
 970                 default:
 971                         popts->ba_intlv_ctl = 0;
 972                         break;
 973                 }
 974         }
 975
 976         if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
 977                 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
 978                         popts->addr_hash = 0;
 979                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
 980                                                "true", buf))
 981                         popts->addr_hash = 1;
 982         }
 983
 984         if (pdimm[0].n_ranks == 4)
 985                 popts->quad_rank_present = 1;
 986
 987         ddr_freq = get_ddr_freq(0) / 1000000;
 988         if (popts->registered_dimm_en) {
 989                 popts->rcw_override = 1;
 990                 popts->rcw_1 = 0x000a5a00;
 991                 if (ddr_freq <= 800)
 992                         popts->rcw_2 = 0x00000000;
 993                 else if (ddr_freq <= 1066)
 994                         popts->rcw_2 = 0x00100000;
 995                 else if (ddr_freq <= 1333)
 996                         popts->rcw_2 = 0x00200000;
 997                 else
 998                         popts->rcw_2 = 0x00300000;
 999         }
1000
1001         fsl_ddr_board_options(popts, pdimm, ctrl_num);
1002
1003         return 0;
1004 }
1005
1006 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1007 {
1008         int i, j, k, check_n_ranks, intlv_invalid = 0;
1009         unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1010         unsigned long long check_rank_density;
1011         struct dimm_params_s *dimm;
1012         /*
1013          * Check if all controllers are configured for memory
1014          * controller interleaving. Identical dimms are recommended. At least
1015          * the size, row and col address should be checked.
1016          */
1017         j = 0;
1018         check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
1019         check_rank_density = pinfo->dimm_params[0][0].rank_density;
1020         check_n_row_addr =  pinfo->dimm_params[0][0].n_row_addr;
1021         check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
1022         check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
1023         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1024                 dimm = &pinfo->dimm_params[i][0];
1025                 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1026                         continue;
1027                 } else if (((check_rank_density != dimm->rank_density) ||
1028                      (check_n_ranks != dimm->n_ranks) ||
1029                      (check_n_row_addr != dimm->n_row_addr) ||
1030                      (check_n_col_addr != dimm->n_col_addr) ||
1031                      (check_intlv !=
1032                         pinfo->memctl_opts[i].memctl_interleaving_mode))){
1033                         intlv_invalid = 1;
1034                         break;
1035                 } else {
1036                         j++;
1037                 }
1038
1039         }
1040         if (intlv_invalid) {
1041                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1042                         pinfo->memctl_opts[i].memctl_interleaving = 0;
1043                 printf("Not all DIMMs are identical. "
1044                         "Memory controller interleaving disabled.\n");
1045         } else {
1046                 switch (check_intlv) {
1047                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1048                 case FSL_DDR_PAGE_INTERLEAVING:
1049                 case FSL_DDR_BANK_INTERLEAVING:
1050                 case FSL_DDR_SUPERBANK_INTERLEAVING:
1051                         if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1052                                 k = 2;
1053                         else
1054                                 k = CONFIG_NUM_DDR_CONTROLLERS;
1055                         break;
1056                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1057                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1058                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1059                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1060                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1061                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1062                 default:
1063                         k = CONFIG_NUM_DDR_CONTROLLERS;
1064                         break;
1065                 }
1066                 debug("%d of %d controllers are interleaving.\n", j, k);
1067                 if (j != k) {
1068                         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1069                                 pinfo->memctl_opts[i].memctl_interleaving = 0;
1070                         printf("Not all controllers have compatible "
1071                                 "interleaving mode. All disabled.\n");
1072                 }
1073         }
1074         debug("Checking interleaving options completed\n");
1075 }
1076
1077 int fsl_use_spd(void)
1078 {
1079         int use_spd = 0;
1080
1081 #ifdef CONFIG_DDR_SPD
1082         char buffer[HWCONFIG_BUFFER_SIZE];
1083         char *buf = NULL;
1084
1085         /*
1086          * Extract hwconfig from environment since we have not properly setup
1087          * the environment but need it for ddr config params
1088          */
1089         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1090                 buf = buffer;
1091
1092         /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1093         if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1094                 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1095                         use_spd = 1;
1096                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
1097                                                "fixed", buf))
1098                         use_spd = 0;
1099                 else
1100                         use_spd = 1;
1101         } else
1102                 use_spd = 1;
1103 #endif
1104
1105         return use_spd;
1106 }