2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_law.h>
14 unsigned int fsl_ddr_get_mem_data_rate(void);
17 * Round mclk_ps to nearest 10 ps in memory controller code.
19 * If an imprecise data rate is too high due to rounding error
20 * propagation, compute a suitably rounded mclk_ps to compute
21 * a working memory controller configuration.
23 unsigned int get_memory_clk_period_ps(void)
27 mclk_ps
= 2000000000000ULL / fsl_ddr_get_mem_data_rate();
28 /* round to nearest 10 ps */
29 return 10 * ((mclk_ps
+ 5) / 10);
32 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
33 unsigned int picos_to_mclk(unsigned int picos
)
35 const unsigned long long ULL_2e12
= 2000000000000ULL;
36 const unsigned long long ULL_8Fs
= 0xFFFFFFFFULL
;
37 unsigned long long clks
;
38 unsigned long long clks_temp
;
43 clks
= fsl_ddr_get_mem_data_rate() * (unsigned long long) picos
;
45 clks
= clks
/ ULL_2e12
;
46 if (clks_temp
% ULL_2e12
) {
54 return (unsigned int) clks
;
57 unsigned int mclk_to_picos(unsigned int mclk
)
59 return get_memory_clk_period_ps() * mclk
;
63 __fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
64 unsigned int memctl_interleaved
,
65 unsigned int ctrl_num
)
67 unsigned long long base
= memctl_common_params
->base_address
;
68 unsigned long long size
= memctl_common_params
->total_mem
;
71 * If no DIMMs on this controller, do not proceed any further.
73 if (!memctl_common_params
->ndimms_present
) {
77 #if !defined(CONFIG_PHYS_64BIT)
78 if (base
>= CONFIG_MAX_MEM_MAPPED
)
80 if ((base
+ size
) >= CONFIG_MAX_MEM_MAPPED
)
81 size
= CONFIG_MAX_MEM_MAPPED
- base
;
86 * Set up LAW for DDR controller 1 space.
88 unsigned int lawbar1_target_id
= memctl_interleaved
89 ? LAW_TRGT_IF_DDR_INTRLV
: LAW_TRGT_IF_DDR_1
;
91 if (set_ddr_laws(base
, size
, lawbar1_target_id
) < 0) {
92 printf("%s: ERROR (ctrl #0, intrlv=%d)\n", __func__
,
96 } else if (ctrl_num
== 1) {
97 if (set_ddr_laws(base
, size
, LAW_TRGT_IF_DDR_2
) < 0) {
98 printf("%s: ERROR (ctrl #1)\n", __func__
);
102 printf("%s: unexpected DDR controller number (%u)\n", __func__
,
107 __attribute__((weak
, alias("__fsl_ddr_set_lawbar"))) void
108 fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
109 unsigned int memctl_interleaved
,
110 unsigned int ctrl_num
);
112 void board_add_ram_info(int use_default
)
114 #if defined(CONFIG_MPC85xx)
115 volatile ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR
);
116 #elif defined(CONFIG_MPC86xx)
117 volatile ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR
);
119 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
120 uint32_t cs0_config
= in_be32(&ddr
->cs0_config
);
122 uint32_t sdram_cfg
= in_be32(&ddr
->sdram_cfg
);
126 switch ((sdram_cfg
& SDRAM_CFG_SDRAM_TYPE_MASK
) >>
127 SDRAM_CFG_SDRAM_TYPE_SHIFT
) {
128 case SDRAM_TYPE_DDR1
:
131 case SDRAM_TYPE_DDR2
:
134 case SDRAM_TYPE_DDR3
:
142 if (sdram_cfg
& SDRAM_CFG_32_BE
)
147 /* Calculate CAS latency based on timing cfg values */
148 cas_lat
= ((in_be32(&ddr
->timing_cfg_1
) >> 16) & 0xf) + 1;
149 if ((in_be32(&ddr
->timing_cfg_3
) >> 12) & 1)
151 printf(", CL=%d", cas_lat
>> 1);
155 if (sdram_cfg
& SDRAM_CFG_ECC_EN
)
160 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
161 if (cs0_config
& 0x20000000) {
163 puts(" DDR Controller Interleaving Mode: ");
165 switch ((cs0_config
>> 24) & 0xf) {
166 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
169 case FSL_DDR_PAGE_INTERLEAVING
:
172 case FSL_DDR_BANK_INTERLEAVING
:
175 case FSL_DDR_SUPERBANK_INTERLEAVING
:
185 if ((sdram_cfg
>> 8) & 0x7f) {
187 puts(" DDR Chip-Select Interleaving Mode: ");
188 switch(sdram_cfg
>> 8 & 0x7f) {
189 case FSL_DDR_CS0_CS1_CS2_CS3
:
190 puts("CS0+CS1+CS2+CS3");
192 case FSL_DDR_CS0_CS1
:
195 case FSL_DDR_CS2_CS3
:
198 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
199 puts("CS0+CS1 and CS2+CS3");