2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_law.h>
15 /* To avoid 64-bit full-divides, we factor this here */
16 #define ULL_2E12 2000000000000ULL
17 #define UL_5POW12 244140625UL
18 #define UL_2POW13 (1UL << 13)
20 #define ULL_8FS 0xFFFFFFFFULL
23 * Round up mclk_ps to nearest 1 ps in memory controller code
24 * if the error is 0.5ps or more.
26 * If an imprecise data rate is too high due to rounding error
27 * propagation, compute a suitably rounded mclk_ps to compute
28 * a working memory controller configuration.
30 unsigned int get_memory_clk_period_ps(void)
32 unsigned int data_rate
= get_ddr_freq(0);
35 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
36 unsigned long long rem
, mclk_ps
= ULL_2E12
;
38 /* Now perform the big divide, the result fits in 32-bits */
39 rem
= do_div(mclk_ps
, data_rate
);
40 result
= (rem
>= (data_rate
>> 1)) ? mclk_ps
+ 1 : mclk_ps
;
45 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
46 unsigned int picos_to_mclk(unsigned int picos
)
48 unsigned long long clks
, clks_rem
;
49 unsigned long data_rate
= get_ddr_freq(0);
51 /* Short circuit for zero picos */
55 /* First multiply the time by the data rate (32x32 => 64) */
56 clks
= picos
* (unsigned long long)data_rate
;
58 * Now divide by 5^12 and track the 32-bit remainder, then divide
59 * by 2*(2^12) using shifts (and updating the remainder).
61 clks_rem
= do_div(clks
, UL_5POW12
);
62 clks_rem
+= (clks
& (UL_2POW13
-1)) * UL_5POW12
;
65 /* If we had a remainder greater than the 1ps error, then round up */
66 if (clks_rem
> data_rate
)
69 /* Clamp to the maximum representable value */
72 return (unsigned int) clks
;
75 unsigned int mclk_to_picos(unsigned int mclk
)
77 return get_memory_clk_period_ps() * mclk
;
81 __fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
82 unsigned int law_memctl
,
83 unsigned int ctrl_num
)
85 unsigned long long base
= memctl_common_params
->base_address
;
86 unsigned long long size
= memctl_common_params
->total_mem
;
89 * If no DIMMs on this controller, do not proceed any further.
91 if (!memctl_common_params
->ndimms_present
) {
95 #if !defined(CONFIG_PHYS_64BIT)
96 if (base
>= CONFIG_MAX_MEM_MAPPED
)
98 if ((base
+ size
) >= CONFIG_MAX_MEM_MAPPED
)
99 size
= CONFIG_MAX_MEM_MAPPED
- base
;
101 if (set_ddr_laws(base
, size
, law_memctl
) < 0) {
102 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__
, ctrl_num
,
106 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
107 base
, size
, law_memctl
);
110 __attribute__((weak
, alias("__fsl_ddr_set_lawbar"))) void
111 fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
112 unsigned int memctl_interleaved
,
113 unsigned int ctrl_num
);
115 void fsl_ddr_set_intl3r(const unsigned int granule_size
)
118 u32
*mcintl3r
= (void *) (CONFIG_SYS_IMMR
+ 0x18004);
119 *mcintl3r
= 0x80000000 | (granule_size
& 0x1f);
120 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size
);
124 void board_add_ram_info(int use_default
)
126 #if defined(CONFIG_MPC83xx)
127 immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
128 ccsr_ddr_t
*ddr
= (void *)&immap
->ddr
;
129 #elif defined(CONFIG_MPC85xx)
130 ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR
);
131 #elif defined(CONFIG_MPC86xx)
132 ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR
);
134 #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
135 u32
*mcintl3r
= (void *) (CONFIG_SYS_IMMR
+ 0x18004);
137 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
138 uint32_t cs0_config
= in_be32(&ddr
->cs0_config
);
140 uint32_t sdram_cfg
= in_be32(&ddr
->sdram_cfg
);
144 switch ((sdram_cfg
& SDRAM_CFG_SDRAM_TYPE_MASK
) >>
145 SDRAM_CFG_SDRAM_TYPE_SHIFT
) {
146 case SDRAM_TYPE_DDR1
:
149 case SDRAM_TYPE_DDR2
:
152 case SDRAM_TYPE_DDR3
:
160 if (sdram_cfg
& SDRAM_CFG_32_BE
)
162 else if (sdram_cfg
& SDRAM_CFG_16_BE
)
167 /* Calculate CAS latency based on timing cfg values */
168 cas_lat
= ((in_be32(&ddr
->timing_cfg_1
) >> 16) & 0xf) + 1;
169 if ((in_be32(&ddr
->timing_cfg_3
) >> 12) & 1)
171 printf(", CL=%d", cas_lat
>> 1);
175 if (sdram_cfg
& SDRAM_CFG_ECC_EN
)
180 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
182 if (*mcintl3r
& 0x80000000) {
184 puts(" DDR Controller Interleaving Mode: ");
185 switch (*mcintl3r
& 0x1f) {
186 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
189 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
192 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
196 puts("3-way UNKNOWN");
202 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
203 if (cs0_config
& 0x20000000) {
205 puts(" DDR Controller Interleaving Mode: ");
207 switch ((cs0_config
>> 24) & 0xf) {
208 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
211 case FSL_DDR_PAGE_INTERLEAVING
:
214 case FSL_DDR_BANK_INTERLEAVING
:
217 case FSL_DDR_SUPERBANK_INTERLEAVING
:
227 if ((sdram_cfg
>> 8) & 0x7f) {
229 puts(" DDR Chip-Select Interleaving Mode: ");
230 switch(sdram_cfg
>> 8 & 0x7f) {
231 case FSL_DDR_CS0_CS1_CS2_CS3
:
232 puts("CS0+CS1+CS2+CS3");
234 case FSL_DDR_CS0_CS1
:
237 case FSL_DDR_CS2_CS3
:
240 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
241 puts("CS0+CS1 and CS2+CS3");