2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_law.h>
15 /* To avoid 64-bit full-divides, we factor this here */
16 #define ULL_2E12 2000000000000ULL
17 #define UL_5POW12 244140625UL
18 #define UL_2POW13 (1UL << 13)
20 #define ULL_8FS 0xFFFFFFFFULL
23 * Round up mclk_ps to nearest 1 ps in memory controller code
24 * if the error is 0.5ps or more.
26 * If an imprecise data rate is too high due to rounding error
27 * propagation, compute a suitably rounded mclk_ps to compute
28 * a working memory controller configuration.
30 unsigned int get_memory_clk_period_ps(void)
32 unsigned int data_rate
= get_ddr_freq(0);
35 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
36 unsigned long long rem
, mclk_ps
= ULL_2E12
;
38 /* Now perform the big divide, the result fits in 32-bits */
39 rem
= do_div(mclk_ps
, data_rate
);
40 result
= (rem
>= (data_rate
>> 1)) ? mclk_ps
+ 1 : mclk_ps
;
45 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
46 unsigned int picos_to_mclk(unsigned int picos
)
48 unsigned long long clks
, clks_rem
;
49 unsigned long data_rate
= get_ddr_freq(0);
51 /* Short circuit for zero picos */
55 /* First multiply the time by the data rate (32x32 => 64) */
56 clks
= picos
* (unsigned long long)data_rate
;
58 * Now divide by 5^12 and track the 32-bit remainder, then divide
59 * by 2*(2^12) using shifts (and updating the remainder).
61 clks_rem
= do_div(clks
, UL_5POW12
);
62 clks_rem
+= (clks
& (UL_2POW13
-1)) * UL_5POW12
;
65 /* If we had a remainder greater than the 1ps error, then round up */
66 if (clks_rem
> data_rate
)
69 /* Clamp to the maximum representable value */
72 return (unsigned int) clks
;
75 unsigned int mclk_to_picos(unsigned int mclk
)
77 return get_memory_clk_period_ps() * mclk
;
81 __fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
82 unsigned int memctl_interleaved
,
83 unsigned int ctrl_num
)
85 unsigned long long base
= memctl_common_params
->base_address
;
86 unsigned long long size
= memctl_common_params
->total_mem
;
89 * If no DIMMs on this controller, do not proceed any further.
91 if (!memctl_common_params
->ndimms_present
) {
95 #if !defined(CONFIG_PHYS_64BIT)
96 if (base
>= CONFIG_MAX_MEM_MAPPED
)
98 if ((base
+ size
) >= CONFIG_MAX_MEM_MAPPED
)
99 size
= CONFIG_MAX_MEM_MAPPED
- base
;
104 * Set up LAW for DDR controller 1 space.
106 unsigned int lawbar1_target_id
= memctl_interleaved
107 ? LAW_TRGT_IF_DDR_INTRLV
: LAW_TRGT_IF_DDR_1
;
109 if (set_ddr_laws(base
, size
, lawbar1_target_id
) < 0) {
110 printf("%s: ERROR (ctrl #0, intrlv=%d)\n", __func__
,
114 } else if (ctrl_num
== 1) {
115 if (set_ddr_laws(base
, size
, LAW_TRGT_IF_DDR_2
) < 0) {
116 printf("%s: ERROR (ctrl #1)\n", __func__
);
120 printf("%s: unexpected DDR controller number (%u)\n", __func__
,
125 __attribute__((weak
, alias("__fsl_ddr_set_lawbar"))) void
126 fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
127 unsigned int memctl_interleaved
,
128 unsigned int ctrl_num
);
130 void board_add_ram_info(int use_default
)
132 #if defined(CONFIG_MPC83xx)
133 immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
134 ccsr_ddr_t
*ddr
= (void *)&immap
->ddr
;
135 #elif defined(CONFIG_MPC85xx)
136 ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR
);
137 #elif defined(CONFIG_MPC86xx)
138 ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR
);
140 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
141 uint32_t cs0_config
= in_be32(&ddr
->cs0_config
);
143 uint32_t sdram_cfg
= in_be32(&ddr
->sdram_cfg
);
147 switch ((sdram_cfg
& SDRAM_CFG_SDRAM_TYPE_MASK
) >>
148 SDRAM_CFG_SDRAM_TYPE_SHIFT
) {
149 case SDRAM_TYPE_DDR1
:
152 case SDRAM_TYPE_DDR2
:
155 case SDRAM_TYPE_DDR3
:
163 if (sdram_cfg
& SDRAM_CFG_32_BE
)
165 else if (sdram_cfg
& SDRAM_CFG_16_BE
)
170 /* Calculate CAS latency based on timing cfg values */
171 cas_lat
= ((in_be32(&ddr
->timing_cfg_1
) >> 16) & 0xf) + 1;
172 if ((in_be32(&ddr
->timing_cfg_3
) >> 12) & 1)
174 printf(", CL=%d", cas_lat
>> 1);
178 if (sdram_cfg
& SDRAM_CFG_ECC_EN
)
183 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
184 if (cs0_config
& 0x20000000) {
186 puts(" DDR Controller Interleaving Mode: ");
188 switch ((cs0_config
>> 24) & 0xf) {
189 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
192 case FSL_DDR_PAGE_INTERLEAVING
:
195 case FSL_DDR_BANK_INTERLEAVING
:
198 case FSL_DDR_SUPERBANK_INTERLEAVING
:
208 if ((sdram_cfg
>> 8) & 0x7f) {
210 puts(" DDR Chip-Select Interleaving Mode: ");
211 switch(sdram_cfg
>> 8 & 0x7f) {
212 case FSL_DDR_CS0_CS1_CS2_CS3
:
213 puts("CS0+CS1+CS2+CS3");
215 case FSL_DDR_CS0_CS1
:
218 case FSL_DDR_CS2_CS3
:
221 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
222 puts("CS0+CS1 and CS2+CS3");