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git.ipfire.org Git - thirdparty/u-boot.git/blob - arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
2 * arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
3 * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
4 * SDRAM controller. Those are all current 405 PPC's.
7 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
11 * Kenneth Johansson ,Ericsson AB.
12 * kenneth.johansson@etx.ericsson.se
14 * hacked up by bill hunter. fixed so we could run before
15 * serial_init and console_init. previous version avoided this by
16 * running out of cache memory during serial/console init, then running
20 * Jun Gu, Artesyn Technology, jung@artesyncp.com
21 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
24 * Stefan Roese, DENX Software Engineering, sr@denx.de.
26 * SPDX-License-Identifier: GPL-2.0+
30 #include <asm/processor.h>
32 #include <asm/ppc4xx.h>
34 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
39 #ifndef CONFIG_SYS_I2C_SPEED
40 #define CONFIG_SYS_I2C_SPEED 50000
43 #define ONE_BILLION 1000000000
45 #define SDRAM0_CFG_DCE 0x80000000
46 #define SDRAM0_CFG_SRE 0x40000000
47 #define SDRAM0_CFG_PME 0x20000000
48 #define SDRAM0_CFG_MEMCHK 0x10000000
49 #define SDRAM0_CFG_REGEN 0x08000000
50 #define SDRAM0_CFG_ECCDD 0x00400000
51 #define SDRAM0_CFG_EMDULR 0x00200000
52 #define SDRAM0_CFG_DRW_SHIFT (31-6)
53 #define SDRAM0_CFG_BRPF_SHIFT (31-8)
55 #define SDRAM0_TR_CASL_SHIFT (31-8)
56 #define SDRAM0_TR_PTA_SHIFT (31-13)
57 #define SDRAM0_TR_CTP_SHIFT (31-15)
58 #define SDRAM0_TR_LDF_SHIFT (31-17)
59 #define SDRAM0_TR_RFTA_SHIFT (31-29)
60 #define SDRAM0_TR_RCD_SHIFT (31-31)
62 #define SDRAM0_RTR_SHIFT (31-15)
63 #define SDRAM0_ECCCFG_SHIFT (31-11)
65 /* SDRAM0_CFG enable macro */
66 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
68 #define SDRAM0_BXCR_SZ_MASK 0x000e0000
69 #define SDRAM0_BXCR_AM_MASK 0x0000e000
71 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
72 #define SDRAM0_BXCR_AM_SHIFT (31-18)
74 #define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
75 #define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
77 #ifdef CONFIG_SPDDRAM_SILENT
78 # define SPD_ERR(x) do { return 0; } while (0)
80 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
83 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
85 /* function prototypes */
86 int spd_read(uint addr
);
90 * This function is reading data from the DIMM module EEPROM over the SPD bus
91 * and uses that to program the sdram controller.
93 * This works on boards that has the same schematics that the AMCC walnut has.
95 * Input: null for default I2C spd functions or a pointer to a custom function
99 long int spd_sdram(int(read_spd
)(uint addr
))
102 int total_size
,bank_size
,bank_code
;
106 int sdram0_pmit
=0x07c00000;
109 #ifndef CONFIG_405EP /* not on PPC405EP */
112 int sdram0_besr0
= -1;
113 int sdram0_besr1
= -1;
114 int sdram0_eccesr
= -1;
130 PPC4xx_SYS_INFO sys_info
;
131 unsigned long bus_period_x_10
;
136 get_sys_info(&sys_info
);
137 bus_period_x_10
= ONE_BILLION
/ (sys_info
.freqPLB
/ 10);
142 * Make sure I2C controller is initialized
145 i2c_init(CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
148 /* Make shure we are using SDRAM */
149 if (read_spd(2) != 0x04) {
150 SPD_ERR("SDRAM - non SDRAM memory module found\n");
153 /* ------------------------------------------------------------------
154 * configure memory timing register
157 * 27 IN Row Precharge Time ( t RP)
158 * 29 MIN RAS to CAS Delay ( t RCD)
159 * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
160 * -------------------------------------------------------------------*/
163 * first figure out which cas latency mode to use
164 * use the min supported mode
167 tmp
= read_spd(127) & 0x6;
168 if (tmp
== 0x02) { /* only cas = 2 supported */
170 /* t_ck = read_spd(9); */
171 /* t_ac = read_spd(10); */
172 } else if (tmp
== 0x04) { /* only cas = 3 supported */
174 /* t_ck = read_spd(9); */
175 /* t_ac = read_spd(10); */
176 } else if (tmp
== 0x06) { /* 2,3 supported, so use 2 */
178 /* t_ck = read_spd(23); */
179 /* t_ac = read_spd(24); */
181 SPD_ERR("SDRAM - unsupported CAS latency \n");
184 /* get some timing values, t_rp,t_rcd,t_ras,t_rc
187 t_rcd
= read_spd(29);
188 t_ras
= read_spd(30);
191 /* The following timing calcs subtract 1 before deviding.
192 * this has effect of using ceiling instead of floor rounding,
193 * and also subtracting 1 to convert number to reg value
196 sdram0_tr
= (min_cas
- 1) << SDRAM0_TR_CASL_SHIFT
;
198 sdram0_tr
|= ((((t_rp
- 1) * 10)/bus_period_x_10
) & 0x3) << SDRAM0_TR_PTA_SHIFT
;
200 tmp
= (((t_rc
- t_rcd
- t_rp
-1) * 10) / bus_period_x_10
) & 0x3;
203 sdram0_tr
|= tmp
<< SDRAM0_TR_CTP_SHIFT
;
204 /* set LDF = 2 cycles, reg value = 1 */
205 sdram0_tr
|= 1 << SDRAM0_TR_LDF_SHIFT
;
206 /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
207 tmp
= (((t_rc
- 1) * 10) / bus_period_x_10
) - 3;
212 sdram0_tr
|= tmp
<< SDRAM0_TR_RFTA_SHIFT
;
213 /* set RCD = t_rcd/bus_period*/
214 sdram0_tr
|= ((((t_rcd
- 1) * 10) / bus_period_x_10
) &0x3) << SDRAM0_TR_RCD_SHIFT
;
217 /*------------------------------------------------------------------
218 * configure RTR register
219 * -------------------------------------------------------------------*/
222 tmp
= read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
243 SPD_ERR("SDRAM - Bad refresh period \n");
245 /* convert from nsec to bus cycles */
246 tmp
= (tmp
* 10) / bus_period_x_10
;
247 sdram0_rtr
= (tmp
& 0x3ff8) << SDRAM0_RTR_SHIFT
;
249 /*------------------------------------------------------------------
250 * determine the number of banks used
251 * -------------------------------------------------------------------*/
252 /* byte 7:6 is module data width */
253 if (read_spd(7) != 0)
254 SPD_ERR("SDRAM - unsupported module width\n");
257 SPD_ERR("SDRAM - unsupported module width\n");
259 bank_cnt
= 1; /* one bank per sdram side */
261 bank_cnt
= 2; /* need two banks per side */
263 bank_cnt
= 4; /* need four banks per side */
265 SPD_ERR("SDRAM - unsupported module width\n");
267 /* byte 5 is the module row count (refered to as dimm "sides") */
276 bank_cnt
= 8; /* 8 is an error code */
278 if (bank_cnt
> 4) /* we only have 4 banks to work with */
279 SPD_ERR("SDRAM - unsupported module rows for this width\n");
281 #ifndef CONFIG_405EP /* not on PPC405EP */
282 /* now check for ECC ability of module. We only support ECC
283 * on 32 bit wide devices with 8 bit ECC.
285 if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
286 sdram0_ecccfg
= 0xf << SDRAM0_ECCCFG_SHIFT
;
294 /*------------------------------------------------------------------
295 * calculate total size
296 * -------------------------------------------------------------------*/
297 /* calculate total size and do sanity check */
299 total_size
= 1 << 22; /* total_size = 4MB */
300 /* now multiply 4M by the smallest device row density */
301 /* note that we don't support asymetric rows */
302 while (((tmp
& 0x0001) == 0) && (tmp
!= 0)) {
303 total_size
= total_size
<< 1;
306 total_size
*= read_spd(5); /* mult by module rows (dimm sides) */
308 /*------------------------------------------------------------------
309 * map rows * cols * banks to a mode
310 * -------------------------------------------------------------------*/
323 SPD_ERR("SDRAM - unsupported mode\n");
336 SPD_ERR("SDRAM - unsupported mode\n");
346 if (read_spd(17) == 2)
347 mode
= 6; /* mode 7 */
349 mode
= 2; /* mode 3 */
352 mode
= 2; /* mode 3 */
355 SPD_ERR("SDRAM - unsupported mode\n");
359 SPD_ERR("SDRAM - unsupported mode\n");
362 /*------------------------------------------------------------------
363 * using the calculated values, compute the bank
364 * config register values.
365 * -------------------------------------------------------------------*/
367 /* compute the size of each bank */
368 bank_size
= total_size
/ bank_cnt
;
369 /* convert bank size to bank size code for ppc4xx
370 by takeing log2(bank_size) - 22 */
371 tmp
= bank_size
; /* start with tmp = bank_size */
372 bank_code
= 0; /* and bank_code = 0 */
373 while (tmp
> 1) { /* this takes log2 of tmp */
374 bank_code
++; /* and stores result in bank_code */
376 } /* bank_code is now log2(bank_size) */
377 bank_code
-= 22; /* subtract 22 to get the code */
379 tmp
= SDRAM0_BXCR_SZ(bank_code
) | SDRAM0_BXCR_AM(mode
) | 1;
380 sdram0_b0cr
= (bank_size
* 0) | tmp
;
381 #ifndef CONFIG_405EP /* not on PPC405EP */
383 sdram0_b2cr
= (bank_size
* 1) | tmp
;
385 sdram0_b1cr
= (bank_size
* 2) | tmp
;
387 sdram0_b3cr
= (bank_size
* 3) | tmp
;
389 /* PPC405EP chip only supports two SDRAM banks */
391 sdram0_b1cr
= (bank_size
* 1) | tmp
;
393 total_size
= 2 * bank_size
;
397 * enable sdram controller DCE=1
398 * enable burst read prefetch to 32 bytes BRPF=2
399 * leave other functions off
402 /*------------------------------------------------------------------
403 * now that we've done our calculations, we are ready to
404 * program all the registers.
405 * -------------------------------------------------------------------*/
407 /* disable memcontroller so updates work */
408 mtsdram(SDRAM0_CFG
, 0);
410 #ifndef CONFIG_405EP /* not on PPC405EP */
411 mtsdram(SDRAM0_BESR0
, sdram0_besr0
);
412 mtsdram(SDRAM0_BESR1
, sdram0_besr1
);
413 mtsdram(SDRAM0_ECCCFG
, sdram0_ecccfg
);
414 mtsdram(SDRAM0_ECCESR
, sdram0_eccesr
);
416 mtsdram(SDRAM0_RTR
, sdram0_rtr
);
417 mtsdram(SDRAM0_PMIT
, sdram0_pmit
);
418 mtsdram(SDRAM0_B0CR
, sdram0_b0cr
);
419 mtsdram(SDRAM0_B1CR
, sdram0_b1cr
);
420 #ifndef CONFIG_405EP /* not on PPC405EP */
421 mtsdram(SDRAM0_B2CR
, sdram0_b2cr
);
422 mtsdram(SDRAM0_B3CR
, sdram0_b3cr
);
424 mtsdram(SDRAM0_TR
, sdram0_tr
);
426 /* SDRAM have a power on delay, 500 micro should do */
428 sdram0_cfg
= SDRAM0_CFG_DCE
| SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD
| SDRAM0_CFG_EMDULR
;
429 #ifndef CONFIG_405EP /* not on PPC405EP */
431 sdram0_cfg
|= SDRAM0_CFG_MEMCHK
;
433 mtsdram(SDRAM0_CFG
, sdram0_cfg
);
438 int spd_read(uint addr
)
442 if (i2c_read(SPD_EEPROM_ADDRESS
, addr
, 1, data
, 1) == 0)
448 #endif /* CONFIG_SPD_EEPROM */