2 * arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
3 * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
4 * DDR controller. Those are 440GP/GX/EP/GR.
7 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
11 * Kenneth Johansson ,Ericsson AB.
12 * kenneth.johansson@etx.ericsson.se
14 * hacked up by bill hunter. fixed so we could run before
15 * serial_init and console_init. previous version avoided this by
16 * running out of cache memory during serial/console init, then running
20 * Jun Gu, Artesyn Technology, jung@artesyncp.com
21 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
23 * (C) Copyright 2005-2007
24 * Stefan Roese, DENX Software Engineering, sr@denx.de.
26 * SPDX-License-Identifier: GPL-2.0+
29 /* define DEBUG for debugging output (obviously ;-)) */
35 #include <asm/processor.h>
37 #include <asm/ppc4xx.h>
42 #if defined(CONFIG_SPD_EEPROM) && \
43 (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
44 defined(CONFIG_440EP) || defined(CONFIG_440GR))
49 #define ONE_BILLION 1000000000
52 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
54 void __spd_ddr_init_hang (void)
58 void spd_ddr_init_hang (void) __attribute__((weak
, alias("__spd_ddr_init_hang")));
60 /*-----------------------------------------------------------------------------+
62 +-----------------------------------------------------------------------------*/
63 #define DEFAULT_SPD_ADDR1 0x53
64 #define DEFAULT_SPD_ADDR2 0x52
65 #define MAXBANKS 4 /* at most 4 dimm banks */
66 #define MAX_SPD_BYTES 256
67 #define NUMHALFCYCLES 4
73 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
74 * region. Right now the cache should still be disabled in U-Boot because of the
75 * EMAC driver, that need it's buffer descriptor to be located in non cached
78 * If at some time this restriction doesn't apply anymore, just define
79 * CONFIG_4xx_DCACHE in the board config file and this code should setup
80 * everything correctly.
82 #ifdef CONFIG_4xx_DCACHE
83 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
85 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
88 /* bank_parms is used to sort the bank sizes by descending order */
91 unsigned long bank_size_bytes
;
94 typedef struct bank_param BANKPARMS
;
96 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
97 extern const unsigned char cfg_simulate_spd_eeprom
[128];
100 static unsigned char spd_read(uchar chip
, uint addr
);
101 static void get_spd_info(unsigned long *dimm_populated
,
102 unsigned char *iic0_dimm_addr
,
103 unsigned long num_dimm_banks
);
104 static void check_mem_type(unsigned long *dimm_populated
,
105 unsigned char *iic0_dimm_addr
,
106 unsigned long num_dimm_banks
);
107 static void check_volt_type(unsigned long *dimm_populated
,
108 unsigned char *iic0_dimm_addr
,
109 unsigned long num_dimm_banks
);
110 static void program_cfg0(unsigned long *dimm_populated
,
111 unsigned char *iic0_dimm_addr
,
112 unsigned long num_dimm_banks
);
113 static void program_cfg1(unsigned long *dimm_populated
,
114 unsigned char *iic0_dimm_addr
,
115 unsigned long num_dimm_banks
);
116 static void program_rtr(unsigned long *dimm_populated
,
117 unsigned char *iic0_dimm_addr
,
118 unsigned long num_dimm_banks
);
119 static void program_tr0(unsigned long *dimm_populated
,
120 unsigned char *iic0_dimm_addr
,
121 unsigned long num_dimm_banks
);
122 static void program_tr1(void);
124 static unsigned long program_bxcr(unsigned long *dimm_populated
,
125 unsigned char *iic0_dimm_addr
,
126 unsigned long num_dimm_banks
);
129 * This function is reading data from the DIMM module EEPROM over the SPD bus
130 * and uses that to program the sdram controller.
132 * This works on boards that has the same schematics that the AMCC walnut has.
134 * BUG: Don't handle ECC memory
135 * BUG: A few values in the TR register is currently hardcoded
137 long int spd_sdram(void) {
138 unsigned char iic0_dimm_addr
[] = SPD_EEPROM_ADDRESS
;
139 unsigned long dimm_populated
[sizeof(iic0_dimm_addr
)];
140 unsigned long total_size
;
143 unsigned long num_dimm_banks
; /* on board dimm banks */
145 num_dimm_banks
= sizeof(iic0_dimm_addr
);
148 * Make sure I2C controller is initialized
151 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM
);
154 * Read the SPD information using I2C interface. Check to see if the
155 * DIMM slots are populated.
157 get_spd_info(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
160 * Check the memory type for the dimms plugged.
162 check_mem_type(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
165 * Check the voltage type for the dimms plugged.
167 check_volt_type(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
169 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
171 * Soft-reset SDRAM controller.
173 mtsdr(SDR0_SRST
, SDR0_SRST_DMC
);
174 mtsdr(SDR0_SRST
, 0x00000000);
178 * program 440GP SDRAM controller options (SDRAM0_CFG0)
180 program_cfg0(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
183 * program 440GP SDRAM controller options (SDRAM0_CFG1)
185 program_cfg1(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
188 * program SDRAM refresh register (SDRAM0_RTR)
190 program_rtr(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
193 * program SDRAM Timing Register 0 (SDRAM0_TR0)
195 program_tr0(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
198 * program the BxCR registers to find out total sdram installed
200 total_size
= program_bxcr(dimm_populated
, iic0_dimm_addr
,
203 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
204 /* and program tlb entries for this size (dynamic) */
205 program_tlb(0, 0, total_size
, MY_TLB_WORD2_I_ENABLE
);
209 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
211 mtsdram(SDRAM0_CLKTR
, 0x40000000);
214 * delay to ensure 200 usec has elapsed
219 * enable the memory controller
221 mfsdram(SDRAM0_CFG0
, cfg0
);
222 mtsdram(SDRAM0_CFG0
, cfg0
| SDRAM_CFG0_DCEN
);
225 * wait for SDRAM_CFG0_DC_EN to complete
228 mfsdram(SDRAM0_MCSTS
, mcsts
);
229 if ((mcsts
& SDRAM_MCSTS_MRSC
) != 0)
234 * program SDRAM Timing Register 1, adding some delays
238 #ifdef CONFIG_DDR_ECC
240 * If ecc is enabled, initialize the parity bits.
242 ecc_init(CONFIG_SYS_SDRAM_BASE
, total_size
);
248 static unsigned char spd_read(uchar chip
, uint addr
)
250 unsigned char data
[2];
252 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
253 if (chip
== CONFIG_SYS_SIMULATE_SPD_EEPROM
) {
255 * Onboard spd eeprom requested -> simulate values
257 return cfg_simulate_spd_eeprom
[addr
];
259 #endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
261 if (i2c_probe(chip
) == 0) {
262 if (i2c_read(chip
, addr
, 1, data
, 1) == 0) {
270 static void get_spd_info(unsigned long *dimm_populated
,
271 unsigned char *iic0_dimm_addr
,
272 unsigned long num_dimm_banks
)
274 unsigned long dimm_num
;
275 unsigned long dimm_found
;
276 unsigned char num_of_bytes
;
277 unsigned char total_size
;
280 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
284 num_of_bytes
= spd_read(iic0_dimm_addr
[dimm_num
], 0);
285 total_size
= spd_read(iic0_dimm_addr
[dimm_num
], 1);
287 if ((num_of_bytes
!= 0) && (total_size
!= 0)) {
288 dimm_populated
[dimm_num
] = true;
290 debug("DIMM slot %lu: populated\n", dimm_num
);
292 dimm_populated
[dimm_num
] = false;
293 debug("DIMM slot %lu: Not populated\n", dimm_num
);
297 if (dimm_found
== false) {
298 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
299 spd_ddr_init_hang ();
303 static void check_mem_type(unsigned long *dimm_populated
,
304 unsigned char *iic0_dimm_addr
,
305 unsigned long num_dimm_banks
)
307 unsigned long dimm_num
;
308 unsigned char dimm_type
;
310 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
311 if (dimm_populated
[dimm_num
] == true) {
312 dimm_type
= spd_read(iic0_dimm_addr
[dimm_num
], 2);
315 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num
);
318 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
320 printf("Only DDR SDRAM DIMMs are supported.\n");
321 printf("Replace the DIMM module with a supported DIMM.\n\n");
322 spd_ddr_init_hang ();
329 static void check_volt_type(unsigned long *dimm_populated
,
330 unsigned char *iic0_dimm_addr
,
331 unsigned long num_dimm_banks
)
333 unsigned long dimm_num
;
334 unsigned long voltage_type
;
336 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
337 if (dimm_populated
[dimm_num
] == true) {
338 voltage_type
= spd_read(iic0_dimm_addr
[dimm_num
], 8);
339 if (voltage_type
!= 0x04) {
340 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
342 spd_ddr_init_hang ();
344 debug("DIMM %lu voltage level supported.\n", dimm_num
);
351 static void program_cfg0(unsigned long *dimm_populated
,
352 unsigned char *iic0_dimm_addr
,
353 unsigned long num_dimm_banks
)
355 unsigned long dimm_num
;
357 unsigned long ecc_enabled
;
359 unsigned char attributes
;
360 unsigned long data_width
;
363 * get Memory Controller Options 0 data
365 mfsdram(SDRAM0_CFG0
, cfg0
);
370 cfg0
&= ~(SDRAM_CFG0_DCEN
| SDRAM_CFG0_MCHK_MASK
|
371 SDRAM_CFG0_RDEN
| SDRAM_CFG0_PMUD
|
372 SDRAM_CFG0_DMWD_MASK
|
373 SDRAM_CFG0_UIOS_MASK
| SDRAM_CFG0_PDP
);
377 * FIXME: assume the DDR SDRAMs in both banks are the same
380 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
381 if (dimm_populated
[dimm_num
] == true) {
382 ecc
= spd_read(iic0_dimm_addr
[dimm_num
], 11);
388 * program Registered DIMM Enable
390 attributes
= spd_read(iic0_dimm_addr
[dimm_num
], 21);
391 if ((attributes
& 0x02) != 0x00) {
392 cfg0
|= SDRAM_CFG0_RDEN
;
396 * program DDR SDRAM Data Width
399 (unsigned long)spd_read(iic0_dimm_addr
[dimm_num
],6) +
400 (((unsigned long)spd_read(iic0_dimm_addr
[dimm_num
],7)) << 8);
401 if (data_width
== 64 || data_width
== 72) {
402 cfg0
|= SDRAM_CFG0_DMWD_64
;
403 } else if (data_width
== 32 || data_width
== 40) {
404 cfg0
|= SDRAM_CFG0_DMWD_32
;
406 printf("WARNING: DIMM with datawidth of %lu bits.\n",
408 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
409 spd_ddr_init_hang ();
416 * program Memory Data Error Checking
418 if (ecc_enabled
== true) {
419 cfg0
|= SDRAM_CFG0_MCHK_GEN
;
421 cfg0
|= SDRAM_CFG0_MCHK_NON
;
425 * program Page Management Unit (0 == enabled)
427 cfg0
&= ~SDRAM_CFG0_PMUD
;
430 * program Memory Controller Options 0
431 * Note: DCEN must be enabled after all DDR SDRAM controller
432 * configuration registers get initialized.
434 mtsdram(SDRAM0_CFG0
, cfg0
);
437 static void program_cfg1(unsigned long *dimm_populated
,
438 unsigned char *iic0_dimm_addr
,
439 unsigned long num_dimm_banks
)
442 mfsdram(SDRAM0_CFG1
, cfg1
);
445 * Self-refresh exit, disable PM
447 cfg1
&= ~(SDRAM_CFG1_SRE
| SDRAM_CFG1_PMEN
);
450 * program Memory Controller Options 1
452 mtsdram(SDRAM0_CFG1
, cfg1
);
455 static void program_rtr(unsigned long *dimm_populated
,
456 unsigned char *iic0_dimm_addr
,
457 unsigned long num_dimm_banks
)
459 unsigned long dimm_num
;
460 unsigned long bus_period_x_10
;
461 unsigned long refresh_rate
= 0;
462 unsigned char refresh_rate_type
;
463 unsigned long refresh_interval
;
464 unsigned long sdram_rtr
;
465 PPC4xx_SYS_INFO sys_info
;
470 get_sys_info(&sys_info
);
471 bus_period_x_10
= ONE_BILLION
/ (sys_info
.freqPLB
/ 10);
473 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
474 if (dimm_populated
[dimm_num
] == true) {
475 refresh_rate_type
= 0x7F & spd_read(iic0_dimm_addr
[dimm_num
], 12);
476 switch (refresh_rate_type
) {
478 refresh_rate
= 15625;
481 refresh_rate
= 15625/4;
484 refresh_rate
= 15625/2;
487 refresh_rate
= 15626*2;
490 refresh_rate
= 15625*4;
493 refresh_rate
= 15625*8;
496 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
498 printf("Replace the DIMM module with a supported DIMM.\n");
506 refresh_interval
= refresh_rate
* 10 / bus_period_x_10
;
507 sdram_rtr
= (refresh_interval
& 0x3ff8) << 16;
510 * program Refresh Timer Register (SDRAM0_RTR)
512 mtsdram(SDRAM0_RTR
, sdram_rtr
);
515 static void program_tr0(unsigned long *dimm_populated
,
516 unsigned char *iic0_dimm_addr
,
517 unsigned long num_dimm_banks
)
519 unsigned long dimm_num
;
522 unsigned char t_rp_ns
;
523 unsigned char t_rcd_ns
;
524 unsigned char t_ras_ns
;
525 unsigned long t_rp_clk
;
526 unsigned long t_ras_rcd_clk
;
527 unsigned long t_rcd_clk
;
528 unsigned long t_rfc_clk
;
529 unsigned long plb_check
;
530 unsigned char cas_bit
;
531 unsigned long cas_index
;
532 unsigned char cas_2_0_available
;
533 unsigned char cas_2_5_available
;
534 unsigned char cas_3_0_available
;
535 unsigned long cycle_time_ns_x_10
[3];
536 unsigned long tcyc_3_0_ns_x_10
;
537 unsigned long tcyc_2_5_ns_x_10
;
538 unsigned long tcyc_2_0_ns_x_10
;
539 unsigned long tcyc_reg
;
540 unsigned long bus_period_x_10
;
541 PPC4xx_SYS_INFO sys_info
;
542 unsigned long residue
;
547 get_sys_info(&sys_info
);
548 bus_period_x_10
= ONE_BILLION
/ (sys_info
.freqPLB
/ 10);
551 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
553 mfsdram(SDRAM0_TR0
, tr0
);
554 tr0
&= ~(SDRAM_TR0_SDWR_MASK
| SDRAM_TR0_SDWD_MASK
|
555 SDRAM_TR0_SDCL_MASK
| SDRAM_TR0_SDPA_MASK
|
556 SDRAM_TR0_SDCP_MASK
| SDRAM_TR0_SDLD_MASK
|
557 SDRAM_TR0_SDRA_MASK
| SDRAM_TR0_SDRD_MASK
);
566 cas_2_0_available
= true;
567 cas_2_5_available
= true;
568 cas_3_0_available
= true;
569 tcyc_2_0_ns_x_10
= 0;
570 tcyc_2_5_ns_x_10
= 0;
571 tcyc_3_0_ns_x_10
= 0;
573 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
574 if (dimm_populated
[dimm_num
] == true) {
575 wcsbc
= spd_read(iic0_dimm_addr
[dimm_num
], 15);
576 t_rp_ns
= spd_read(iic0_dimm_addr
[dimm_num
], 27) >> 2;
577 t_rcd_ns
= spd_read(iic0_dimm_addr
[dimm_num
], 29) >> 2;
578 t_ras_ns
= spd_read(iic0_dimm_addr
[dimm_num
], 30);
579 cas_bit
= spd_read(iic0_dimm_addr
[dimm_num
], 18);
581 for (cas_index
= 0; cas_index
< 3; cas_index
++) {
584 tcyc_reg
= spd_read(iic0_dimm_addr
[dimm_num
], 9);
587 tcyc_reg
= spd_read(iic0_dimm_addr
[dimm_num
], 23);
590 tcyc_reg
= spd_read(iic0_dimm_addr
[dimm_num
], 25);
594 if ((tcyc_reg
& 0x0F) >= 10) {
595 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
597 spd_ddr_init_hang ();
600 cycle_time_ns_x_10
[cas_index
] =
601 (((tcyc_reg
& 0xF0) >> 4) * 10) + (tcyc_reg
& 0x0F);
606 if ((cas_bit
& 0x80) != 0) {
608 } else if ((cas_bit
& 0x40) != 0) {
610 } else if ((cas_bit
& 0x20) != 0) {
614 if (((cas_bit
& 0x10) != 0) && (cas_index
< 3)) {
615 tcyc_3_0_ns_x_10
= cycle_time_ns_x_10
[cas_index
];
618 if (cas_index
!= 0) {
621 cas_3_0_available
= false;
624 if (((cas_bit
& 0x08) != 0) || (cas_index
< 3)) {
625 tcyc_2_5_ns_x_10
= cycle_time_ns_x_10
[cas_index
];
628 if (cas_index
!= 0) {
631 cas_2_5_available
= false;
634 if (((cas_bit
& 0x04) != 0) || (cas_index
< 3)) {
635 tcyc_2_0_ns_x_10
= cycle_time_ns_x_10
[cas_index
];
638 if (cas_index
!= 0) {
641 cas_2_0_available
= false;
649 * Program SD_WR and SD_WCSBC fields
651 tr0
|= SDRAM_TR0_SDWR_2_CLK
; /* Write Recovery: 2 CLK */
654 tr0
|= SDRAM_TR0_SDWD_0_CLK
;
657 tr0
|= SDRAM_TR0_SDWD_1_CLK
;
662 * Program SD_CASL field
664 if ((cas_2_0_available
== true) &&
665 (bus_period_x_10
>= tcyc_2_0_ns_x_10
)) {
666 tr0
|= SDRAM_TR0_SDCL_2_0_CLK
;
667 } else if ((cas_2_5_available
== true) &&
668 (bus_period_x_10
>= tcyc_2_5_ns_x_10
)) {
669 tr0
|= SDRAM_TR0_SDCL_2_5_CLK
;
670 } else if ((cas_3_0_available
== true) &&
671 (bus_period_x_10
>= tcyc_3_0_ns_x_10
)) {
672 tr0
|= SDRAM_TR0_SDCL_3_0_CLK
;
674 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
675 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
676 printf("Make sure the PLB speed is within the supported range.\n");
677 spd_ddr_init_hang ();
681 * Calculate Trp in clock cycles and round up if necessary
682 * Program SD_PTA field
684 t_rp_clk
= sys_info
.freqPLB
* t_rp_ns
/ ONE_BILLION
;
685 plb_check
= ONE_BILLION
* t_rp_clk
/ t_rp_ns
;
686 if (sys_info
.freqPLB
!= plb_check
) {
689 switch ((unsigned long)t_rp_clk
) {
693 tr0
|= SDRAM_TR0_SDPA_2_CLK
;
696 tr0
|= SDRAM_TR0_SDPA_3_CLK
;
699 tr0
|= SDRAM_TR0_SDPA_4_CLK
;
704 * Program SD_CTP field
706 t_ras_rcd_clk
= sys_info
.freqPLB
* (t_ras_ns
- t_rcd_ns
) / ONE_BILLION
;
707 plb_check
= ONE_BILLION
* t_ras_rcd_clk
/ (t_ras_ns
- t_rcd_ns
);
708 if (sys_info
.freqPLB
!= plb_check
) {
711 switch (t_ras_rcd_clk
) {
715 tr0
|= SDRAM_TR0_SDCP_2_CLK
;
718 tr0
|= SDRAM_TR0_SDCP_3_CLK
;
721 tr0
|= SDRAM_TR0_SDCP_4_CLK
;
724 tr0
|= SDRAM_TR0_SDCP_5_CLK
;
729 * Program SD_LDF field
731 tr0
|= SDRAM_TR0_SDLD_2_CLK
;
734 * Program SD_RFTA field
735 * FIXME tRFC hardcoded as 75 nanoseconds
737 t_rfc_clk
= sys_info
.freqPLB
/ (ONE_BILLION
/ 75);
738 residue
= sys_info
.freqPLB
% (ONE_BILLION
/ 75);
739 if (residue
>= (ONE_BILLION
/ 150)) {
750 tr0
|= SDRAM_TR0_SDRA_6_CLK
;
753 tr0
|= SDRAM_TR0_SDRA_7_CLK
;
756 tr0
|= SDRAM_TR0_SDRA_8_CLK
;
759 tr0
|= SDRAM_TR0_SDRA_9_CLK
;
762 tr0
|= SDRAM_TR0_SDRA_10_CLK
;
765 tr0
|= SDRAM_TR0_SDRA_11_CLK
;
768 tr0
|= SDRAM_TR0_SDRA_12_CLK
;
771 tr0
|= SDRAM_TR0_SDRA_13_CLK
;
776 * Program SD_RCD field
778 t_rcd_clk
= sys_info
.freqPLB
* t_rcd_ns
/ ONE_BILLION
;
779 plb_check
= ONE_BILLION
* t_rcd_clk
/ t_rcd_ns
;
780 if (sys_info
.freqPLB
!= plb_check
) {
787 tr0
|= SDRAM_TR0_SDRD_2_CLK
;
790 tr0
|= SDRAM_TR0_SDRD_3_CLK
;
793 tr0
|= SDRAM_TR0_SDRD_4_CLK
;
797 debug("tr0: %lx\n", tr0
);
798 mtsdram(SDRAM0_TR0
, tr0
);
801 static int short_mem_test(void)
804 unsigned long bxcr_num
;
805 unsigned long *membase
;
806 const unsigned long test
[NUMMEMTESTS
][NUMMEMWORDS
] = {
807 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
808 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
809 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
810 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
811 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
812 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
813 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
814 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
815 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
816 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
817 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
818 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
819 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
820 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
821 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
822 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
824 for (bxcr_num
= 0; bxcr_num
< MAXBXCR
; bxcr_num
++) {
825 mtdcr(SDRAM0_CFGADDR
, SDRAM0_B0CR
+ (bxcr_num
<< 2));
826 if ((mfdcr(SDRAM0_CFGDATA
) & SDRAM_BXCR_SDBE
) == SDRAM_BXCR_SDBE
) {
827 /* Bank is enabled */
828 membase
= (unsigned long*)
829 (mfdcr(SDRAM0_CFGDATA
) & SDRAM_BXCR_SDBA_MASK
);
832 * Run the short memory test
834 for (i
= 0; i
< NUMMEMTESTS
; i
++) {
835 for (j
= 0; j
< NUMMEMWORDS
; j
++) {
836 /* printf("bank enabled base:%x\n", &membase[j]); */
837 membase
[j
] = test
[i
][j
];
838 ppcDcbf((unsigned long)&(membase
[j
]));
841 for (j
= 0; j
< NUMMEMWORDS
; j
++) {
842 if (membase
[j
] != test
[i
][j
]) {
843 ppcDcbf((unsigned long)&(membase
[j
]));
846 ppcDcbf((unsigned long)&(membase
[j
]));
854 * see if the rdclt value passed
864 static void program_tr1(void)
869 unsigned long ecc_temp
;
870 unsigned long dlycal
;
871 unsigned long dly_val
;
873 unsigned long max_pass_length
;
874 unsigned long current_pass_length
;
875 unsigned long current_fail_length
;
876 unsigned long current_start
;
878 unsigned long rdclt_offset
;
882 unsigned char window_found
;
883 unsigned char fail_found
;
884 unsigned char pass_found
;
885 PPC4xx_SYS_INFO sys_info
;
890 get_sys_info(&sys_info
);
893 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
895 mfsdram(SDRAM0_TR1
, tr1
);
896 tr1
&= ~(SDRAM_TR1_RDSS_MASK
| SDRAM_TR1_RDSL_MASK
|
897 SDRAM_TR1_RDCD_MASK
| SDRAM_TR1_RDCT_MASK
);
899 mfsdram(SDRAM0_TR0
, tr0
);
900 if (((tr0
& SDRAM_TR0_SDCL_MASK
) == SDRAM_TR0_SDCL_2_5_CLK
) &&
901 (sys_info
.freqPLB
> 100000000)) {
902 tr1
|= SDRAM_TR1_RDSS_TR2
;
903 tr1
|= SDRAM_TR1_RDSL_STAGE3
;
904 tr1
|= SDRAM_TR1_RDCD_RCD_1_2
;
906 tr1
|= SDRAM_TR1_RDSS_TR1
;
907 tr1
|= SDRAM_TR1_RDSL_STAGE2
;
908 tr1
|= SDRAM_TR1_RDCD_RCD_0_0
;
912 * save CFG0 ECC setting to a temporary variable and turn ECC off
914 mfsdram(SDRAM0_CFG0
, cfg0
);
915 ecc_temp
= cfg0
& SDRAM_CFG0_MCHK_MASK
;
916 mtsdram(SDRAM0_CFG0
, (cfg0
& ~SDRAM_CFG0_MCHK_MASK
) | SDRAM_CFG0_MCHK_NON
);
919 * get the delay line calibration register value
921 mfsdram(SDRAM0_DLYCAL
, dlycal
);
922 dly_val
= SDRAM_DLYCAL_DLCV_DECODE(dlycal
) << 2;
927 current_pass_length
= 0;
928 current_fail_length
= 0;
931 window_found
= false;
934 debug("Starting memory test ");
936 for (k
= 0; k
< NUMHALFCYCLES
; k
++) {
937 for (rdclt
= 0; rdclt
< dly_val
; rdclt
++) {
939 * Set the timing reg for the test.
941 mtsdram(SDRAM0_TR1
, (tr1
| SDRAM_TR1_RDCT_ENCODE(rdclt
)));
943 if (short_mem_test()) {
944 if (fail_found
== true) {
946 if (current_pass_length
== 0) {
947 current_start
= rdclt_offset
+ rdclt
;
950 current_fail_length
= 0;
951 current_pass_length
++;
953 if (current_pass_length
> max_pass_length
) {
954 max_pass_length
= current_pass_length
;
955 max_start
= current_start
;
956 max_end
= rdclt_offset
+ rdclt
;
960 current_pass_length
= 0;
961 current_fail_length
++;
963 if (current_fail_length
>= (dly_val
>>2)) {
964 if (fail_found
== false) {
966 } else if (pass_found
== true) {
975 if (window_found
== true)
978 tr1
= tr1
^ SDRAM_TR1_RDCD_MASK
;
979 rdclt_offset
+= dly_val
;
984 * make sure we find the window
986 if (window_found
== false) {
987 printf("ERROR: Cannot determine a common read delay.\n");
988 spd_ddr_init_hang ();
992 * restore the orignal ECC setting
994 mtsdram(SDRAM0_CFG0
, (cfg0
& ~SDRAM_CFG0_MCHK_MASK
) | ecc_temp
);
997 * set the SDRAM TR1 RDCD value
999 tr1
&= ~SDRAM_TR1_RDCD_MASK
;
1000 if ((tr0
& SDRAM_TR0_SDCL_MASK
) == SDRAM_TR0_SDCL_2_5_CLK
) {
1001 tr1
|= SDRAM_TR1_RDCD_RCD_1_2
;
1003 tr1
|= SDRAM_TR1_RDCD_RCD_0_0
;
1007 * set the SDRAM TR1 RDCLT value
1009 tr1
&= ~SDRAM_TR1_RDCT_MASK
;
1010 while (max_end
>= (dly_val
<< 1)) {
1011 max_end
-= (dly_val
<< 1);
1012 max_start
-= (dly_val
<< 1);
1015 rdclt_average
= ((max_start
+ max_end
) >> 1);
1017 if (rdclt_average
< 0) {
1021 if (rdclt_average
>= dly_val
) {
1022 rdclt_average
-= dly_val
;
1023 tr1
= tr1
^ SDRAM_TR1_RDCD_MASK
;
1025 tr1
|= SDRAM_TR1_RDCT_ENCODE(rdclt_average
);
1027 debug("tr1: %lx\n", tr1
);
1030 * program SDRAM Timing Register 1 TR1
1032 mtsdram(SDRAM0_TR1
, tr1
);
1035 static unsigned long program_bxcr(unsigned long *dimm_populated
,
1036 unsigned char *iic0_dimm_addr
,
1037 unsigned long num_dimm_banks
)
1039 unsigned long dimm_num
;
1040 unsigned long bank_base_addr
;
1045 unsigned char num_row_addr
;
1046 unsigned char num_col_addr
;
1047 unsigned char num_banks
;
1048 unsigned char bank_size_id
;
1049 unsigned long ctrl_bank_num
[MAXBANKS
];
1050 unsigned long bx_cr_num
;
1051 unsigned long largest_size_index
;
1052 unsigned long largest_size
;
1053 unsigned long current_size_index
;
1054 BANKPARMS bank_parms
[MAXBXCR
];
1055 unsigned long sorted_bank_num
[MAXBXCR
]; /* DDR Controller bank number table (sorted by size) */
1056 unsigned long sorted_bank_size
[MAXBXCR
]; /* DDR Controller bank size table (sorted by size)*/
1059 * Set the BxCR regs. First, wipe out the bank config registers.
1061 for (bx_cr_num
= 0; bx_cr_num
< MAXBXCR
; bx_cr_num
++) {
1062 mtdcr(SDRAM0_CFGADDR
, SDRAM0_B0CR
+ (bx_cr_num
<< 2));
1063 mtdcr(SDRAM0_CFGDATA
, 0x00000000);
1064 bank_parms
[bx_cr_num
].bank_size_bytes
= 0;
1067 #ifdef CONFIG_BAMBOO
1069 * This next section is hardware dependent and must be programmed
1070 * to match the hardware. For bamboo, the following holds...
1071 * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1072 * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1073 * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1074 * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1075 * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1077 ctrl_bank_num
[0] = 0;
1078 ctrl_bank_num
[1] = 1;
1079 ctrl_bank_num
[2] = 3;
1082 * Ocotea, Ebony and the other IBM/AMCC eval boards have
1083 * 2 DIMM slots with each max 2 banks
1085 ctrl_bank_num
[0] = 0;
1086 ctrl_bank_num
[1] = 2;
1090 * reset the bank_base address
1092 bank_base_addr
= CONFIG_SYS_SDRAM_BASE
;
1094 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
1095 if (dimm_populated
[dimm_num
] == true) {
1096 num_row_addr
= spd_read(iic0_dimm_addr
[dimm_num
], 3);
1097 num_col_addr
= spd_read(iic0_dimm_addr
[dimm_num
], 4);
1098 num_banks
= spd_read(iic0_dimm_addr
[dimm_num
], 5);
1099 bank_size_id
= spd_read(iic0_dimm_addr
[dimm_num
], 31);
1100 debug("DIMM%ld: row=%d col=%d banks=%d\n", dimm_num
,
1101 num_row_addr
, num_col_addr
, num_banks
);
1104 * Set the SDRAM0_BxCR regs
1107 switch (bank_size_id
) {
1109 cr
|= SDRAM_BXCR_SDSZ_8
;
1112 cr
|= SDRAM_BXCR_SDSZ_16
;
1115 cr
|= SDRAM_BXCR_SDSZ_32
;
1118 cr
|= SDRAM_BXCR_SDSZ_64
;
1121 cr
|= SDRAM_BXCR_SDSZ_128
;
1124 cr
|= SDRAM_BXCR_SDSZ_256
;
1127 cr
|= SDRAM_BXCR_SDSZ_512
;
1130 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1132 printf("ERROR: Unsupported value for the banksize: %d.\n",
1134 printf("Replace the DIMM module with a supported DIMM.\n\n");
1135 spd_ddr_init_hang ();
1138 switch (num_col_addr
) {
1140 cr
|= SDRAM_BXCR_SDAM_1
;
1143 cr
|= SDRAM_BXCR_SDAM_2
;
1146 cr
|= SDRAM_BXCR_SDAM_3
;
1149 cr
|= SDRAM_BXCR_SDAM_4
;
1152 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1154 printf("ERROR: Unsupported value for number of "
1155 "column addresses: %d.\n", num_col_addr
);
1156 printf("Replace the DIMM module with a supported DIMM.\n\n");
1157 spd_ddr_init_hang ();
1163 cr
|= SDRAM_BXCR_SDBE
;
1165 for (i
= 0; i
< num_banks
; i
++) {
1166 bank_parms
[ctrl_bank_num
[dimm_num
]+i
].bank_size_bytes
=
1167 (4 << 20) * bank_size_id
;
1168 bank_parms
[ctrl_bank_num
[dimm_num
]+i
].cr
= cr
;
1169 debug("DIMM%ld-bank %ld (SDRAM0_B%ldCR): "
1170 "bank_size_bytes=%ld\n",
1172 ctrl_bank_num
[dimm_num
] + i
,
1173 bank_parms
[ctrl_bank_num
[dimm_num
] + i
].bank_size_bytes
);
1178 /* Initialize sort tables */
1179 for (i
= 0; i
< MAXBXCR
; i
++) {
1180 sorted_bank_num
[i
] = i
;
1181 sorted_bank_size
[i
] = bank_parms
[i
].bank_size_bytes
;
1184 for (i
= 0; i
< MAXBXCR
-1; i
++) {
1185 largest_size
= sorted_bank_size
[i
];
1186 largest_size_index
= 255;
1188 /* Find the largest remaining value */
1189 for (j
= i
+ 1; j
< MAXBXCR
; j
++) {
1190 if (sorted_bank_size
[j
] > largest_size
) {
1191 /* Save largest remaining value and its index */
1192 largest_size
= sorted_bank_size
[j
];
1193 largest_size_index
= j
;
1197 if (largest_size_index
!= 255) {
1198 /* Swap the current and largest values */
1199 current_size_index
= sorted_bank_num
[largest_size_index
];
1200 sorted_bank_size
[largest_size_index
] = sorted_bank_size
[i
];
1201 sorted_bank_size
[i
] = largest_size
;
1202 sorted_bank_num
[largest_size_index
] = sorted_bank_num
[i
];
1203 sorted_bank_num
[i
] = current_size_index
;
1207 /* Set the SDRAM0_BxCR regs thanks to sort tables */
1208 for (bx_cr_num
= 0, bank_base_addr
= 0; bx_cr_num
< MAXBXCR
; bx_cr_num
++) {
1209 if (bank_parms
[sorted_bank_num
[bx_cr_num
]].bank_size_bytes
) {
1210 mtdcr(SDRAM0_CFGADDR
, SDRAM0_B0CR
+ (sorted_bank_num
[bx_cr_num
] << 2));
1211 temp
= mfdcr(SDRAM0_CFGDATA
) & ~(SDRAM_BXCR_SDBA_MASK
| SDRAM_BXCR_SDSZ_MASK
|
1212 SDRAM_BXCR_SDAM_MASK
| SDRAM_BXCR_SDBE
);
1213 temp
= temp
| (bank_base_addr
& SDRAM_BXCR_SDBA_MASK
) |
1214 bank_parms
[sorted_bank_num
[bx_cr_num
]].cr
;
1215 mtdcr(SDRAM0_CFGDATA
, temp
);
1216 bank_base_addr
+= bank_parms
[sorted_bank_num
[bx_cr_num
]].bank_size_bytes
;
1217 debug("SDRAM0_B%ldCR=0x%08lx\n",
1218 sorted_bank_num
[bx_cr_num
], temp
);
1222 return(bank_base_addr
);
1224 #endif /* CONFIG_SPD_EEPROM */