2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/ppc4xx-emac.h>
27 #include <asm/processor.h>
28 #include <asm/ppc4xx-gpio.h>
29 #include <asm/ppc4xx.h>
31 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
32 DECLARE_GLOBAL_DATA_PTR
;
35 #ifndef CONFIG_SYS_PLL_RECONFIG
36 #define CONFIG_SYS_PLL_RECONFIG 0
39 #if defined(CONFIG_440EPX) || \
40 defined(CONFIG_460EX) || defined(CONFIG_460GT)
41 static void reset_with_rli(void)
46 * Set reload inhibit so configuration will persist across
49 mfcpr(CPR0_ICFG
, reg
);
50 reg
|= CPR0_ICFG_RLI_MASK
;
51 mtcpr(CPR0_ICFG
, reg
);
53 /* Reset processor if configuration changed */
54 __asm__
__volatile__ ("sync; isync");
55 mtspr(SPRN_DBCR0
, 0x20000000);
59 void reconfigure_pll(u32 new_cpu_freq
)
61 #if defined(CONFIG_440EPX)
64 u32 prbdv0
, target_prbdv0
, /* CLK_PRIMBD */
65 fwdva
, target_fwdva
, fwdvb
, target_fwdvb
, /* CLK_PLLD */
66 fbdv
, target_fbdv
, lfbdv
, target_lfbdv
,
67 perdv0
, target_perdv0
, /* CLK_PERD */
68 spcid0
, target_spcid0
; /* CLK_SPCID */
70 /* Reconfigure clocks if necessary.
71 * See PPC440EPx User's Manual, sections 8.2 and 14 */
72 if (new_cpu_freq
== 667) {
81 mfcpr(CPR0_PRIMBD0
, reg
);
82 temp
= (reg
& PRBDV_MASK
) >> 24;
83 prbdv0
= temp
? temp
: 8;
84 if (prbdv0
!= target_prbdv0
) {
86 reg
|= ((target_prbdv0
== 8 ? 0 : target_prbdv0
) << 24);
87 mtcpr(CPR0_PRIMBD0
, reg
);
91 mfcpr(CPR0_PLLD
, reg
);
93 temp
= (reg
& PLLD_FWDVA_MASK
) >> 16;
94 fwdva
= temp
? temp
: 16;
96 temp
= (reg
& PLLD_FWDVB_MASK
) >> 8;
97 fwdvb
= temp
? temp
: 8;
99 temp
= (reg
& PLLD_FBDV_MASK
) >> 24;
100 fbdv
= temp
? temp
: 32;
102 temp
= (reg
& PLLD_LFBDV_MASK
);
103 lfbdv
= temp
? temp
: 64;
105 if (fwdva
!= target_fwdva
|| fbdv
!= target_fbdv
|| lfbdv
!= target_lfbdv
) {
106 reg
&= ~(PLLD_FWDVA_MASK
| PLLD_FWDVB_MASK
|
107 PLLD_FBDV_MASK
| PLLD_LFBDV_MASK
);
108 reg
|= ((target_fwdva
== 16 ? 0 : target_fwdva
) << 16) |
109 ((target_fwdvb
== 8 ? 0 : target_fwdvb
) << 8) |
110 ((target_fbdv
== 32 ? 0 : target_fbdv
) << 24) |
111 (target_lfbdv
== 64 ? 0 : target_lfbdv
);
112 mtcpr(CPR0_PLLD
, reg
);
116 mfcpr(CPR0_PERD
, reg
);
117 perdv0
= (reg
& CPR0_PERD_PERDV0_MASK
) >> 24;
118 if (perdv0
!= target_perdv0
) {
119 reg
&= ~CPR0_PERD_PERDV0_MASK
;
120 reg
|= (target_perdv0
<< 24);
121 mtcpr(CPR0_PERD
, reg
);
125 mfcpr(CPR0_SPCID
, reg
);
126 temp
= (reg
& CPR0_SPCID_SPCIDV0_MASK
) >> 24;
127 spcid0
= temp
? temp
: 4;
128 if (spcid0
!= target_spcid0
) {
129 reg
&= ~CPR0_SPCID_SPCIDV0_MASK
;
130 reg
|= ((target_spcid0
== 4 ? 0 : target_spcid0
) << 24);
131 mtcpr(CPR0_SPCID
, reg
);
136 /* Get current value of FWDVA.*/
137 mfcpr(CPR0_PLLD
, reg
);
138 temp
= (reg
& PLLD_FWDVA_MASK
) >> 16;
141 * Check to see if FWDVA has been set to value of 1. if it has we must
146 * Load register that contains current boot strapping option.
148 mfcpr(CPR0_ICFG
, reg
);
150 * Strapping option bits (ICS) are already in correct position,
151 * only masking needed.
153 reg
&= CPR0_ICFG_ICS_MASK
;
155 if ((reg
== BOOT_STRAP_OPTION_A
) || (reg
== BOOT_STRAP_OPTION_B
) ||
156 (reg
== BOOT_STRAP_OPTION_D
) || (reg
== BOOT_STRAP_OPTION_E
)) {
157 mfcpr(CPR0_PLLD
, reg
);
159 /* Get current value of fbdv. */
160 temp
= (reg
& PLLD_FBDV_MASK
) >> 24;
161 fbdv
= temp
? temp
: 32;
163 /* Get current value of lfbdv. */
164 temp
= (reg
& PLLD_LFBDV_MASK
);
165 lfbdv
= temp
? temp
: 64;
168 * Get current value of FWDVA. Assign current FWDVA to
171 mfcpr(CPR0_PLLD
, reg
);
172 target_fwdvb
= (reg
& PLLD_FWDVA_MASK
) >> 16;
173 fwdvb
= target_fwdvb
? target_fwdvb
: 8;
176 * Get current value of FWDVB. Assign current FWDVB to
179 target_fwdva
= (reg
& PLLD_FWDVB_MASK
) >> 8;
180 fwdva
= target_fwdva
? target_fwdva
: 16;
183 * Update CPR0_PLLD with switched FWDVA and FWDVB.
185 reg
&= ~(PLLD_FWDVA_MASK
| PLLD_FWDVB_MASK
|
186 PLLD_FBDV_MASK
| PLLD_LFBDV_MASK
);
187 reg
|= ((fwdva
== 16 ? 0 : fwdva
) << 16) |
188 ((fwdvb
== 8 ? 0 : fwdvb
) << 8) |
189 ((fbdv
== 32 ? 0 : fbdv
) << 24) |
190 (lfbdv
== 64 ? 0 : lfbdv
);
191 mtcpr(CPR0_PLLD
, reg
);
193 /* Acknowledge that a reset is required. */
198 /* Now reset the CPU if needed */
203 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
207 * See "9.2.1.1 Booting with Option E" in the 460EX/GT
210 mfcpr(CPR0_PLLC
, reg
);
211 if ((reg
& (CPR0_PLLC_RST
| CPR0_PLLC_ENG
)) == CPR0_PLLC_RST
) {
215 reg
= (reg
& ~CPR0_PLLC_RST
) | CPR0_PLLC_ENG
;
216 mtcpr(CPR0_PLLC
, reg
);
218 /* Now reset the CPU */
225 * Breath some life into the CPU...
227 * Reconfigure PLL if necessary,
228 * set up the memory map,
229 * initialize a bunch of registers
234 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
238 reconfigure_pll(CONFIG_SYS_PLL_RECONFIG
);
240 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
241 !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
243 * GPIO0 setup (select GPIO or alternate function)
245 #if defined(CONFIG_SYS_GPIO0_OR)
246 out32(GPIO0_OR
, CONFIG_SYS_GPIO0_OR
); /* set initial state of output pins */
248 #if defined(CONFIG_SYS_GPIO0_ODR)
249 out32(GPIO0_ODR
, CONFIG_SYS_GPIO0_ODR
); /* open-drain select */
251 out32(GPIO0_OSRH
, CONFIG_SYS_GPIO0_OSRH
); /* output select */
252 out32(GPIO0_OSRL
, CONFIG_SYS_GPIO0_OSRL
);
253 out32(GPIO0_ISR1H
, CONFIG_SYS_GPIO0_ISR1H
); /* input select */
254 out32(GPIO0_ISR1L
, CONFIG_SYS_GPIO0_ISR1L
);
255 out32(GPIO0_TSRH
, CONFIG_SYS_GPIO0_TSRH
); /* three-state select */
256 out32(GPIO0_TSRL
, CONFIG_SYS_GPIO0_TSRL
);
257 #if defined(CONFIG_SYS_GPIO0_ISR2H)
258 out32(GPIO0_ISR2H
, CONFIG_SYS_GPIO0_ISR2H
);
259 out32(GPIO0_ISR2L
, CONFIG_SYS_GPIO0_ISR2L
);
261 #if defined (CONFIG_SYS_GPIO0_TCR)
262 out32(GPIO0_TCR
, CONFIG_SYS_GPIO0_TCR
); /* enable output driver for outputs */
264 #endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
266 #if defined (CONFIG_405EP)
268 * Set EMAC noise filter bits
270 mtdcr(CPC0_EPCTL
, CPC0_EPCTL_E0NFE
| CPC0_EPCTL_E1NFE
);
271 #endif /* CONFIG_405EP */
273 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
274 gpio_set_chip_configuration();
275 #endif /* CONFIG_SYS_4xx_GPIO_TABLE */
278 * External Bus Controller (EBC) Setup
280 #if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
281 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
282 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
283 defined(CONFIG_405EX) || defined(CONFIG_405))
285 * Move the next instructions into icache, since these modify the flash
286 * we are running from!
288 asm volatile(" bl 0f" ::: "lr");
289 asm volatile("0: mflr 3" ::: "r3");
290 asm volatile(" addi 4, 0, 14" ::: "r4");
291 asm volatile(" mtctr 4" ::: "ctr");
292 asm volatile("1: icbt 0, 3");
293 asm volatile(" addi 3, 3, 32" ::: "r3");
294 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
295 asm volatile(" addis 3, 0, 0x0" ::: "r3");
296 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
297 asm volatile(" mtctr 3" ::: "ctr");
298 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
301 mtebc(PB0AP
, CONFIG_SYS_EBC_PB0AP
);
302 mtebc(PB0CR
, CONFIG_SYS_EBC_PB0CR
);
305 #if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
306 mtebc(PB1AP
, CONFIG_SYS_EBC_PB1AP
);
307 mtebc(PB1CR
, CONFIG_SYS_EBC_PB1CR
);
310 #if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
311 mtebc(PB2AP
, CONFIG_SYS_EBC_PB2AP
);
312 mtebc(PB2CR
, CONFIG_SYS_EBC_PB2CR
);
315 #if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
316 mtebc(PB3AP
, CONFIG_SYS_EBC_PB3AP
);
317 mtebc(PB3CR
, CONFIG_SYS_EBC_PB3CR
);
320 #if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
321 mtebc(PB4AP
, CONFIG_SYS_EBC_PB4AP
);
322 mtebc(PB4CR
, CONFIG_SYS_EBC_PB4CR
);
325 #if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
326 mtebc(PB5AP
, CONFIG_SYS_EBC_PB5AP
);
327 mtebc(PB5CR
, CONFIG_SYS_EBC_PB5CR
);
330 #if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
331 mtebc(PB6AP
, CONFIG_SYS_EBC_PB6AP
);
332 mtebc(PB6CR
, CONFIG_SYS_EBC_PB6CR
);
335 #if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
336 mtebc(PB7AP
, CONFIG_SYS_EBC_PB7AP
);
337 mtebc(PB7CR
, CONFIG_SYS_EBC_PB7CR
);
340 #if defined (CONFIG_SYS_EBC_CFG)
341 mtebc(EBC0_CFG
, CONFIG_SYS_EBC_CFG
);
344 #if defined(CONFIG_WATCHDOG)
345 val
= mfspr(SPRN_TCR
);
346 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
347 val
|= 0xb8000000; /* generate system reset after 1.34 seconds */
348 #elif defined(CONFIG_440EPX)
349 val
|= 0xb0000000; /* generate system reset after 1.34 seconds */
351 val
|= 0xf0000000; /* generate system reset after 2.684 seconds */
353 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
354 val
&= ~0x30000000; /* clear WRC bits */
355 val
|= CONFIG_SYS_4xx_RESET_TYPE
<< 28; /* set board specific WRC type */
357 mtspr(SPRN_TCR
, val
);
359 val
= mfspr(SPRN_TSR
);
360 val
|= 0x80000000; /* enable watchdog timer */
361 mtspr(SPRN_TSR
, val
);
363 reset_4xx_watchdog();
364 #endif /* CONFIG_WATCHDOG */
366 #if defined(CONFIG_440GX)
367 /* Take the GX out of compatibility mode
368 * Travis Sawyer, 9 Mar 2004
369 * NOTE: 440gx user manual inconsistency here
370 * Compatibility mode and Ethernet Clock select are not
371 * correct in the manual
373 mfsdr(SDR0_MFR
, val
);
376 #endif /* CONFIG_440GX */
378 #if defined(CONFIG_460EX)
380 * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
381 * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
382 * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
384 mfsdr(SDR0_AHB_CFG
, val
);
387 mtsdr(SDR0_AHB_CFG
, val
);
388 mfsdr(SDR0_USB2HOST_CFG
, val
);
391 mtsdr(SDR0_USB2HOST_CFG
, val
);
392 #endif /* CONFIG_460EX */
394 #if defined(CONFIG_405EX) || \
395 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
396 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
397 defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
399 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
401 mtdcr(PLB4A0_ACR
, (mfdcr(PLB4A0_ACR
) & ~PLB4Ax_ACR_RDP_MASK
) |
402 PLB4Ax_ACR_RDP_4DEEP
);
403 mtdcr(PLB4A1_ACR
, (mfdcr(PLB4A1_ACR
) & ~PLB4Ax_ACR_RDP_MASK
) |
404 PLB4Ax_ACR_RDP_4DEEP
);
405 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
409 * initialize higher level parts of CPU like time base and timers
411 int cpu_init_r (void)
413 #if defined(CONFIG_405GP)
414 uint pvr
= get_pvr();
417 * Set edge conditioning circuitry on PPC405GPr
418 * for compatibility to existing PPC405GP designs.
420 if ((pvr
& 0xfffffff0) == (PVR_405GPR_RB
& 0xfffffff0)) {
421 mtdcr(CPC0_ECR
, 0x60606000);
423 #endif /* defined(CONFIG_405GP) */
428 #if defined(CONFIG_PCI) && \
429 (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
430 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
432 * 440EP(x)/GR(x) PCI async/sync clocking restriction:
434 * In asynchronous PCI mode, the synchronous PCI clock must meet
435 * certain requirements. The following equation describes the
436 * relationship that must be maintained between the asynchronous PCI
437 * clock and synchronous PCI clock. Select an appropriate PCI:PLB
438 * ratio to maintain the relationship:
440 * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
442 static int ppc4xx_pci_sync_clock_ok(u32 sync
, u32 async
)
444 if (((async
- 1000000) > sync
) || (sync
> ((2 * async
) - 1000000)))
450 int ppc4xx_pci_sync_clock_config(u32 async
)
457 CPR0_SPCID_SPCIDV0_DIV1
, CPR0_SPCID_SPCIDV0_DIV2
,
458 CPR0_SPCID_SPCIDV0_DIV3
, CPR0_SPCID_SPCIDV0_DIV4
};
460 get_sys_info(&sys_info
);
461 sync
= sys_info
.freqPCI
;
464 * First check if the equation above is met
466 if (!ppc4xx_pci_sync_clock_ok(sync
, async
)) {
468 * Reconfigure PCI sync clock to meet the equation.
469 * Start with highest possible PCI sync frequency
472 for (div
= 1; div
<= 4; div
++) {
473 sync
= sys_info
.freqPLB
/ div
;
474 if (ppc4xx_pci_sync_clock_ok(sync
, async
))
479 mtcpr(CPR0_SPCID
, spcid_val
[div
]);
481 mfcpr(CPR0_ICFG
, reg
);
482 reg
|= CPR0_ICFG_RLI_MASK
;
483 mtcpr(CPR0_ICFG
, reg
);
486 mtspr(SPRN_DBCR0
, 0x20000000);
488 /* Impossible to configure the PCI sync clock */