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powerpc: Drop unused code related to generic board
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / start.S
1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
10 */
11
12 /*
13 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
14 *
15 * The following description only applies to the NOR flash style booting.
16 * NAND booting is different. For more details about NAND booting on 4xx
17 * take a look at doc/README.nand-boot-ppc440.
18 *
19 * The CPU starts at address 0xfffffffc (last word in the address space).
20 * The U-Boot image therefore has to be located in the "upper" area of the
21 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
22 * the boot chip-select (CS0) is quite big and covers this area. On the
23 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
24 * reconfigure this CS0 (and other chip-selects as well when configured
25 * this way) in the boot process to the "correct" values matching the
26 * board layout.
27 */
28
29 #include <asm-offsets.h>
30 #include <config.h>
31 #include <asm/ppc4xx.h>
32 #include <version.h>
33
34 #include <ppc_asm.tmpl>
35 #include <ppc_defs.h>
36
37 #include <asm/cache.h>
38 #include <asm/mmu.h>
39 #include <asm/ppc4xx-isram.h>
40
41 #ifdef CONFIG_SYS_INIT_DCACHE_CS
42 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
43 # define PBxAP PB1AP
44 # define PBxCR PB0CR
45 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
46 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
47 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
48 # endif
49 # endif
50 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
51 # define PBxAP PB1AP
52 # define PBxCR PB1CR
53 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
54 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
55 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
56 # endif
57 # endif
58 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
59 # define PBxAP PB2AP
60 # define PBxCR PB2CR
61 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
62 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
63 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
64 # endif
65 # endif
66 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
67 # define PBxAP PB3AP
68 # define PBxCR PB3CR
69 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
70 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
71 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
72 # endif
73 # endif
74 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
75 # define PBxAP PB4AP
76 # define PBxCR PB4CR
77 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
78 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
79 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
80 # endif
81 # endif
82 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
83 # define PBxAP PB5AP
84 # define PBxCR PB5CR
85 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
86 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
87 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
88 # endif
89 # endif
90 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
91 # define PBxAP PB6AP
92 # define PBxCR PB6CR
93 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
94 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
95 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
96 # endif
97 # endif
98 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
99 # define PBxAP PB7AP
100 # define PBxCR PB7CR
101 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
102 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
103 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
104 # endif
105 # endif
106 # ifndef PBxAP_VAL
107 # define PBxAP_VAL 0
108 # endif
109 # ifndef PBxCR_VAL
110 # define PBxCR_VAL 0
111 # endif
112 /*
113 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
114 * used as temporary stack pointer for the primordial stack
115 */
116 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
117 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
118 EBC_BXAP_TWT_ENCODE(7) | \
119 EBC_BXAP_BCE_DISABLE | \
120 EBC_BXAP_BCT_2TRANS | \
121 EBC_BXAP_CSN_ENCODE(0) | \
122 EBC_BXAP_OEN_ENCODE(0) | \
123 EBC_BXAP_WBN_ENCODE(0) | \
124 EBC_BXAP_WBF_ENCODE(0) | \
125 EBC_BXAP_TH_ENCODE(2) | \
126 EBC_BXAP_RE_DISABLED | \
127 EBC_BXAP_SOR_NONDELAYED | \
128 EBC_BXAP_BEM_WRITEONLY | \
129 EBC_BXAP_PEN_DISABLED)
130 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
131 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
132 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
133 EBC_BXCR_BS_64MB | \
134 EBC_BXCR_BU_RW | \
135 EBC_BXCR_BW_16BIT)
136 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
137 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
138 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
139 # endif
140 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
141
142 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
143 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
144 #endif
145
146 /*
147 * Unless otherwise overriden, enable two 128MB cachable instruction regions
148 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
149 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
150 */
151 #if !defined(CONFIG_SYS_FLASH_BASE)
152 /* If not already defined, set it to the "last" 128MByte region */
153 # define CONFIG_SYS_FLASH_BASE 0xf8000000
154 #endif
155 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
156 # define CONFIG_SYS_ICACHE_SACR_VALUE \
157 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
158 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
159 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
160 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
161
162 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
163 # define CONFIG_SYS_DCACHE_SACR_VALUE \
164 (0x00000000)
165 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
166
167 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
168 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
169 #endif
170
171 #define function_prolog(func_name) .text; \
172 .align 2; \
173 .globl func_name; \
174 func_name:
175 #define function_epilog(func_name) .type func_name,@function; \
176 .size func_name,.-func_name
177
178 /* We don't want the MMU yet.
179 */
180 #undef MSR_KERNEL
181 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
182
183
184 .extern ext_bus_cntlr_init
185
186 /*
187 * Set up GOT: Global Offset Table
188 *
189 * Use r12 to access the GOT
190 */
191 #if !defined(CONFIG_SPL_BUILD)
192 START_GOT
193 GOT_ENTRY(_GOT2_TABLE_)
194 GOT_ENTRY(_FIXUP_TABLE_)
195
196 GOT_ENTRY(_start)
197 GOT_ENTRY(_start_of_vectors)
198 GOT_ENTRY(_end_of_vectors)
199 GOT_ENTRY(transfer_to_handler)
200
201 GOT_ENTRY(__init_end)
202 GOT_ENTRY(__bss_end)
203 GOT_ENTRY(__bss_start)
204 END_GOT
205 #endif /* CONFIG_SPL_BUILD */
206
207 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
208 /*
209 * 4xx RAM-booting U-Boot image is started from offset 0
210 */
211 .text
212 bl _start_440
213 #endif
214
215 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
216 /*
217 * This is the entry of the real U-Boot from a board port
218 * that supports SPL booting on the PPC4xx. We only need
219 * to call board_init_f() here. Everything else has already
220 * been done in the SPL u-boot version.
221 */
222 GET_GOT /* initialize GOT access */
223 bl board_init_f /* run 1st part of board init code (in Flash)*/
224 /* NOTREACHED - board_init_f() does not return */
225 #endif
226
227 /*
228 * 440 Startup -- on reset only the top 4k of the effective
229 * address space is mapped in by an entry in the instruction
230 * and data shadow TLB. The .bootpg section is located in the
231 * top 4k & does only what's necessary to map in the the rest
232 * of the boot rom. Once the boot rom is mapped in we can
233 * proceed with normal startup.
234 *
235 * NOTE: CS0 only covers the top 2MB of the effective address
236 * space after reset.
237 */
238
239 #if defined(CONFIG_440)
240 .section .bootpg,"ax"
241 .globl _start_440
242
243 /**************************************************************************/
244 _start_440:
245 /*--------------------------------------------------------------------+
246 | 440EPX BUP Change - Hardware team request
247 +--------------------------------------------------------------------*/
248 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
249 sync
250 nop
251 nop
252 #endif
253 /*----------------------------------------------------------------+
254 | Core bug fix. Clear the esr
255 +-----------------------------------------------------------------*/
256 li r0,0
257 mtspr SPRN_ESR,r0
258 /*----------------------------------------------------------------*/
259 /* Clear and set up some registers. */
260 /*----------------------------------------------------------------*/
261 iccci r0,r0 /* NOTE: operands not used for 440 */
262 dccci r0,r0 /* NOTE: operands not used for 440 */
263 sync
264 li r0,0
265 mtspr SPRN_SRR0,r0
266 mtspr SPRN_SRR1,r0
267 mtspr SPRN_CSRR0,r0
268 mtspr SPRN_CSRR1,r0
269 /* NOTE: 440GX adds machine check status regs */
270 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
271 mtspr SPRN_MCSRR0,r0
272 mtspr SPRN_MCSRR1,r0
273 mfspr r1,SPRN_MCSR
274 mtspr SPRN_MCSR,r1
275 #endif
276
277 /*----------------------------------------------------------------*/
278 /* CCR0 init */
279 /*----------------------------------------------------------------*/
280 /* Disable store gathering & broadcast, guarantee inst/data
281 * cache block touch, force load/store alignment
282 * (see errata 1.12: 440_33)
283 */
284 lis r1,0x0030 /* store gathering & broadcast disable */
285 ori r1,r1,0x6000 /* cache touch */
286 mtspr SPRN_CCR0,r1
287
288 /*----------------------------------------------------------------*/
289 /* Initialize debug */
290 /*----------------------------------------------------------------*/
291 mfspr r1,SPRN_DBCR0
292 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
293 bne skip_debug_init /* if set, don't clear debug register */
294 mfspr r1,SPRN_CCR0
295 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
296 mtspr SPRN_CCR0,r1
297 mtspr SPRN_DBCR0,r0
298 mtspr SPRN_DBCR1,r0
299 mtspr SPRN_DBCR2,r0
300 mtspr SPRN_IAC1,r0
301 mtspr SPRN_IAC2,r0
302 mtspr SPRN_IAC3,r0
303 mtspr SPRN_DAC1,r0
304 mtspr SPRN_DAC2,r0
305 mtspr SPRN_DVC1,r0
306 mtspr SPRN_DVC2,r0
307
308 mfspr r1,SPRN_DBSR
309 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
310 skip_debug_init:
311
312 #if defined (CONFIG_440SPE)
313 /*----------------------------------------------------------------+
314 | Initialize Core Configuration Reg1.
315 | a. ICDPEI: Record even parity. Normal operation.
316 | b. ICTPEI: Record even parity. Normal operation.
317 | c. DCTPEI: Record even parity. Normal operation.
318 | d. DCDPEI: Record even parity. Normal operation.
319 | e. DCUPEI: Record even parity. Normal operation.
320 | f. DCMPEI: Record even parity. Normal operation.
321 | g. FCOM: Normal operation
322 | h. MMUPEI: Record even parity. Normal operation.
323 | i. FFF: Flush only as much data as necessary.
324 | j. TCS: Timebase increments from CPU clock.
325 +-----------------------------------------------------------------*/
326 li r0,0
327 mtspr SPRN_CCR1, r0
328
329 /*----------------------------------------------------------------+
330 | Reset the timebase.
331 | The previous write to CCR1 sets the timebase source.
332 +-----------------------------------------------------------------*/
333 mtspr SPRN_TBWL, r0
334 mtspr SPRN_TBWU, r0
335 #endif
336
337 /*----------------------------------------------------------------*/
338 /* Setup interrupt vectors */
339 /*----------------------------------------------------------------*/
340 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
341 li r1,0x0100
342 mtspr SPRN_IVOR0,r1 /* Critical input */
343 li r1,0x0200
344 mtspr SPRN_IVOR1,r1 /* Machine check */
345 li r1,0x0300
346 mtspr SPRN_IVOR2,r1 /* Data storage */
347 li r1,0x0400
348 mtspr SPRN_IVOR3,r1 /* Instruction storage */
349 li r1,0x0500
350 mtspr SPRN_IVOR4,r1 /* External interrupt */
351 li r1,0x0600
352 mtspr SPRN_IVOR5,r1 /* Alignment */
353 li r1,0x0700
354 mtspr SPRN_IVOR6,r1 /* Program check */
355 li r1,0x0800
356 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
357 li r1,0x0c00
358 mtspr SPRN_IVOR8,r1 /* System call */
359 li r1,0x0a00
360 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
361 li r1,0x0900
362 mtspr SPRN_IVOR10,r1 /* Decrementer */
363 li r1,0x1300
364 mtspr SPRN_IVOR13,r1 /* Data TLB error */
365 li r1,0x1400
366 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
367 li r1,0x2000
368 mtspr SPRN_IVOR15,r1 /* Debug */
369
370 /*----------------------------------------------------------------*/
371 /* Configure cache regions */
372 /*----------------------------------------------------------------*/
373 mtspr SPRN_INV0,r0
374 mtspr SPRN_INV1,r0
375 mtspr SPRN_INV2,r0
376 mtspr SPRN_INV3,r0
377 mtspr SPRN_DNV0,r0
378 mtspr SPRN_DNV1,r0
379 mtspr SPRN_DNV2,r0
380 mtspr SPRN_DNV3,r0
381 mtspr SPRN_ITV0,r0
382 mtspr SPRN_ITV1,r0
383 mtspr SPRN_ITV2,r0
384 mtspr SPRN_ITV3,r0
385 mtspr SPRN_DTV0,r0
386 mtspr SPRN_DTV1,r0
387 mtspr SPRN_DTV2,r0
388 mtspr SPRN_DTV3,r0
389
390 /*----------------------------------------------------------------*/
391 /* Cache victim limits */
392 /*----------------------------------------------------------------*/
393 /* floors 0, ceiling max to use the entire cache -- nothing locked
394 */
395 lis r1,0x0001
396 ori r1,r1,0xf800
397 mtspr SPRN_IVLIM,r1
398 mtspr SPRN_DVLIM,r1
399
400 /*----------------------------------------------------------------+
401 |Initialize MMUCR[STID] = 0.
402 +-----------------------------------------------------------------*/
403 mfspr r0,SPRN_MMUCR
404 addis r1,0,0xFFFF
405 ori r1,r1,0xFF00
406 and r0,r0,r1
407 mtspr SPRN_MMUCR,r0
408
409 /*----------------------------------------------------------------*/
410 /* Clear all TLB entries -- TID = 0, TS = 0 */
411 /*----------------------------------------------------------------*/
412 addis r0,0,0x0000
413 #ifdef CONFIG_SYS_RAMBOOT
414 li r4,0 /* Start with TLB #0 */
415 #else
416 li r4,1 /* Start with TLB #1 */
417 #endif
418 li r1,64 /* 64 TLB entries */
419 sub r1,r1,r4 /* calculate last TLB # */
420 mtctr r1
421 rsttlb:
422 #ifdef CONFIG_SYS_RAMBOOT
423 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
424 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
425 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
426 #endif
427 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
428 tlbwe r0,r4,1
429 tlbwe r0,r4,2
430 tlbnxt: addi r4,r4,1 /* Next TLB */
431 bdnz rsttlb
432
433 /*----------------------------------------------------------------*/
434 /* TLB entry setup -- step thru tlbtab */
435 /*----------------------------------------------------------------*/
436 #if defined(CONFIG_440SPE_REVA)
437 /*----------------------------------------------------------------*/
438 /* We have different TLB tables for revA and rev B of 440SPe */
439 /*----------------------------------------------------------------*/
440 mfspr r1, PVR
441 lis r0,0x5342
442 ori r0,r0,0x1891
443 cmpw r7,r1,r0
444 bne r7,..revA
445 bl tlbtabB
446 b ..goon
447 ..revA:
448 bl tlbtabA
449 ..goon:
450 #else
451 bl tlbtab /* Get tlbtab pointer */
452 #endif
453 mr r5,r0
454 li r1,0x003f /* 64 TLB entries max */
455 mtctr r1
456 li r4,0 /* TLB # */
457
458 addi r5,r5,-4
459 1:
460 #ifdef CONFIG_SYS_RAMBOOT
461 tlbre r3,r4,0 /* Read contents from TLB word #0 */
462 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
463 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
464 #endif
465 lwzu r0,4(r5)
466 cmpwi r0,0
467 beq 2f /* 0 marks end */
468 lwzu r1,4(r5)
469 lwzu r2,4(r5)
470 tlbwe r0,r4,0 /* TLB Word 0 */
471 tlbwe r1,r4,1 /* TLB Word 1 */
472 tlbwe r2,r4,2 /* TLB Word 2 */
473 tlbnx2: addi r4,r4,1 /* Next TLB */
474 bdnz 1b
475
476 /*----------------------------------------------------------------*/
477 /* Continue from 'normal' start */
478 /*----------------------------------------------------------------*/
479 2:
480 bl 3f
481 b _start
482
483 3: li r0,0
484 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
485 mflr r1
486 mtspr SPRN_SRR0,r1
487 rfi
488 #endif /* CONFIG_440 */
489
490 /*
491 * r3 - 1st arg to board_init(): IMMP pointer
492 * r4 - 2nd arg to board_init(): boot flag
493 */
494 #if !defined(CONFIG_SPL_BUILD)
495 .text
496 .long 0x27051956 /* U-Boot Magic Number */
497 .globl version_string
498 version_string:
499 .ascii U_BOOT_VERSION_STRING, "\0"
500
501 . = EXC_OFF_SYS_RESET
502 .globl _start_of_vectors
503 _start_of_vectors:
504
505 /* Critical input. */
506 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
507
508 #ifdef CONFIG_440
509 /* Machine check */
510 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
511 #else
512 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
513 #endif /* CONFIG_440 */
514
515 /* Data Storage exception. */
516 STD_EXCEPTION(0x300, DataStorage, UnknownException)
517
518 /* Instruction Storage exception. */
519 STD_EXCEPTION(0x400, InstStorage, UnknownException)
520
521 /* External Interrupt exception. */
522 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
523
524 /* Alignment exception. */
525 . = 0x600
526 Alignment:
527 EXCEPTION_PROLOG(SRR0, SRR1)
528 mfspr r4,DAR
529 stw r4,_DAR(r21)
530 mfspr r5,DSISR
531 stw r5,_DSISR(r21)
532 addi r3,r1,STACK_FRAME_OVERHEAD
533 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
534
535 /* Program check exception */
536 . = 0x700
537 ProgramCheck:
538 EXCEPTION_PROLOG(SRR0, SRR1)
539 addi r3,r1,STACK_FRAME_OVERHEAD
540 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
541 MSR_KERNEL, COPY_EE)
542
543 #ifdef CONFIG_440
544 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
545 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
546 STD_EXCEPTION(0xa00, APU, UnknownException)
547 #endif
548 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
549
550 #ifdef CONFIG_440
551 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
552 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
553 #else
554 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
555 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
556 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
557 #endif
558 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
559
560 .globl _end_of_vectors
561 _end_of_vectors:
562 . = _START_OFFSET
563 #endif
564 .globl _start
565 _start:
566
567 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
568 /*
569 * This is the entry of the real U-Boot from a board port
570 * that supports SPL booting on the PPC4xx. We only need
571 * to call board_init_f() here. Everything else has already
572 * been done in the SPL u-boot version.
573 */
574 GET_GOT /* initialize GOT access */
575 bl board_init_f /* run 1st part of board init code (in Flash)*/
576 /* NOTREACHED - board_init_f() does not return */
577 #endif
578
579 /*****************************************************************************/
580 #if defined(CONFIG_440)
581
582 /*----------------------------------------------------------------*/
583 /* Clear and set up some registers. */
584 /*----------------------------------------------------------------*/
585 li r0,0x0000
586 lis r1,0xffff
587 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
588 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
589 mtspr SPRN_TBWU,r0
590 mtspr SPRN_TSR,r1 /* clear all timer exception status */
591 mtspr SPRN_TCR,r0 /* disable all */
592 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
593 mtxer r0 /* clear integer exception register */
594
595 /*----------------------------------------------------------------*/
596 /* Debug setup -- some (not very good) ice's need an event*/
597 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
598 /* value you need in this case 0x8cff 0000 should do the trick */
599 /*----------------------------------------------------------------*/
600 #if defined(CONFIG_SYS_INIT_DBCR)
601 lis r1,0xffff
602 ori r1,r1,0xffff
603 mtspr SPRN_DBSR,r1 /* Clear all status bits */
604 lis r0,CONFIG_SYS_INIT_DBCR@h
605 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
606 mtspr SPRN_DBCR0,r0
607 isync
608 #endif
609
610 /*----------------------------------------------------------------*/
611 /* Setup the internal SRAM */
612 /*----------------------------------------------------------------*/
613 li r0,0
614
615 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
616 /* Clear Dcache to use as RAM */
617 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
618 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
619 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
620 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
621 rlwinm. r5,r4,0,27,31
622 rlwinm r5,r4,27,5,31
623 beq ..d_ran
624 addi r5,r5,0x0001
625 ..d_ran:
626 mtctr r5
627 ..d_ag:
628 dcbz r0,r3
629 addi r3,r3,32
630 bdnz ..d_ag
631
632 /*
633 * Lock the init-ram/stack in d-cache, so that other regions
634 * may use d-cache as well
635 * Note, that this current implementation locks exactly 4k
636 * of d-cache, so please make sure that you don't define a
637 * bigger init-ram area. Take a look at the lwmon5 440EPx
638 * implementation as a reference.
639 */
640 msync
641 isync
642 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
643 lis r1,0x0201
644 ori r1,r1,0xf808
645 mtspr SPRN_DVLIM,r1
646 lis r1,0x0808
647 ori r1,r1,0x0808
648 mtspr SPRN_DNV0,r1
649 mtspr SPRN_DNV1,r1
650 mtspr SPRN_DNV2,r1
651 mtspr SPRN_DNV3,r1
652 mtspr SPRN_DTV0,r1
653 mtspr SPRN_DTV1,r1
654 mtspr SPRN_DTV2,r1
655 mtspr SPRN_DTV3,r1
656 msync
657 isync
658 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
659
660 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
661 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
662 /* not all PPC's have internal SRAM usable as L2-cache */
663 #if defined(CONFIG_440GX) || \
664 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
665 defined(CONFIG_460SX)
666 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
667 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
668 lis r1, 0x0000
669 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
670 mtdcr L2_CACHE_CFG,r1
671 #endif
672
673 lis r2,0x7fff
674 ori r2,r2,0xffff
675 mfdcr r1,ISRAM0_DPC
676 and r1,r1,r2 /* Disable parity check */
677 mtdcr ISRAM0_DPC,r1
678 mfdcr r1,ISRAM0_PMEG
679 and r1,r1,r2 /* Disable pwr mgmt */
680 mtdcr ISRAM0_PMEG,r1
681
682 lis r1,0x8000 /* BAS = 8000_0000 */
683 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
684 ori r1,r1,0x0980 /* first 64k */
685 mtdcr ISRAM0_SB0CR,r1
686 lis r1,0x8001
687 ori r1,r1,0x0980 /* second 64k */
688 mtdcr ISRAM0_SB1CR,r1
689 lis r1, 0x8002
690 ori r1,r1, 0x0980 /* third 64k */
691 mtdcr ISRAM0_SB2CR,r1
692 lis r1, 0x8003
693 ori r1,r1, 0x0980 /* fourth 64k */
694 mtdcr ISRAM0_SB3CR,r1
695 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
696 defined(CONFIG_460GT)
697 lis r1,0x0000 /* BAS = X_0000_0000 */
698 ori r1,r1,0x0984 /* first 64k */
699 mtdcr ISRAM0_SB0CR,r1
700 lis r1,0x0001
701 ori r1,r1,0x0984 /* second 64k */
702 mtdcr ISRAM0_SB1CR,r1
703 lis r1, 0x0002
704 ori r1,r1, 0x0984 /* third 64k */
705 mtdcr ISRAM0_SB2CR,r1
706 lis r1, 0x0003
707 ori r1,r1, 0x0984 /* fourth 64k */
708 mtdcr ISRAM0_SB3CR,r1
709 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
710 lis r2,0x7fff
711 ori r2,r2,0xffff
712 mfdcr r1,ISRAM1_DPC
713 and r1,r1,r2 /* Disable parity check */
714 mtdcr ISRAM1_DPC,r1
715 mfdcr r1,ISRAM1_PMEG
716 and r1,r1,r2 /* Disable pwr mgmt */
717 mtdcr ISRAM1_PMEG,r1
718
719 lis r1,0x0004 /* BAS = 4_0004_0000 */
720 ori r1,r1,ISRAM1_SIZE /* ocm size */
721 mtdcr ISRAM1_SB0CR,r1
722 #endif
723 #elif defined(CONFIG_460SX)
724 lis r1,0x0000 /* BAS = 0000_0000 */
725 ori r1,r1,0x0B84 /* first 128k */
726 mtdcr ISRAM0_SB0CR,r1
727 lis r1,0x0001
728 ori r1,r1,0x0B84 /* second 128k */
729 mtdcr ISRAM0_SB1CR,r1
730 lis r1, 0x0002
731 ori r1,r1, 0x0B84 /* third 128k */
732 mtdcr ISRAM0_SB2CR,r1
733 lis r1, 0x0003
734 ori r1,r1, 0x0B84 /* fourth 128k */
735 mtdcr ISRAM0_SB3CR,r1
736 #elif defined(CONFIG_440GP)
737 ori r1,r1,0x0380 /* 8k rw */
738 mtdcr ISRAM0_SB0CR,r1
739 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
740 #endif
741 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
742
743 /*----------------------------------------------------------------*/
744 /* Setup the stack in internal SRAM */
745 /*----------------------------------------------------------------*/
746 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
747 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
748 li r0,0
749 stwu r0,-4(r1)
750 stwu r0,-4(r1) /* Terminate call chain */
751
752 stwu r1,-8(r1) /* Save back chain and move SP */
753 lis r0,RESET_VECTOR@h /* Address of reset vector */
754 ori r0,r0, RESET_VECTOR@l
755 stwu r1,-8(r1) /* Save back chain and move SP */
756 stw r0,+12(r1) /* Save return addr (underflow vect) */
757
758 #ifndef CONFIG_SPL_BUILD
759 GET_GOT
760 #endif
761
762 bl cpu_init_f /* run low-level CPU init code (from Flash) */
763 mr r3, r1
764 bl board_init_f_alloc_reserve
765 mr r1, r3
766 bl board_init_f_init_reserve
767 li r0,0
768 stwu r0, -4(r1)
769 stwu r0, -4(r1)
770 li r3, 0
771 bl board_init_f
772 /* NOTREACHED - board_init_f() does not return */
773
774 #endif /* CONFIG_440 */
775
776 /*****************************************************************************/
777 #if defined(CONFIG_405GP) || \
778 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
779 defined(CONFIG_405EX) || defined(CONFIG_405)
780 /*----------------------------------------------------------------------- */
781 /* Clear and set up some registers. */
782 /*----------------------------------------------------------------------- */
783 addi r4,r0,0x0000
784 #if !defined(CONFIG_405EX)
785 mtspr SPRN_SGR,r4
786 #else
787 /*
788 * On 405EX, completely clearing the SGR leads to PPC hangup
789 * upon PCIe configuration access. The PCIe memory regions
790 * need to be guarded!
791 */
792 lis r3,0x0000
793 ori r3,r3,0x7FFC
794 mtspr SPRN_SGR,r3
795 #endif
796 mtspr SPRN_DCWR,r4
797 mtesr r4 /* clear Exception Syndrome Reg */
798 mttcr r4 /* clear Timer Control Reg */
799 mtxer r4 /* clear Fixed-Point Exception Reg */
800 mtevpr r4 /* clear Exception Vector Prefix Reg */
801 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
802 /* dbsr is cleared by setting bits to 1) */
803 mtdbsr r4 /* clear/reset the dbsr */
804
805 /* Invalidate the i- and d-caches. */
806 bl invalidate_icache
807 bl invalidate_dcache
808
809 /* Set-up icache cacheability. */
810 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
811 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
812 mticcr r4
813 isync
814
815 /* Set-up dcache cacheability. */
816 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
817 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
818 mtdccr r4
819
820 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
821 && !defined (CONFIG_XILINX_405)
822 /*----------------------------------------------------------------------- */
823 /* Tune the speed and size for flash CS0 */
824 /*----------------------------------------------------------------------- */
825 bl ext_bus_cntlr_init
826 #endif
827
828 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
829 /*
830 * For boards that don't have OCM and can't use the data cache
831 * for their primordial stack, setup stack here directly after the
832 * SDRAM is initialized in ext_bus_cntlr_init.
833 */
834 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
835 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
836
837 li r0, 0 /* Make room for stack frame header and */
838 stwu r0, -4(r1) /* clear final stack frame so that */
839 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
840 /*
841 * Set up a dummy frame to store reset vector as return address.
842 * this causes stack underflow to reset board.
843 */
844 stwu r1, -8(r1) /* Save back chain and move SP */
845 lis r0, RESET_VECTOR@h /* Address of reset vector */
846 ori r0, r0, RESET_VECTOR@l
847 stwu r1, -8(r1) /* Save back chain and move SP */
848 stw r0, +12(r1) /* Save return addr (underflow vect) */
849 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
850
851 #if defined(CONFIG_405EP)
852 /*----------------------------------------------------------------------- */
853 /* DMA Status, clear to come up clean */
854 /*----------------------------------------------------------------------- */
855 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
856 ori r3,r3, 0xFFFF
857 mtdcr DMASR, r3
858
859 bl ppc405ep_init /* do ppc405ep specific init */
860 #endif /* CONFIG_405EP */
861
862 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
863 #if defined(CONFIG_405EZ)
864 /********************************************************************
865 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
866 *******************************************************************/
867 /*
868 * We can map the OCM on the PLB3, so map it at
869 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
870 */
871 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
872 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
873 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
874 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
875 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
876 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
877 isync
878
879 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
880 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
881 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
882 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
883 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
884 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
885 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
886 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
887 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
888 mtdcr OCM0_DISDPC,r3
889
890 isync
891 #else /* CONFIG_405EZ */
892 /********************************************************************
893 * Setup OCM - On Chip Memory
894 *******************************************************************/
895 /* Setup OCM */
896 lis r0, 0x7FFF
897 ori r0, r0, 0xFFFF
898 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
899 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
900 and r3, r3, r0 /* disable data-side IRAM */
901 and r4, r4, r0 /* disable data-side IRAM */
902 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
903 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
904 isync
905
906 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
907 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
908 mtdcr OCM0_DSARC, r3
909 addis r4, 0, 0xC000 /* OCM data area enabled */
910 mtdcr OCM0_DSCNTL, r4
911 isync
912 #endif /* CONFIG_405EZ */
913 #endif
914
915 /*----------------------------------------------------------------------- */
916 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
917 /*----------------------------------------------------------------------- */
918 #ifdef CONFIG_SYS_INIT_DCACHE_CS
919 li r4, PBxAP
920 mtdcr EBC0_CFGADDR, r4
921 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
922 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
923 mtdcr EBC0_CFGDATA, r4
924
925 addi r4, 0, PBxCR
926 mtdcr EBC0_CFGADDR, r4
927 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
928 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
929 mtdcr EBC0_CFGDATA, r4
930
931 /*
932 * Enable the data cache for the 128MB storage access control region
933 * at CONFIG_SYS_INIT_RAM_ADDR.
934 */
935 mfdccr r4
936 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
937 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
938 mtdccr r4
939
940 /*
941 * Preallocate data cache lines to be used to avoid a subsequent
942 * cache miss and an ensuing machine check exception when exceptions
943 * are enabled.
944 */
945 li r0, 0
946
947 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
948 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
949
950 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
951 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
952
953 /*
954 * Convert the size, in bytes, to the number of cache lines/blocks
955 * to preallocate.
956 */
957 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
958 srwi r5, r4, L1_CACHE_SHIFT
959 beq ..load_counter
960 addi r5, r5, 0x0001
961 ..load_counter:
962 mtctr r5
963
964 /* Preallocate the computed number of cache blocks. */
965 ..alloc_dcache_block:
966 dcba r0, r3
967 addi r3, r3, L1_CACHE_BYTES
968 bdnz ..alloc_dcache_block
969 sync
970
971 /*
972 * Load the initial stack pointer and data area and convert the size,
973 * in bytes, to the number of words to initialize to a known value.
974 */
975 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
976 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
977
978 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
979 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
980 mtctr r4
981
982 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
983 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
984
985 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
986 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
987
988 ..stackloop:
989 stwu r4, -4(r2)
990 bdnz ..stackloop
991
992 /*
993 * Make room for stack frame header and clear final stack frame so
994 * that stack backtraces terminate cleanly.
995 */
996 stwu r0, -4(r1)
997 stwu r0, -4(r1)
998
999 /*
1000 * Set up a dummy frame to store reset vector as return address.
1001 * this causes stack underflow to reset board.
1002 */
1003 stwu r1, -8(r1) /* Save back chain and move SP */
1004 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1005 ori r0, r0, RESET_VECTOR@l
1006 stwu r1, -8(r1) /* Save back chain and move SP */
1007 stw r0, +12(r1) /* Save return addr (underflow vect) */
1008
1009 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1010 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1011 /*
1012 * Stack in OCM.
1013 */
1014
1015 /* Set up Stack at top of OCM */
1016 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1017 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1018
1019 /* Set up a zeroized stack frame so that backtrace works right */
1020 li r0, 0
1021 stwu r0, -4(r1)
1022 stwu r0, -4(r1)
1023
1024 /*
1025 * Set up a dummy frame to store reset vector as return address.
1026 * this causes stack underflow to reset board.
1027 */
1028 stwu r1, -8(r1) /* Save back chain and move SP */
1029 lis r0, RESET_VECTOR@h /* Address of reset vector */
1030 ori r0, r0, RESET_VECTOR@l
1031 stwu r1, -8(r1) /* Save back chain and move SP */
1032 stw r0, +12(r1) /* Save return addr (underflow vect) */
1033 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1034
1035 GET_GOT /* initialize GOT access */
1036
1037 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1038 mr r3, r1
1039 bl board_init_f_alloc_reserve
1040 mr r1, r3
1041 bl board_init_f_init_reserve
1042 stwu r0, -4(r1)
1043 stwu r0, -4(r1)
1044 li r3, 0
1045 bl board_init_f /* run first part of init code (from Flash) */
1046 /* NOTREACHED - board_init_f() does not return */
1047
1048 #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
1049 /*----------------------------------------------------------------------- */
1050
1051
1052 #if !defined(CONFIG_SPL_BUILD)
1053 /*
1054 * This code finishes saving the registers to the exception frame
1055 * and jumps to the appropriate handler for the exception.
1056 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1057 */
1058 .globl transfer_to_handler
1059 transfer_to_handler:
1060 stw r22,_NIP(r21)
1061 lis r22,MSR_POW@h
1062 andc r23,r23,r22
1063 stw r23,_MSR(r21)
1064 SAVE_GPR(7, r21)
1065 SAVE_4GPRS(8, r21)
1066 SAVE_8GPRS(12, r21)
1067 SAVE_8GPRS(24, r21)
1068 mflr r23
1069 andi. r24,r23,0x3f00 /* get vector offset */
1070 stw r24,TRAP(r21)
1071 li r22,0
1072 stw r22,RESULT(r21)
1073 mtspr SPRG2,r22 /* r1 is now kernel sp */
1074 lwz r24,0(r23) /* virtual address of handler */
1075 lwz r23,4(r23) /* where to go when done */
1076 mtspr SRR0,r24
1077 mtspr SRR1,r20
1078 mtlr r23
1079 SYNC
1080 rfi /* jump to handler, enable MMU */
1081
1082 int_return:
1083 mfmsr r28 /* Disable interrupts */
1084 li r4,0
1085 ori r4,r4,MSR_EE
1086 andc r28,r28,r4
1087 SYNC /* Some chip revs need this... */
1088 mtmsr r28
1089 SYNC
1090 lwz r2,_CTR(r1)
1091 lwz r0,_LINK(r1)
1092 mtctr r2
1093 mtlr r0
1094 lwz r2,_XER(r1)
1095 lwz r0,_CCR(r1)
1096 mtspr XER,r2
1097 mtcrf 0xFF,r0
1098 REST_10GPRS(3, r1)
1099 REST_10GPRS(13, r1)
1100 REST_8GPRS(23, r1)
1101 REST_GPR(31, r1)
1102 lwz r2,_NIP(r1) /* Restore environment */
1103 lwz r0,_MSR(r1)
1104 mtspr SRR0,r2
1105 mtspr SRR1,r0
1106 lwz r0,GPR0(r1)
1107 lwz r2,GPR2(r1)
1108 lwz r1,GPR1(r1)
1109 SYNC
1110 rfi
1111
1112 crit_return:
1113 mfmsr r28 /* Disable interrupts */
1114 li r4,0
1115 ori r4,r4,MSR_EE
1116 andc r28,r28,r4
1117 SYNC /* Some chip revs need this... */
1118 mtmsr r28
1119 SYNC
1120 lwz r2,_CTR(r1)
1121 lwz r0,_LINK(r1)
1122 mtctr r2
1123 mtlr r0
1124 lwz r2,_XER(r1)
1125 lwz r0,_CCR(r1)
1126 mtspr XER,r2
1127 mtcrf 0xFF,r0
1128 REST_10GPRS(3, r1)
1129 REST_10GPRS(13, r1)
1130 REST_8GPRS(23, r1)
1131 REST_GPR(31, r1)
1132 lwz r2,_NIP(r1) /* Restore environment */
1133 lwz r0,_MSR(r1)
1134 mtspr SPRN_CSRR0,r2
1135 mtspr SPRN_CSRR1,r0
1136 lwz r0,GPR0(r1)
1137 lwz r2,GPR2(r1)
1138 lwz r1,GPR1(r1)
1139 SYNC
1140 rfci
1141
1142 #ifdef CONFIG_440
1143 mck_return:
1144 mfmsr r28 /* Disable interrupts */
1145 li r4,0
1146 ori r4,r4,MSR_EE
1147 andc r28,r28,r4
1148 SYNC /* Some chip revs need this... */
1149 mtmsr r28
1150 SYNC
1151 lwz r2,_CTR(r1)
1152 lwz r0,_LINK(r1)
1153 mtctr r2
1154 mtlr r0
1155 lwz r2,_XER(r1)
1156 lwz r0,_CCR(r1)
1157 mtspr XER,r2
1158 mtcrf 0xFF,r0
1159 REST_10GPRS(3, r1)
1160 REST_10GPRS(13, r1)
1161 REST_8GPRS(23, r1)
1162 REST_GPR(31, r1)
1163 lwz r2,_NIP(r1) /* Restore environment */
1164 lwz r0,_MSR(r1)
1165 mtspr SPRN_MCSRR0,r2
1166 mtspr SPRN_MCSRR1,r0
1167 lwz r0,GPR0(r1)
1168 lwz r2,GPR2(r1)
1169 lwz r1,GPR1(r1)
1170 SYNC
1171 rfmci
1172 #endif /* CONFIG_440 */
1173
1174
1175 .globl get_pvr
1176 get_pvr:
1177 mfspr r3, PVR
1178 blr
1179
1180 /*------------------------------------------------------------------------------- */
1181 /* Function: out16 */
1182 /* Description: Output 16 bits */
1183 /*------------------------------------------------------------------------------- */
1184 .globl out16
1185 out16:
1186 sth r4,0x0000(r3)
1187 blr
1188
1189 /*------------------------------------------------------------------------------- */
1190 /* Function: out16r */
1191 /* Description: Byte reverse and output 16 bits */
1192 /*------------------------------------------------------------------------------- */
1193 .globl out16r
1194 out16r:
1195 sthbrx r4,r0,r3
1196 blr
1197
1198 /*------------------------------------------------------------------------------- */
1199 /* Function: out32r */
1200 /* Description: Byte reverse and output 32 bits */
1201 /*------------------------------------------------------------------------------- */
1202 .globl out32r
1203 out32r:
1204 stwbrx r4,r0,r3
1205 blr
1206
1207 /*------------------------------------------------------------------------------- */
1208 /* Function: in16 */
1209 /* Description: Input 16 bits */
1210 /*------------------------------------------------------------------------------- */
1211 .globl in16
1212 in16:
1213 lhz r3,0x0000(r3)
1214 blr
1215
1216 /*------------------------------------------------------------------------------- */
1217 /* Function: in16r */
1218 /* Description: Input 16 bits and byte reverse */
1219 /*------------------------------------------------------------------------------- */
1220 .globl in16r
1221 in16r:
1222 lhbrx r3,r0,r3
1223 blr
1224
1225 /*------------------------------------------------------------------------------- */
1226 /* Function: in32r */
1227 /* Description: Input 32 bits and byte reverse */
1228 /*------------------------------------------------------------------------------- */
1229 .globl in32r
1230 in32r:
1231 lwbrx r3,r0,r3
1232 blr
1233
1234 #if !defined(CONFIG_SPL_BUILD)
1235 /*
1236 * void relocate_code (addr_sp, gd, addr_moni)
1237 *
1238 * This "function" does not return, instead it continues in RAM
1239 * after relocating the monitor code.
1240 *
1241 * r3 = Relocated stack pointer
1242 * r4 = Relocated global data pointer
1243 * r5 = Relocated text pointer
1244 */
1245 .globl relocate_code
1246 relocate_code:
1247 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1248 /*
1249 * We need to flush the initial global data (gd_t) and bd_info
1250 * before the dcache will be invalidated.
1251 */
1252
1253 /* Save registers */
1254 mr r9, r3
1255 mr r10, r4
1256 mr r11, r5
1257
1258 /*
1259 * Flush complete dcache, this is faster than flushing the
1260 * ranges for global_data and bd_info instead.
1261 */
1262 bl flush_dcache
1263
1264 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1265 /*
1266 * Undo the earlier data cache set-up for the primordial stack and
1267 * data area. First, invalidate the data cache and then disable data
1268 * cacheability for that area. Finally, restore the EBC values, if
1269 * any.
1270 */
1271
1272 /* Invalidate the primordial stack and data area in cache */
1273 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1274 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1275
1276 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1277 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1278 add r4, r4, r3
1279
1280 bl invalidate_dcache_range
1281
1282 /* Disable cacheability for the region */
1283 mfdccr r3
1284 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1285 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1286 and r3, r3, r4
1287 mtdccr r3
1288
1289 /* Restore the EBC parameters */
1290 li r3, PBxAP
1291 mtdcr EBC0_CFGADDR, r3
1292 lis r3, PBxAP_VAL@h
1293 ori r3, r3, PBxAP_VAL@l
1294 mtdcr EBC0_CFGDATA, r3
1295
1296 li r3, PBxCR
1297 mtdcr EBC0_CFGADDR, r3
1298 lis r3, PBxCR_VAL@h
1299 ori r3, r3, PBxCR_VAL@l
1300 mtdcr EBC0_CFGDATA, r3
1301 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1302
1303 /* Restore registers */
1304 mr r3, r9
1305 mr r4, r10
1306 mr r5, r11
1307 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1308
1309 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1310 /*
1311 * Unlock the previously locked d-cache
1312 */
1313 msync
1314 isync
1315 /* set TFLOOR/NFLOOR to 0 again */
1316 lis r6,0x0001
1317 ori r6,r6,0xf800
1318 mtspr SPRN_DVLIM,r6
1319 lis r6,0x0000
1320 ori r6,r6,0x0000
1321 mtspr SPRN_DNV0,r6
1322 mtspr SPRN_DNV1,r6
1323 mtspr SPRN_DNV2,r6
1324 mtspr SPRN_DNV3,r6
1325 mtspr SPRN_DTV0,r6
1326 mtspr SPRN_DTV1,r6
1327 mtspr SPRN_DTV2,r6
1328 mtspr SPRN_DTV3,r6
1329 msync
1330 isync
1331
1332 /* Invalidate data cache, now no longer our stack */
1333 dccci 0,0
1334 sync
1335 isync
1336 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1337
1338 /*
1339 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1340 * to speed up the boot process. Now this cache needs to be disabled.
1341 */
1342 #if defined(CONFIG_440)
1343 /* Clear all potential pending exceptions */
1344 mfspr r1,SPRN_MCSR
1345 mtspr SPRN_MCSR,r1
1346 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1347 tlbre r0,r1,0x0002 /* Read contents */
1348 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1349 tlbwe r0,r1,0x0002 /* Save it out */
1350 sync
1351 isync
1352 #endif /* defined(CONFIG_440) */
1353 mr r1, r3 /* Set new stack pointer */
1354 mr r9, r4 /* Save copy of Init Data pointer */
1355 mr r10, r5 /* Save copy of Destination Address */
1356
1357 GET_GOT
1358 mr r3, r5 /* Destination Address */
1359 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1360 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1361 lwz r5, GOT(__init_end)
1362 sub r5, r5, r4
1363 li r6, L1_CACHE_BYTES /* Cache Line Size */
1364
1365 /*
1366 * Fix GOT pointer:
1367 *
1368 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1369 *
1370 * Offset:
1371 */
1372 sub r15, r10, r4
1373
1374 /* First our own GOT */
1375 add r12, r12, r15
1376 /* then the one used by the C code */
1377 add r30, r30, r15
1378
1379 /*
1380 * Now relocate code
1381 */
1382
1383 cmplw cr1,r3,r4
1384 addi r0,r5,3
1385 srwi. r0,r0,2
1386 beq cr1,4f /* In place copy is not necessary */
1387 beq 7f /* Protect against 0 count */
1388 mtctr r0
1389 bge cr1,2f
1390
1391 la r8,-4(r4)
1392 la r7,-4(r3)
1393 1: lwzu r0,4(r8)
1394 stwu r0,4(r7)
1395 bdnz 1b
1396 b 4f
1397
1398 2: slwi r0,r0,2
1399 add r8,r4,r0
1400 add r7,r3,r0
1401 3: lwzu r0,-4(r8)
1402 stwu r0,-4(r7)
1403 bdnz 3b
1404
1405 /*
1406 * Now flush the cache: note that we must start from a cache aligned
1407 * address. Otherwise we might miss one cache line.
1408 */
1409 4: cmpwi r6,0
1410 add r5,r3,r5
1411 beq 7f /* Always flush prefetch queue in any case */
1412 subi r0,r6,1
1413 andc r3,r3,r0
1414 mr r4,r3
1415 5: dcbst 0,r4
1416 add r4,r4,r6
1417 cmplw r4,r5
1418 blt 5b
1419 sync /* Wait for all dcbst to complete on bus */
1420 mr r4,r3
1421 6: icbi 0,r4
1422 add r4,r4,r6
1423 cmplw r4,r5
1424 blt 6b
1425 7: sync /* Wait for all icbi to complete on bus */
1426 isync
1427
1428 /*
1429 * We are done. Do not return, instead branch to second part of board
1430 * initialization, now running from RAM.
1431 */
1432
1433 addi r0, r10, in_ram - _start + _START_OFFSET
1434 mtlr r0
1435 blr /* NEVER RETURNS! */
1436
1437 in_ram:
1438
1439 /*
1440 * Relocation Function, r12 point to got2+0x8000
1441 *
1442 * Adjust got2 pointers, no need to check for 0, this code
1443 * already puts a few entries in the table.
1444 */
1445 li r0,__got2_entries@sectoff@l
1446 la r3,GOT(_GOT2_TABLE_)
1447 lwz r11,GOT(_GOT2_TABLE_)
1448 mtctr r0
1449 sub r11,r3,r11
1450 addi r3,r3,-4
1451 1: lwzu r0,4(r3)
1452 cmpwi r0,0
1453 beq- 2f
1454 add r0,r0,r11
1455 stw r0,0(r3)
1456 2: bdnz 1b
1457
1458 /*
1459 * Now adjust the fixups and the pointers to the fixups
1460 * in case we need to move ourselves again.
1461 */
1462 li r0,__fixup_entries@sectoff@l
1463 lwz r3,GOT(_FIXUP_TABLE_)
1464 cmpwi r0,0
1465 mtctr r0
1466 addi r3,r3,-4
1467 beq 4f
1468 3: lwzu r4,4(r3)
1469 lwzux r0,r4,r11
1470 cmpwi r0,0
1471 add r0,r0,r11
1472 stw r4,0(r3)
1473 beq- 5f
1474 stw r0,0(r4)
1475 5: bdnz 3b
1476 4:
1477 clear_bss:
1478 /*
1479 * Now clear BSS segment
1480 */
1481 lwz r3,GOT(__bss_start)
1482 lwz r4,GOT(__bss_end)
1483
1484 cmplw 0, r3, r4
1485 beq 7f
1486
1487 li r0, 0
1488
1489 andi. r5, r4, 3
1490 beq 6f
1491 sub r4, r4, r5
1492 mtctr r5
1493 mr r5, r4
1494 5: stb r0, 0(r5)
1495 addi r5, r5, 1
1496 bdnz 5b
1497 6:
1498 stw r0, 0(r3)
1499 addi r3, r3, 4
1500 cmplw 0, r3, r4
1501 bne 6b
1502
1503 7:
1504 mr r3, r9 /* Init Data pointer */
1505 mr r4, r10 /* Destination Address */
1506 bl board_init_r
1507
1508 /*
1509 * Copy exception vector code to low memory
1510 *
1511 * r3: dest_addr
1512 * r7: source address, r8: end address, r9: target address
1513 */
1514 .globl trap_init
1515 trap_init:
1516 mflr r4 /* save link register */
1517 GET_GOT
1518 lwz r7, GOT(_start_of_vectors)
1519 lwz r8, GOT(_end_of_vectors)
1520
1521 li r9, 0x100 /* reset vector always at 0x100 */
1522
1523 cmplw 0, r7, r8
1524 bgelr /* return if r7>=r8 - just in case */
1525 1:
1526 lwz r0, 0(r7)
1527 stw r0, 0(r9)
1528 addi r7, r7, 4
1529 addi r9, r9, 4
1530 cmplw 0, r7, r8
1531 bne 1b
1532
1533 /*
1534 * relocate `hdlr' and `int_return' entries
1535 */
1536 li r7, .L_MachineCheck - _start + _START_OFFSET
1537 li r8, Alignment - _start + _START_OFFSET
1538 2:
1539 bl trap_reloc
1540 addi r7, r7, 0x100 /* next exception vector */
1541 cmplw 0, r7, r8
1542 blt 2b
1543
1544 li r7, .L_Alignment - _start + _START_OFFSET
1545 bl trap_reloc
1546
1547 li r7, .L_ProgramCheck - _start + _START_OFFSET
1548 bl trap_reloc
1549
1550 #ifdef CONFIG_440
1551 li r7, .L_FPUnavailable - _start + _START_OFFSET
1552 bl trap_reloc
1553
1554 li r7, .L_Decrementer - _start + _START_OFFSET
1555 bl trap_reloc
1556
1557 li r7, .L_APU - _start + _START_OFFSET
1558 bl trap_reloc
1559
1560 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1561 bl trap_reloc
1562
1563 li r7, .L_DataTLBError - _start + _START_OFFSET
1564 bl trap_reloc
1565 #else /* CONFIG_440 */
1566 li r7, .L_PIT - _start + _START_OFFSET
1567 bl trap_reloc
1568
1569 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1570 bl trap_reloc
1571
1572 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1573 bl trap_reloc
1574 #endif /* CONFIG_440 */
1575
1576 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1577 bl trap_reloc
1578
1579 #if !defined(CONFIG_440)
1580 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1581 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1582 mtmsr r7 /* change MSR */
1583 #else
1584 bl __440_msr_set
1585 b __440_msr_continue
1586
1587 __440_msr_set:
1588 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1589 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1590 mtspr SPRN_SRR1,r7
1591 mflr r7
1592 mtspr SPRN_SRR0,r7
1593 rfi
1594 __440_msr_continue:
1595 #endif
1596
1597 mtlr r4 /* restore link register */
1598 blr
1599 #endif /* CONFIG_SPL_BUILD */
1600
1601 #if defined(CONFIG_440)
1602 /*----------------------------------------------------------------------------+
1603 | dcbz_area.
1604 +----------------------------------------------------------------------------*/
1605 function_prolog(dcbz_area)
1606 rlwinm. r5,r4,0,27,31
1607 rlwinm r5,r4,27,5,31
1608 beq ..d_ra2
1609 addi r5,r5,0x0001
1610 ..d_ra2:mtctr r5
1611 ..d_ag2:dcbz r0,r3
1612 addi r3,r3,32
1613 bdnz ..d_ag2
1614 sync
1615 blr
1616 function_epilog(dcbz_area)
1617 #endif /* CONFIG_440 */
1618 #endif /* CONFIG_SPL_BUILD */
1619
1620 /*------------------------------------------------------------------------------- */
1621 /* Function: in8 */
1622 /* Description: Input 8 bits */
1623 /*------------------------------------------------------------------------------- */
1624 .globl in8
1625 in8:
1626 lbz r3,0x0000(r3)
1627 blr
1628
1629 /*------------------------------------------------------------------------------- */
1630 /* Function: out8 */
1631 /* Description: Output 8 bits */
1632 /*------------------------------------------------------------------------------- */
1633 .globl out8
1634 out8:
1635 stb r4,0x0000(r3)
1636 blr
1637
1638 /*------------------------------------------------------------------------------- */
1639 /* Function: out32 */
1640 /* Description: Output 32 bits */
1641 /*------------------------------------------------------------------------------- */
1642 .globl out32
1643 out32:
1644 stw r4,0x0000(r3)
1645 blr
1646
1647 /*------------------------------------------------------------------------------- */
1648 /* Function: in32 */
1649 /* Description: Input 32 bits */
1650 /*------------------------------------------------------------------------------- */
1651 .globl in32
1652 in32:
1653 lwz 3,0x0000(3)
1654 blr
1655
1656 /**************************************************************************/
1657 /* PPC405EP specific stuff */
1658 /**************************************************************************/
1659 #ifdef CONFIG_405EP
1660 ppc405ep_init:
1661
1662 #ifdef CONFIG_BUBINGA
1663 /*
1664 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1665 * function) to support FPGA and NVRAM accesses below.
1666 */
1667
1668 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1669 ori r3,r3,GPIO0_OSRH@l
1670 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1671 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1672 stw r4,0(r3)
1673 lis r3,GPIO0_OSRL@h
1674 ori r3,r3,GPIO0_OSRL@l
1675 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1676 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1677 stw r4,0(r3)
1678
1679 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1680 ori r3,r3,GPIO0_ISR1H@l
1681 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1682 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1683 stw r4,0(r3)
1684 lis r3,GPIO0_ISR1L@h
1685 ori r3,r3,GPIO0_ISR1L@l
1686 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1687 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1688 stw r4,0(r3)
1689
1690 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1691 ori r3,r3,GPIO0_TSRH@l
1692 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1693 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1694 stw r4,0(r3)
1695 lis r3,GPIO0_TSRL@h
1696 ori r3,r3,GPIO0_TSRL@l
1697 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1698 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1699 stw r4,0(r3)
1700
1701 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1702 ori r3,r3,GPIO0_TCR@l
1703 lis r4,CONFIG_SYS_GPIO0_TCR@h
1704 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1705 stw r4,0(r3)
1706
1707 li r3,PB1AP /* program EBC bank 1 for RTC access */
1708 mtdcr EBC0_CFGADDR,r3
1709 lis r3,CONFIG_SYS_EBC_PB1AP@h
1710 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1711 mtdcr EBC0_CFGDATA,r3
1712 li r3,PB1CR
1713 mtdcr EBC0_CFGADDR,r3
1714 lis r3,CONFIG_SYS_EBC_PB1CR@h
1715 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1716 mtdcr EBC0_CFGDATA,r3
1717
1718 li r3,PB1AP /* program EBC bank 1 for RTC access */
1719 mtdcr EBC0_CFGADDR,r3
1720 lis r3,CONFIG_SYS_EBC_PB1AP@h
1721 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1722 mtdcr EBC0_CFGDATA,r3
1723 li r3,PB1CR
1724 mtdcr EBC0_CFGADDR,r3
1725 lis r3,CONFIG_SYS_EBC_PB1CR@h
1726 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1727 mtdcr EBC0_CFGDATA,r3
1728
1729 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1730 mtdcr EBC0_CFGADDR,r3
1731 lis r3,CONFIG_SYS_EBC_PB4AP@h
1732 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1733 mtdcr EBC0_CFGDATA,r3
1734 li r3,PB4CR
1735 mtdcr EBC0_CFGADDR,r3
1736 lis r3,CONFIG_SYS_EBC_PB4CR@h
1737 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1738 mtdcr EBC0_CFGDATA,r3
1739 #endif
1740
1741 /*
1742 !-----------------------------------------------------------------------
1743 ! Check to see if chip is in bypass mode.
1744 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1745 ! CPU reset Otherwise, skip this step and keep going.
1746 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1747 ! will not be fast enough for the SDRAM (min 66MHz)
1748 !-----------------------------------------------------------------------
1749 */
1750 mfdcr r5, CPC0_PLLMR1
1751 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1752 cmpi cr0,0,r4,0x1
1753
1754 beq pll_done /* if SSCS =b'1' then PLL has */
1755 /* already been set */
1756 /* and CPU has been reset */
1757 /* so skip to next section */
1758
1759 #ifdef CONFIG_BUBINGA
1760 /*
1761 !-----------------------------------------------------------------------
1762 ! Read NVRAM to get value to write in PLLMR.
1763 ! If value has not been correctly saved, write default value
1764 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1765 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1766 !
1767 ! WARNING: This code assumes the first three words in the nvram_t
1768 ! structure in openbios.h. Changing the beginning of
1769 ! the structure will break this code.
1770 !
1771 !-----------------------------------------------------------------------
1772 */
1773 addis r3,0,NVRAM_BASE@h
1774 addi r3,r3,NVRAM_BASE@l
1775
1776 lwz r4, 0(r3)
1777 addis r5,0,NVRVFY1@h
1778 addi r5,r5,NVRVFY1@l
1779 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1780 bne ..no_pllset
1781 addi r3,r3,4
1782 lwz r4, 0(r3)
1783 addis r5,0,NVRVFY2@h
1784 addi r5,r5,NVRVFY2@l
1785 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1786 bne ..no_pllset
1787 addi r3,r3,8 /* Skip over conf_size */
1788 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1789 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1790 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1791 cmpi cr0,0,r5,1 /* See if PLL is locked */
1792 beq pll_write
1793 ..no_pllset:
1794 #endif /* CONFIG_BUBINGA */
1795
1796 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1797 ori r3,r3,PLLMR0_DEFAULT@l /* */
1798 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1799 ori r4,r4,PLLMR1_DEFAULT@l /* */
1800
1801 1:
1802 b pll_write /* Write the CPC0_PLLMR with new value */
1803
1804 pll_done:
1805 /*
1806 !-----------------------------------------------------------------------
1807 ! Clear Soft Reset Register
1808 ! This is needed to enable PCI if not booting from serial EPROM
1809 !-----------------------------------------------------------------------
1810 */
1811 addi r3, 0, 0x0
1812 mtdcr CPC0_SRR, r3
1813
1814 addis r3,0,0x0010
1815 mtctr r3
1816 pci_wait:
1817 bdnz pci_wait
1818
1819 blr /* return to main code */
1820
1821 /*
1822 !-----------------------------------------------------------------------------
1823 ! Function: pll_write
1824 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1825 ! That is:
1826 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1827 ! 2. PLL is reset
1828 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1829 ! 4. PLL Reset is cleared
1830 ! 5. Wait 100us for PLL to lock
1831 ! 6. A core reset is performed
1832 ! Input: r3 = Value to write to CPC0_PLLMR0
1833 ! Input: r4 = Value to write to CPC0_PLLMR1
1834 ! Output r3 = none
1835 !-----------------------------------------------------------------------------
1836 */
1837 .globl pll_write
1838 pll_write:
1839 mfdcr r5, CPC0_UCR
1840 andis. r5,r5,0xFFFF
1841 ori r5,r5,0x0101 /* Stop the UART clocks */
1842 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1843
1844 mfdcr r5, CPC0_PLLMR1
1845 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1846 mtdcr CPC0_PLLMR1,r5
1847 oris r5,r5,0x4000 /* Set PLL Reset */
1848 mtdcr CPC0_PLLMR1,r5
1849
1850 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1851 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1852 oris r5,r5,0x4000 /* Set PLL Reset */
1853 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1854 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1855 mtdcr CPC0_PLLMR1,r5
1856
1857 /*
1858 ! Wait min of 100us for PLL to lock.
1859 ! See CMOS 27E databook for more info.
1860 ! At 200MHz, that means waiting 20,000 instructions
1861 */
1862 addi r3,0,20000 /* 2000 = 0x4e20 */
1863 mtctr r3
1864 pll_wait:
1865 bdnz pll_wait
1866
1867 oris r5,r5,0x8000 /* Enable PLL */
1868 mtdcr CPC0_PLLMR1,r5 /* Engage */
1869
1870 /*
1871 * Reset CPU to guarantee timings are OK
1872 * Not sure if this is needed...
1873 */
1874 addis r3,0,0x1000
1875 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
1876 /* execution will continue from the poweron */
1877 /* vector of 0xfffffffc */
1878 #endif /* CONFIG_405EP */
1879
1880 #if defined(CONFIG_440)
1881 /*----------------------------------------------------------------------------+
1882 | mttlb3.
1883 +----------------------------------------------------------------------------*/
1884 function_prolog(mttlb3)
1885 TLBWE(4,3,2)
1886 blr
1887 function_epilog(mttlb3)
1888
1889 /*----------------------------------------------------------------------------+
1890 | mftlb3.
1891 +----------------------------------------------------------------------------*/
1892 function_prolog(mftlb3)
1893 TLBRE(3,3,2)
1894 blr
1895 function_epilog(mftlb3)
1896
1897 /*----------------------------------------------------------------------------+
1898 | mttlb2.
1899 +----------------------------------------------------------------------------*/
1900 function_prolog(mttlb2)
1901 TLBWE(4,3,1)
1902 blr
1903 function_epilog(mttlb2)
1904
1905 /*----------------------------------------------------------------------------+
1906 | mftlb2.
1907 +----------------------------------------------------------------------------*/
1908 function_prolog(mftlb2)
1909 TLBRE(3,3,1)
1910 blr
1911 function_epilog(mftlb2)
1912
1913 /*----------------------------------------------------------------------------+
1914 | mttlb1.
1915 +----------------------------------------------------------------------------*/
1916 function_prolog(mttlb1)
1917 TLBWE(4,3,0)
1918 blr
1919 function_epilog(mttlb1)
1920
1921 /*----------------------------------------------------------------------------+
1922 | mftlb1.
1923 +----------------------------------------------------------------------------*/
1924 function_prolog(mftlb1)
1925 TLBRE(3,3,0)
1926 blr
1927 function_epilog(mftlb1)
1928 #endif /* CONFIG_440 */
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