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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / start.S
1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27 /*------------------------------------------------------------------------------+
28 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
30 *
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
37 *
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
41 *
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
45 *
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
49 */
50
51 /*
52 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
53 *
54 * The following description only applies to the NOR flash style booting.
55 * NAND booting is different. For more details about NAND booting on 4xx
56 * take a look at doc/README.nand-boot-ppc440.
57 *
58 * The CPU starts at address 0xfffffffc (last word in the address space).
59 * The U-Boot image therefore has to be located in the "upper" area of the
60 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
61 * the boot chip-select (CS0) is quite big and covers this area. On the
62 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
63 * reconfigure this CS0 (and other chip-selects as well when configured
64 * this way) in the boot process to the "correct" values matching the
65 * board layout.
66 */
67
68 #include <asm-offsets.h>
69 #include <config.h>
70 #include <asm/ppc4xx.h>
71 #include <version.h>
72
73 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
74
75 #include <ppc_asm.tmpl>
76 #include <ppc_defs.h>
77
78 #include <asm/cache.h>
79 #include <asm/mmu.h>
80 #include <asm/ppc4xx-isram.h>
81
82 #ifdef CONFIG_SYS_INIT_DCACHE_CS
83 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
84 # define PBxAP PB1AP
85 # define PBxCR PB0CR
86 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
87 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
88 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
89 # endif
90 # endif
91 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
92 # define PBxAP PB1AP
93 # define PBxCR PB1CR
94 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
95 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
96 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
97 # endif
98 # endif
99 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
100 # define PBxAP PB2AP
101 # define PBxCR PB2CR
102 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
103 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
104 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
105 # endif
106 # endif
107 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
108 # define PBxAP PB3AP
109 # define PBxCR PB3CR
110 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
111 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
112 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
113 # endif
114 # endif
115 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
116 # define PBxAP PB4AP
117 # define PBxCR PB4CR
118 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
119 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
120 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
121 # endif
122 # endif
123 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
124 # define PBxAP PB5AP
125 # define PBxCR PB5CR
126 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
127 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
128 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
129 # endif
130 # endif
131 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
132 # define PBxAP PB6AP
133 # define PBxCR PB6CR
134 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
135 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
136 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
137 # endif
138 # endif
139 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
140 # define PBxAP PB7AP
141 # define PBxCR PB7CR
142 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
143 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
144 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
145 # endif
146 # endif
147 # ifndef PBxAP_VAL
148 # define PBxAP_VAL 0
149 # endif
150 # ifndef PBxCR_VAL
151 # define PBxCR_VAL 0
152 # endif
153 /*
154 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
155 * used as temporary stack pointer for the primordial stack
156 */
157 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
158 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
159 EBC_BXAP_TWT_ENCODE(7) | \
160 EBC_BXAP_BCE_DISABLE | \
161 EBC_BXAP_BCT_2TRANS | \
162 EBC_BXAP_CSN_ENCODE(0) | \
163 EBC_BXAP_OEN_ENCODE(0) | \
164 EBC_BXAP_WBN_ENCODE(0) | \
165 EBC_BXAP_WBF_ENCODE(0) | \
166 EBC_BXAP_TH_ENCODE(2) | \
167 EBC_BXAP_RE_DISABLED | \
168 EBC_BXAP_SOR_NONDELAYED | \
169 EBC_BXAP_BEM_WRITEONLY | \
170 EBC_BXAP_PEN_DISABLED)
171 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
172 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
173 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
174 EBC_BXCR_BS_64MB | \
175 EBC_BXCR_BU_RW | \
176 EBC_BXCR_BW_16BIT)
177 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
178 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
179 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
180 # endif
181 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
182
183 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
184 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
185 #endif
186
187 /*
188 * Unless otherwise overriden, enable two 128MB cachable instruction regions
189 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
190 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
191 */
192 #if !defined(CONFIG_SYS_FLASH_BASE)
193 /* If not already defined, set it to the "last" 128MByte region */
194 # define CONFIG_SYS_FLASH_BASE 0xf8000000
195 #endif
196 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
197 # define CONFIG_SYS_ICACHE_SACR_VALUE \
198 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
199 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
200 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
201 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
202
203 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
204 # define CONFIG_SYS_DCACHE_SACR_VALUE \
205 (0x00000000)
206 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
207
208 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
209 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
210 #endif
211
212 #define function_prolog(func_name) .text; \
213 .align 2; \
214 .globl func_name; \
215 func_name:
216 #define function_epilog(func_name) .type func_name,@function; \
217 .size func_name,.-func_name
218
219 /* We don't want the MMU yet.
220 */
221 #undef MSR_KERNEL
222 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
223
224
225 .extern ext_bus_cntlr_init
226 #ifdef CONFIG_NAND_U_BOOT
227 .extern reconfig_tlb0
228 #endif
229
230 /*
231 * Set up GOT: Global Offset Table
232 *
233 * Use r12 to access the GOT
234 */
235 #if !defined(CONFIG_NAND_SPL)
236 START_GOT
237 GOT_ENTRY(_GOT2_TABLE_)
238 GOT_ENTRY(_FIXUP_TABLE_)
239
240 GOT_ENTRY(_start)
241 GOT_ENTRY(_start_of_vectors)
242 GOT_ENTRY(_end_of_vectors)
243 GOT_ENTRY(transfer_to_handler)
244
245 GOT_ENTRY(__init_end)
246 GOT_ENTRY(__bss_end__)
247 GOT_ENTRY(__bss_start)
248 END_GOT
249 #endif /* CONFIG_NAND_SPL */
250
251 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
252 /*
253 * NAND U-Boot image is started from offset 0
254 */
255 .text
256 #if defined(CONFIG_440)
257 bl reconfig_tlb0
258 #endif
259 GET_GOT
260 bl cpu_init_f /* run low-level CPU init code (from Flash) */
261 bl board_init_f
262 /* NOTREACHED - board_init_f() does not return */
263 #endif
264
265 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
266 /*
267 * 4xx RAM-booting U-Boot image is started from offset 0
268 */
269 .text
270 bl _start_440
271 #endif
272
273 /*
274 * 440 Startup -- on reset only the top 4k of the effective
275 * address space is mapped in by an entry in the instruction
276 * and data shadow TLB. The .bootpg section is located in the
277 * top 4k & does only what's necessary to map in the the rest
278 * of the boot rom. Once the boot rom is mapped in we can
279 * proceed with normal startup.
280 *
281 * NOTE: CS0 only covers the top 2MB of the effective address
282 * space after reset.
283 */
284
285 #if defined(CONFIG_440)
286 #if !defined(CONFIG_NAND_SPL)
287 .section .bootpg,"ax"
288 #endif
289 .globl _start_440
290
291 /**************************************************************************/
292 _start_440:
293 /*--------------------------------------------------------------------+
294 | 440EPX BUP Change - Hardware team request
295 +--------------------------------------------------------------------*/
296 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
297 sync
298 nop
299 nop
300 #endif
301 /*----------------------------------------------------------------+
302 | Core bug fix. Clear the esr
303 +-----------------------------------------------------------------*/
304 li r0,0
305 mtspr SPRN_ESR,r0
306 /*----------------------------------------------------------------*/
307 /* Clear and set up some registers. */
308 /*----------------------------------------------------------------*/
309 iccci r0,r0 /* NOTE: operands not used for 440 */
310 dccci r0,r0 /* NOTE: operands not used for 440 */
311 sync
312 li r0,0
313 mtspr SPRN_SRR0,r0
314 mtspr SPRN_SRR1,r0
315 mtspr SPRN_CSRR0,r0
316 mtspr SPRN_CSRR1,r0
317 /* NOTE: 440GX adds machine check status regs */
318 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
319 mtspr SPRN_MCSRR0,r0
320 mtspr SPRN_MCSRR1,r0
321 mfspr r1,SPRN_MCSR
322 mtspr SPRN_MCSR,r1
323 #endif
324
325 /*----------------------------------------------------------------*/
326 /* CCR0 init */
327 /*----------------------------------------------------------------*/
328 /* Disable store gathering & broadcast, guarantee inst/data
329 * cache block touch, force load/store alignment
330 * (see errata 1.12: 440_33)
331 */
332 lis r1,0x0030 /* store gathering & broadcast disable */
333 ori r1,r1,0x6000 /* cache touch */
334 mtspr SPRN_CCR0,r1
335
336 /*----------------------------------------------------------------*/
337 /* Initialize debug */
338 /*----------------------------------------------------------------*/
339 mfspr r1,SPRN_DBCR0
340 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
341 bne skip_debug_init /* if set, don't clear debug register */
342 mfspr r1,SPRN_CCR0
343 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
344 mtspr SPRN_CCR0,r1
345 mtspr SPRN_DBCR0,r0
346 mtspr SPRN_DBCR1,r0
347 mtspr SPRN_DBCR2,r0
348 mtspr SPRN_IAC1,r0
349 mtspr SPRN_IAC2,r0
350 mtspr SPRN_IAC3,r0
351 mtspr SPRN_DAC1,r0
352 mtspr SPRN_DAC2,r0
353 mtspr SPRN_DVC1,r0
354 mtspr SPRN_DVC2,r0
355
356 mfspr r1,SPRN_DBSR
357 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
358 skip_debug_init:
359
360 #if defined (CONFIG_440SPE)
361 /*----------------------------------------------------------------+
362 | Initialize Core Configuration Reg1.
363 | a. ICDPEI: Record even parity. Normal operation.
364 | b. ICTPEI: Record even parity. Normal operation.
365 | c. DCTPEI: Record even parity. Normal operation.
366 | d. DCDPEI: Record even parity. Normal operation.
367 | e. DCUPEI: Record even parity. Normal operation.
368 | f. DCMPEI: Record even parity. Normal operation.
369 | g. FCOM: Normal operation
370 | h. MMUPEI: Record even parity. Normal operation.
371 | i. FFF: Flush only as much data as necessary.
372 | j. TCS: Timebase increments from CPU clock.
373 +-----------------------------------------------------------------*/
374 li r0,0
375 mtspr SPRN_CCR1, r0
376
377 /*----------------------------------------------------------------+
378 | Reset the timebase.
379 | The previous write to CCR1 sets the timebase source.
380 +-----------------------------------------------------------------*/
381 mtspr SPRN_TBWL, r0
382 mtspr SPRN_TBWU, r0
383 #endif
384
385 /*----------------------------------------------------------------*/
386 /* Setup interrupt vectors */
387 /*----------------------------------------------------------------*/
388 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
389 li r1,0x0100
390 mtspr SPRN_IVOR0,r1 /* Critical input */
391 li r1,0x0200
392 mtspr SPRN_IVOR1,r1 /* Machine check */
393 li r1,0x0300
394 mtspr SPRN_IVOR2,r1 /* Data storage */
395 li r1,0x0400
396 mtspr SPRN_IVOR3,r1 /* Instruction storage */
397 li r1,0x0500
398 mtspr SPRN_IVOR4,r1 /* External interrupt */
399 li r1,0x0600
400 mtspr SPRN_IVOR5,r1 /* Alignment */
401 li r1,0x0700
402 mtspr SPRN_IVOR6,r1 /* Program check */
403 li r1,0x0800
404 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
405 li r1,0x0c00
406 mtspr SPRN_IVOR8,r1 /* System call */
407 li r1,0x0a00
408 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
409 li r1,0x0900
410 mtspr SPRN_IVOR10,r1 /* Decrementer */
411 li r1,0x1300
412 mtspr SPRN_IVOR13,r1 /* Data TLB error */
413 li r1,0x1400
414 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
415 li r1,0x2000
416 mtspr SPRN_IVOR15,r1 /* Debug */
417
418 /*----------------------------------------------------------------*/
419 /* Configure cache regions */
420 /*----------------------------------------------------------------*/
421 mtspr SPRN_INV0,r0
422 mtspr SPRN_INV1,r0
423 mtspr SPRN_INV2,r0
424 mtspr SPRN_INV3,r0
425 mtspr SPRN_DNV0,r0
426 mtspr SPRN_DNV1,r0
427 mtspr SPRN_DNV2,r0
428 mtspr SPRN_DNV3,r0
429 mtspr SPRN_ITV0,r0
430 mtspr SPRN_ITV1,r0
431 mtspr SPRN_ITV2,r0
432 mtspr SPRN_ITV3,r0
433 mtspr SPRN_DTV0,r0
434 mtspr SPRN_DTV1,r0
435 mtspr SPRN_DTV2,r0
436 mtspr SPRN_DTV3,r0
437
438 /*----------------------------------------------------------------*/
439 /* Cache victim limits */
440 /*----------------------------------------------------------------*/
441 /* floors 0, ceiling max to use the entire cache -- nothing locked
442 */
443 lis r1,0x0001
444 ori r1,r1,0xf800
445 mtspr SPRN_IVLIM,r1
446 mtspr SPRN_DVLIM,r1
447
448 /*----------------------------------------------------------------+
449 |Initialize MMUCR[STID] = 0.
450 +-----------------------------------------------------------------*/
451 mfspr r0,SPRN_MMUCR
452 addis r1,0,0xFFFF
453 ori r1,r1,0xFF00
454 and r0,r0,r1
455 mtspr SPRN_MMUCR,r0
456
457 /*----------------------------------------------------------------*/
458 /* Clear all TLB entries -- TID = 0, TS = 0 */
459 /*----------------------------------------------------------------*/
460 addis r0,0,0x0000
461 #ifdef CONFIG_SYS_RAMBOOT
462 li r4,0 /* Start with TLB #0 */
463 #else
464 li r4,1 /* Start with TLB #1 */
465 #endif
466 li r1,64 /* 64 TLB entries */
467 sub r1,r1,r4 /* calculate last TLB # */
468 mtctr r1
469 rsttlb:
470 #ifdef CONFIG_SYS_RAMBOOT
471 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
472 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
473 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
474 #endif
475 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
476 tlbwe r0,r4,1
477 tlbwe r0,r4,2
478 tlbnxt: addi r4,r4,1 /* Next TLB */
479 bdnz rsttlb
480
481 /*----------------------------------------------------------------*/
482 /* TLB entry setup -- step thru tlbtab */
483 /*----------------------------------------------------------------*/
484 #if defined(CONFIG_440SPE_REVA)
485 /*----------------------------------------------------------------*/
486 /* We have different TLB tables for revA and rev B of 440SPe */
487 /*----------------------------------------------------------------*/
488 mfspr r1, PVR
489 lis r0,0x5342
490 ori r0,r0,0x1891
491 cmpw r7,r1,r0
492 bne r7,..revA
493 bl tlbtabB
494 b ..goon
495 ..revA:
496 bl tlbtabA
497 ..goon:
498 #else
499 bl tlbtab /* Get tlbtab pointer */
500 #endif
501 mr r5,r0
502 li r1,0x003f /* 64 TLB entries max */
503 mtctr r1
504 li r4,0 /* TLB # */
505
506 addi r5,r5,-4
507 1:
508 #ifdef CONFIG_SYS_RAMBOOT
509 tlbre r3,r4,0 /* Read contents from TLB word #0 */
510 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
511 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
512 #endif
513 lwzu r0,4(r5)
514 cmpwi r0,0
515 beq 2f /* 0 marks end */
516 lwzu r1,4(r5)
517 lwzu r2,4(r5)
518 tlbwe r0,r4,0 /* TLB Word 0 */
519 tlbwe r1,r4,1 /* TLB Word 1 */
520 tlbwe r2,r4,2 /* TLB Word 2 */
521 tlbnx2: addi r4,r4,1 /* Next TLB */
522 bdnz 1b
523
524 /*----------------------------------------------------------------*/
525 /* Continue from 'normal' start */
526 /*----------------------------------------------------------------*/
527 2:
528 bl 3f
529 b _start
530
531 3: li r0,0
532 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
533 mflr r1
534 mtspr SPRN_SRR0,r1
535 rfi
536 #endif /* CONFIG_440 */
537
538 /*
539 * r3 - 1st arg to board_init(): IMMP pointer
540 * r4 - 2nd arg to board_init(): boot flag
541 */
542 #ifndef CONFIG_NAND_SPL
543 .text
544 .long 0x27051956 /* U-Boot Magic Number */
545 .globl version_string
546 version_string:
547 .ascii U_BOOT_VERSION_STRING, "\0"
548
549 . = EXC_OFF_SYS_RESET
550 .globl _start_of_vectors
551 _start_of_vectors:
552
553 /* Critical input. */
554 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
555
556 #ifdef CONFIG_440
557 /* Machine check */
558 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
559 #else
560 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
561 #endif /* CONFIG_440 */
562
563 /* Data Storage exception. */
564 STD_EXCEPTION(0x300, DataStorage, UnknownException)
565
566 /* Instruction Storage exception. */
567 STD_EXCEPTION(0x400, InstStorage, UnknownException)
568
569 /* External Interrupt exception. */
570 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
571
572 /* Alignment exception. */
573 . = 0x600
574 Alignment:
575 EXCEPTION_PROLOG(SRR0, SRR1)
576 mfspr r4,DAR
577 stw r4,_DAR(r21)
578 mfspr r5,DSISR
579 stw r5,_DSISR(r21)
580 addi r3,r1,STACK_FRAME_OVERHEAD
581 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
582
583 /* Program check exception */
584 . = 0x700
585 ProgramCheck:
586 EXCEPTION_PROLOG(SRR0, SRR1)
587 addi r3,r1,STACK_FRAME_OVERHEAD
588 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
589 MSR_KERNEL, COPY_EE)
590
591 #ifdef CONFIG_440
592 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
593 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
594 STD_EXCEPTION(0xa00, APU, UnknownException)
595 #endif
596 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
597
598 #ifdef CONFIG_440
599 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
600 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
601 #else
602 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
603 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
604 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
605 #endif
606 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
607
608 .globl _end_of_vectors
609 _end_of_vectors:
610 . = _START_OFFSET
611 #endif
612 .globl _start
613 _start:
614
615 /*****************************************************************************/
616 #if defined(CONFIG_440)
617
618 /*----------------------------------------------------------------*/
619 /* Clear and set up some registers. */
620 /*----------------------------------------------------------------*/
621 li r0,0x0000
622 lis r1,0xffff
623 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
624 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
625 mtspr SPRN_TBWU,r0
626 mtspr SPRN_TSR,r1 /* clear all timer exception status */
627 mtspr SPRN_TCR,r0 /* disable all */
628 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
629 mtxer r0 /* clear integer exception register */
630
631 /*----------------------------------------------------------------*/
632 /* Debug setup -- some (not very good) ice's need an event*/
633 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
634 /* value you need in this case 0x8cff 0000 should do the trick */
635 /*----------------------------------------------------------------*/
636 #if defined(CONFIG_SYS_INIT_DBCR)
637 lis r1,0xffff
638 ori r1,r1,0xffff
639 mtspr SPRN_DBSR,r1 /* Clear all status bits */
640 lis r0,CONFIG_SYS_INIT_DBCR@h
641 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
642 mtspr SPRN_DBCR0,r0
643 isync
644 #endif
645
646 /*----------------------------------------------------------------*/
647 /* Setup the internal SRAM */
648 /*----------------------------------------------------------------*/
649 li r0,0
650
651 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
652 /* Clear Dcache to use as RAM */
653 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
654 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
655 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
656 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
657 rlwinm. r5,r4,0,27,31
658 rlwinm r5,r4,27,5,31
659 beq ..d_ran
660 addi r5,r5,0x0001
661 ..d_ran:
662 mtctr r5
663 ..d_ag:
664 dcbz r0,r3
665 addi r3,r3,32
666 bdnz ..d_ag
667
668 /*
669 * Lock the init-ram/stack in d-cache, so that other regions
670 * may use d-cache as well
671 * Note, that this current implementation locks exactly 4k
672 * of d-cache, so please make sure that you don't define a
673 * bigger init-ram area. Take a look at the lwmon5 440EPx
674 * implementation as a reference.
675 */
676 msync
677 isync
678 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
679 lis r1,0x0201
680 ori r1,r1,0xf808
681 mtspr SPRN_DVLIM,r1
682 lis r1,0x0808
683 ori r1,r1,0x0808
684 mtspr SPRN_DNV0,r1
685 mtspr SPRN_DNV1,r1
686 mtspr SPRN_DNV2,r1
687 mtspr SPRN_DNV3,r1
688 mtspr SPRN_DTV0,r1
689 mtspr SPRN_DTV1,r1
690 mtspr SPRN_DTV2,r1
691 mtspr SPRN_DTV3,r1
692 msync
693 isync
694 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
695
696 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
697 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
698 /* not all PPC's have internal SRAM usable as L2-cache */
699 #if defined(CONFIG_440GX) || \
700 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
701 defined(CONFIG_460SX)
702 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
703 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
704 defined(CONFIG_APM821XX)
705 lis r1, 0x0000
706 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
707 mtdcr L2_CACHE_CFG,r1
708 #endif
709
710 lis r2,0x7fff
711 ori r2,r2,0xffff
712 mfdcr r1,ISRAM0_DPC
713 and r1,r1,r2 /* Disable parity check */
714 mtdcr ISRAM0_DPC,r1
715 mfdcr r1,ISRAM0_PMEG
716 and r1,r1,r2 /* Disable pwr mgmt */
717 mtdcr ISRAM0_PMEG,r1
718
719 lis r1,0x8000 /* BAS = 8000_0000 */
720 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
721 ori r1,r1,0x0980 /* first 64k */
722 mtdcr ISRAM0_SB0CR,r1
723 lis r1,0x8001
724 ori r1,r1,0x0980 /* second 64k */
725 mtdcr ISRAM0_SB1CR,r1
726 lis r1, 0x8002
727 ori r1,r1, 0x0980 /* third 64k */
728 mtdcr ISRAM0_SB2CR,r1
729 lis r1, 0x8003
730 ori r1,r1, 0x0980 /* fourth 64k */
731 mtdcr ISRAM0_SB3CR,r1
732 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
733 defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
734 lis r1,0x0000 /* BAS = X_0000_0000 */
735 ori r1,r1,0x0984 /* first 64k */
736 mtdcr ISRAM0_SB0CR,r1
737 lis r1,0x0001
738 ori r1,r1,0x0984 /* second 64k */
739 mtdcr ISRAM0_SB1CR,r1
740 lis r1, 0x0002
741 ori r1,r1, 0x0984 /* third 64k */
742 mtdcr ISRAM0_SB2CR,r1
743 lis r1, 0x0003
744 ori r1,r1, 0x0984 /* fourth 64k */
745 mtdcr ISRAM0_SB3CR,r1
746 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
747 defined(CONFIG_APM821XX)
748 lis r2,0x7fff
749 ori r2,r2,0xffff
750 mfdcr r1,ISRAM1_DPC
751 and r1,r1,r2 /* Disable parity check */
752 mtdcr ISRAM1_DPC,r1
753 mfdcr r1,ISRAM1_PMEG
754 and r1,r1,r2 /* Disable pwr mgmt */
755 mtdcr ISRAM1_PMEG,r1
756
757 lis r1,0x0004 /* BAS = 4_0004_0000 */
758 ori r1,r1,ISRAM1_SIZE /* ocm size */
759 mtdcr ISRAM1_SB0CR,r1
760 #endif
761 #elif defined(CONFIG_460SX)
762 lis r1,0x0000 /* BAS = 0000_0000 */
763 ori r1,r1,0x0B84 /* first 128k */
764 mtdcr ISRAM0_SB0CR,r1
765 lis r1,0x0001
766 ori r1,r1,0x0B84 /* second 128k */
767 mtdcr ISRAM0_SB1CR,r1
768 lis r1, 0x0002
769 ori r1,r1, 0x0B84 /* third 128k */
770 mtdcr ISRAM0_SB2CR,r1
771 lis r1, 0x0003
772 ori r1,r1, 0x0B84 /* fourth 128k */
773 mtdcr ISRAM0_SB3CR,r1
774 #elif defined(CONFIG_440GP)
775 ori r1,r1,0x0380 /* 8k rw */
776 mtdcr ISRAM0_SB0CR,r1
777 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
778 #endif
779 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
780
781 /*----------------------------------------------------------------*/
782 /* Setup the stack in internal SRAM */
783 /*----------------------------------------------------------------*/
784 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
785 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
786 li r0,0
787 stwu r0,-4(r1)
788 stwu r0,-4(r1) /* Terminate call chain */
789
790 stwu r1,-8(r1) /* Save back chain and move SP */
791 lis r0,RESET_VECTOR@h /* Address of reset vector */
792 ori r0,r0, RESET_VECTOR@l
793 stwu r1,-8(r1) /* Save back chain and move SP */
794 stw r0,+12(r1) /* Save return addr (underflow vect) */
795
796 #ifdef CONFIG_NAND_SPL
797 bl nand_boot_common /* will not return */
798 #else
799 GET_GOT
800
801 bl cpu_init_f /* run low-level CPU init code (from Flash) */
802 bl board_init_f
803 /* NOTREACHED - board_init_f() does not return */
804 #endif
805
806 #endif /* CONFIG_440 */
807
808 /*****************************************************************************/
809 #ifdef CONFIG_IOP480
810 /*----------------------------------------------------------------------- */
811 /* Set up some machine state registers. */
812 /*----------------------------------------------------------------------- */
813 addi r0,r0,0x0000 /* initialize r0 to zero */
814 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
815 mttcr r0 /* timer control register */
816 mtexier r0 /* disable all interrupts */
817 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
818 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
819 mtdbsr r4 /* clear/reset the dbsr */
820 mtexisr r4 /* clear all pending interrupts */
821 addis r4,r0,0x8000
822 mtexier r4 /* enable critical exceptions */
823 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
824 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
825 mtiocr r4 /* since bit not used) & DRC to latch */
826 /* data bus on rising edge of CAS */
827 /*----------------------------------------------------------------------- */
828 /* Clear XER. */
829 /*----------------------------------------------------------------------- */
830 mtxer r0
831 /*----------------------------------------------------------------------- */
832 /* Invalidate i-cache and d-cache TAG arrays. */
833 /*----------------------------------------------------------------------- */
834 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
835 addi r4,0,1024 /* 1/4 of I-cache */
836 ..cloop:
837 iccci 0,r3
838 iccci r4,r3
839 dccci 0,r3
840 addic. r3,r3,-16 /* move back one cache line */
841 bne ..cloop /* loop back to do rest until r3 = 0 */
842
843 /* */
844 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
845 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
846 /* */
847
848 /* first copy IOP480 register base address into r3 */
849 addis r3,0,0x5000 /* IOP480 register base address hi */
850 /* ori r3,r3,0x0000 / IOP480 register base address lo */
851
852 #ifdef CONFIG_ADCIOP
853 /* use r4 as the working variable */
854 /* turn on CS3 (LOCCTL.7) */
855 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
856 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
857 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
858 #endif
859
860 #ifdef CONFIG_DASA_SIM
861 /* use r4 as the working variable */
862 /* turn on MA17 (LOCCTL.7) */
863 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
864 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
865 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
866 #endif
867
868 /* turn on MA16..13 (LCS0BRD.12 = 0) */
869 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
870 andi. r4,r4,0xefff /* make bit 12 = 0 */
871 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
872
873 /* make sure above stores all comlete before going on */
874 sync
875
876 /* last thing, set local init status done bit (DEVINIT.31) */
877 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
878 oris r4,r4,0x8000 /* make bit 31 = 1 */
879 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
880
881 /* clear all pending interrupts and disable all interrupts */
882 li r4,-1 /* set p1 to 0xffffffff */
883 stw r4,0x1b0(r3) /* clear all pending interrupts */
884 stw r4,0x1b8(r3) /* clear all pending interrupts */
885 li r4,0 /* set r4 to 0 */
886 stw r4,0x1b4(r3) /* disable all interrupts */
887 stw r4,0x1bc(r3) /* disable all interrupts */
888
889 /* make sure above stores all comlete before going on */
890 sync
891
892 /* Set-up icache cacheability. */
893 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
894 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
895 mticcr r1
896 isync
897
898 /* Set-up dcache cacheability. */
899 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
900 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
901 mtdccr r1
902
903 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
904 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
905 li r0, 0 /* Make room for stack frame header and */
906 stwu r0, -4(r1) /* clear final stack frame so that */
907 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
908
909 GET_GOT /* initialize GOT access */
910
911 bl board_init_f /* run first part of init code (from Flash) */
912 /* NOTREACHED - board_init_f() does not return */
913
914 #endif /* CONFIG_IOP480 */
915
916 /*****************************************************************************/
917 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
918 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
919 defined(CONFIG_405EX) || defined(CONFIG_405)
920 /*----------------------------------------------------------------------- */
921 /* Clear and set up some registers. */
922 /*----------------------------------------------------------------------- */
923 addi r4,r0,0x0000
924 #if !defined(CONFIG_405EX)
925 mtspr SPRN_SGR,r4
926 #else
927 /*
928 * On 405EX, completely clearing the SGR leads to PPC hangup
929 * upon PCIe configuration access. The PCIe memory regions
930 * need to be guarded!
931 */
932 lis r3,0x0000
933 ori r3,r3,0x7FFC
934 mtspr SPRN_SGR,r3
935 #endif
936 mtspr SPRN_DCWR,r4
937 mtesr r4 /* clear Exception Syndrome Reg */
938 mttcr r4 /* clear Timer Control Reg */
939 mtxer r4 /* clear Fixed-Point Exception Reg */
940 mtevpr r4 /* clear Exception Vector Prefix Reg */
941 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
942 /* dbsr is cleared by setting bits to 1) */
943 mtdbsr r4 /* clear/reset the dbsr */
944
945 /* Invalidate the i- and d-caches. */
946 bl invalidate_icache
947 bl invalidate_dcache
948
949 /* Set-up icache cacheability. */
950 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
951 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
952 mticcr r4
953 isync
954
955 /* Set-up dcache cacheability. */
956 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
957 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
958 mtdccr r4
959
960 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
961 && !defined (CONFIG_XILINX_405)
962 /*----------------------------------------------------------------------- */
963 /* Tune the speed and size for flash CS0 */
964 /*----------------------------------------------------------------------- */
965 bl ext_bus_cntlr_init
966 #endif
967
968 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
969 /*
970 * For boards that don't have OCM and can't use the data cache
971 * for their primordial stack, setup stack here directly after the
972 * SDRAM is initialized in ext_bus_cntlr_init.
973 */
974 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
975 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
976
977 li r0, 0 /* Make room for stack frame header and */
978 stwu r0, -4(r1) /* clear final stack frame so that */
979 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
980 /*
981 * Set up a dummy frame to store reset vector as return address.
982 * this causes stack underflow to reset board.
983 */
984 stwu r1, -8(r1) /* Save back chain and move SP */
985 lis r0, RESET_VECTOR@h /* Address of reset vector */
986 ori r0, r0, RESET_VECTOR@l
987 stwu r1, -8(r1) /* Save back chain and move SP */
988 stw r0, +12(r1) /* Save return addr (underflow vect) */
989 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
990
991 #if defined(CONFIG_405EP)
992 /*----------------------------------------------------------------------- */
993 /* DMA Status, clear to come up clean */
994 /*----------------------------------------------------------------------- */
995 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
996 ori r3,r3, 0xFFFF
997 mtdcr DMASR, r3
998
999 bl ppc405ep_init /* do ppc405ep specific init */
1000 #endif /* CONFIG_405EP */
1001
1002 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
1003 #if defined(CONFIG_405EZ)
1004 /********************************************************************
1005 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1006 *******************************************************************/
1007 /*
1008 * We can map the OCM on the PLB3, so map it at
1009 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1010 */
1011 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1012 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1013 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1014 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
1015 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1016 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
1017 isync
1018
1019 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1020 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1021 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1022 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1023 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
1024 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1025 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1026 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
1027 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1028 mtdcr OCM0_DISDPC,r3
1029
1030 isync
1031 #else /* CONFIG_405EZ */
1032 /********************************************************************
1033 * Setup OCM - On Chip Memory
1034 *******************************************************************/
1035 /* Setup OCM */
1036 lis r0, 0x7FFF
1037 ori r0, r0, 0xFFFF
1038 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1039 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
1040 and r3, r3, r0 /* disable data-side IRAM */
1041 and r4, r4, r0 /* disable data-side IRAM */
1042 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1043 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
1044 isync
1045
1046 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1047 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1048 mtdcr OCM0_DSARC, r3
1049 addis r4, 0, 0xC000 /* OCM data area enabled */
1050 mtdcr OCM0_DSCNTL, r4
1051 isync
1052 #endif /* CONFIG_405EZ */
1053 #endif
1054
1055 /*----------------------------------------------------------------------- */
1056 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1057 /*----------------------------------------------------------------------- */
1058 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1059 li r4, PBxAP
1060 mtdcr EBC0_CFGADDR, r4
1061 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1062 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1063 mtdcr EBC0_CFGDATA, r4
1064
1065 addi r4, 0, PBxCR
1066 mtdcr EBC0_CFGADDR, r4
1067 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1068 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1069 mtdcr EBC0_CFGDATA, r4
1070
1071 /*
1072 * Enable the data cache for the 128MB storage access control region
1073 * at CONFIG_SYS_INIT_RAM_ADDR.
1074 */
1075 mfdccr r4
1076 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1077 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1078 mtdccr r4
1079
1080 /*
1081 * Preallocate data cache lines to be used to avoid a subsequent
1082 * cache miss and an ensuing machine check exception when exceptions
1083 * are enabled.
1084 */
1085 li r0, 0
1086
1087 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1088 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1089
1090 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1091 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1092
1093 /*
1094 * Convert the size, in bytes, to the number of cache lines/blocks
1095 * to preallocate.
1096 */
1097 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1098 srwi r5, r4, L1_CACHE_SHIFT
1099 beq ..load_counter
1100 addi r5, r5, 0x0001
1101 ..load_counter:
1102 mtctr r5
1103
1104 /* Preallocate the computed number of cache blocks. */
1105 ..alloc_dcache_block:
1106 dcba r0, r3
1107 addi r3, r3, L1_CACHE_BYTES
1108 bdnz ..alloc_dcache_block
1109 sync
1110
1111 /*
1112 * Load the initial stack pointer and data area and convert the size,
1113 * in bytes, to the number of words to initialize to a known value.
1114 */
1115 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1116 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1117
1118 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
1119 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1120 mtctr r4
1121
1122 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1123 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1124
1125 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1126 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1127
1128 ..stackloop:
1129 stwu r4, -4(r2)
1130 bdnz ..stackloop
1131
1132 /*
1133 * Make room for stack frame header and clear final stack frame so
1134 * that stack backtraces terminate cleanly.
1135 */
1136 stwu r0, -4(r1)
1137 stwu r0, -4(r1)
1138
1139 /*
1140 * Set up a dummy frame to store reset vector as return address.
1141 * this causes stack underflow to reset board.
1142 */
1143 stwu r1, -8(r1) /* Save back chain and move SP */
1144 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1145 ori r0, r0, RESET_VECTOR@l
1146 stwu r1, -8(r1) /* Save back chain and move SP */
1147 stw r0, +12(r1) /* Save return addr (underflow vect) */
1148
1149 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1150 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1151 /*
1152 * Stack in OCM.
1153 */
1154
1155 /* Set up Stack at top of OCM */
1156 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1157 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1158
1159 /* Set up a zeroized stack frame so that backtrace works right */
1160 li r0, 0
1161 stwu r0, -4(r1)
1162 stwu r0, -4(r1)
1163
1164 /*
1165 * Set up a dummy frame to store reset vector as return address.
1166 * this causes stack underflow to reset board.
1167 */
1168 stwu r1, -8(r1) /* Save back chain and move SP */
1169 lis r0, RESET_VECTOR@h /* Address of reset vector */
1170 ori r0, r0, RESET_VECTOR@l
1171 stwu r1, -8(r1) /* Save back chain and move SP */
1172 stw r0, +12(r1) /* Save return addr (underflow vect) */
1173 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1174
1175 #ifdef CONFIG_NAND_SPL
1176 bl nand_boot_common /* will not return */
1177 #else
1178 GET_GOT /* initialize GOT access */
1179
1180 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1181
1182 bl board_init_f /* run first part of init code (from Flash) */
1183 /* NOTREACHED - board_init_f() does not return */
1184
1185 #endif /* CONFIG_NAND_SPL */
1186
1187 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1188 /*----------------------------------------------------------------------- */
1189
1190
1191 #ifndef CONFIG_NAND_SPL
1192 /*
1193 * This code finishes saving the registers to the exception frame
1194 * and jumps to the appropriate handler for the exception.
1195 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1196 */
1197 .globl transfer_to_handler
1198 transfer_to_handler:
1199 stw r22,_NIP(r21)
1200 lis r22,MSR_POW@h
1201 andc r23,r23,r22
1202 stw r23,_MSR(r21)
1203 SAVE_GPR(7, r21)
1204 SAVE_4GPRS(8, r21)
1205 SAVE_8GPRS(12, r21)
1206 SAVE_8GPRS(24, r21)
1207 mflr r23
1208 andi. r24,r23,0x3f00 /* get vector offset */
1209 stw r24,TRAP(r21)
1210 li r22,0
1211 stw r22,RESULT(r21)
1212 mtspr SPRG2,r22 /* r1 is now kernel sp */
1213 lwz r24,0(r23) /* virtual address of handler */
1214 lwz r23,4(r23) /* where to go when done */
1215 mtspr SRR0,r24
1216 mtspr SRR1,r20
1217 mtlr r23
1218 SYNC
1219 rfi /* jump to handler, enable MMU */
1220
1221 int_return:
1222 mfmsr r28 /* Disable interrupts */
1223 li r4,0
1224 ori r4,r4,MSR_EE
1225 andc r28,r28,r4
1226 SYNC /* Some chip revs need this... */
1227 mtmsr r28
1228 SYNC
1229 lwz r2,_CTR(r1)
1230 lwz r0,_LINK(r1)
1231 mtctr r2
1232 mtlr r0
1233 lwz r2,_XER(r1)
1234 lwz r0,_CCR(r1)
1235 mtspr XER,r2
1236 mtcrf 0xFF,r0
1237 REST_10GPRS(3, r1)
1238 REST_10GPRS(13, r1)
1239 REST_8GPRS(23, r1)
1240 REST_GPR(31, r1)
1241 lwz r2,_NIP(r1) /* Restore environment */
1242 lwz r0,_MSR(r1)
1243 mtspr SRR0,r2
1244 mtspr SRR1,r0
1245 lwz r0,GPR0(r1)
1246 lwz r2,GPR2(r1)
1247 lwz r1,GPR1(r1)
1248 SYNC
1249 rfi
1250
1251 crit_return:
1252 mfmsr r28 /* Disable interrupts */
1253 li r4,0
1254 ori r4,r4,MSR_EE
1255 andc r28,r28,r4
1256 SYNC /* Some chip revs need this... */
1257 mtmsr r28
1258 SYNC
1259 lwz r2,_CTR(r1)
1260 lwz r0,_LINK(r1)
1261 mtctr r2
1262 mtlr r0
1263 lwz r2,_XER(r1)
1264 lwz r0,_CCR(r1)
1265 mtspr XER,r2
1266 mtcrf 0xFF,r0
1267 REST_10GPRS(3, r1)
1268 REST_10GPRS(13, r1)
1269 REST_8GPRS(23, r1)
1270 REST_GPR(31, r1)
1271 lwz r2,_NIP(r1) /* Restore environment */
1272 lwz r0,_MSR(r1)
1273 mtspr SPRN_CSRR0,r2
1274 mtspr SPRN_CSRR1,r0
1275 lwz r0,GPR0(r1)
1276 lwz r2,GPR2(r1)
1277 lwz r1,GPR1(r1)
1278 SYNC
1279 rfci
1280
1281 #ifdef CONFIG_440
1282 mck_return:
1283 mfmsr r28 /* Disable interrupts */
1284 li r4,0
1285 ori r4,r4,MSR_EE
1286 andc r28,r28,r4
1287 SYNC /* Some chip revs need this... */
1288 mtmsr r28
1289 SYNC
1290 lwz r2,_CTR(r1)
1291 lwz r0,_LINK(r1)
1292 mtctr r2
1293 mtlr r0
1294 lwz r2,_XER(r1)
1295 lwz r0,_CCR(r1)
1296 mtspr XER,r2
1297 mtcrf 0xFF,r0
1298 REST_10GPRS(3, r1)
1299 REST_10GPRS(13, r1)
1300 REST_8GPRS(23, r1)
1301 REST_GPR(31, r1)
1302 lwz r2,_NIP(r1) /* Restore environment */
1303 lwz r0,_MSR(r1)
1304 mtspr SPRN_MCSRR0,r2
1305 mtspr SPRN_MCSRR1,r0
1306 lwz r0,GPR0(r1)
1307 lwz r2,GPR2(r1)
1308 lwz r1,GPR1(r1)
1309 SYNC
1310 rfmci
1311 #endif /* CONFIG_440 */
1312
1313
1314 .globl get_pvr
1315 get_pvr:
1316 mfspr r3, PVR
1317 blr
1318
1319 /*------------------------------------------------------------------------------- */
1320 /* Function: out16 */
1321 /* Description: Output 16 bits */
1322 /*------------------------------------------------------------------------------- */
1323 .globl out16
1324 out16:
1325 sth r4,0x0000(r3)
1326 blr
1327
1328 /*------------------------------------------------------------------------------- */
1329 /* Function: out16r */
1330 /* Description: Byte reverse and output 16 bits */
1331 /*------------------------------------------------------------------------------- */
1332 .globl out16r
1333 out16r:
1334 sthbrx r4,r0,r3
1335 blr
1336
1337 /*------------------------------------------------------------------------------- */
1338 /* Function: out32r */
1339 /* Description: Byte reverse and output 32 bits */
1340 /*------------------------------------------------------------------------------- */
1341 .globl out32r
1342 out32r:
1343 stwbrx r4,r0,r3
1344 blr
1345
1346 /*------------------------------------------------------------------------------- */
1347 /* Function: in16 */
1348 /* Description: Input 16 bits */
1349 /*------------------------------------------------------------------------------- */
1350 .globl in16
1351 in16:
1352 lhz r3,0x0000(r3)
1353 blr
1354
1355 /*------------------------------------------------------------------------------- */
1356 /* Function: in16r */
1357 /* Description: Input 16 bits and byte reverse */
1358 /*------------------------------------------------------------------------------- */
1359 .globl in16r
1360 in16r:
1361 lhbrx r3,r0,r3
1362 blr
1363
1364 /*------------------------------------------------------------------------------- */
1365 /* Function: in32r */
1366 /* Description: Input 32 bits and byte reverse */
1367 /*------------------------------------------------------------------------------- */
1368 .globl in32r
1369 in32r:
1370 lwbrx r3,r0,r3
1371 blr
1372
1373 /*
1374 * void relocate_code (addr_sp, gd, addr_moni)
1375 *
1376 * This "function" does not return, instead it continues in RAM
1377 * after relocating the monitor code.
1378 *
1379 * r3 = Relocated stack pointer
1380 * r4 = Relocated global data pointer
1381 * r5 = Relocated text pointer
1382 */
1383 .globl relocate_code
1384 relocate_code:
1385 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1386 /*
1387 * We need to flush the initial global data (gd_t) and bd_info
1388 * before the dcache will be invalidated.
1389 */
1390
1391 /* Save registers */
1392 mr r9, r3
1393 mr r10, r4
1394 mr r11, r5
1395
1396 /*
1397 * Flush complete dcache, this is faster than flushing the
1398 * ranges for global_data and bd_info instead.
1399 */
1400 bl flush_dcache
1401
1402 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1403 /*
1404 * Undo the earlier data cache set-up for the primordial stack and
1405 * data area. First, invalidate the data cache and then disable data
1406 * cacheability for that area. Finally, restore the EBC values, if
1407 * any.
1408 */
1409
1410 /* Invalidate the primordial stack and data area in cache */
1411 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1412 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1413
1414 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1415 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1416 add r4, r4, r3
1417
1418 bl invalidate_dcache_range
1419
1420 /* Disable cacheability for the region */
1421 mfdccr r3
1422 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1423 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1424 and r3, r3, r4
1425 mtdccr r3
1426
1427 /* Restore the EBC parameters */
1428 li r3, PBxAP
1429 mtdcr EBC0_CFGADDR, r3
1430 lis r3, PBxAP_VAL@h
1431 ori r3, r3, PBxAP_VAL@l
1432 mtdcr EBC0_CFGDATA, r3
1433
1434 li r3, PBxCR
1435 mtdcr EBC0_CFGADDR, r3
1436 lis r3, PBxCR_VAL@h
1437 ori r3, r3, PBxCR_VAL@l
1438 mtdcr EBC0_CFGDATA, r3
1439 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1440
1441 /* Restore registers */
1442 mr r3, r9
1443 mr r4, r10
1444 mr r5, r11
1445 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1446
1447 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1448 /*
1449 * Unlock the previously locked d-cache
1450 */
1451 msync
1452 isync
1453 /* set TFLOOR/NFLOOR to 0 again */
1454 lis r6,0x0001
1455 ori r6,r6,0xf800
1456 mtspr SPRN_DVLIM,r6
1457 lis r6,0x0000
1458 ori r6,r6,0x0000
1459 mtspr SPRN_DNV0,r6
1460 mtspr SPRN_DNV1,r6
1461 mtspr SPRN_DNV2,r6
1462 mtspr SPRN_DNV3,r6
1463 mtspr SPRN_DTV0,r6
1464 mtspr SPRN_DTV1,r6
1465 mtspr SPRN_DTV2,r6
1466 mtspr SPRN_DTV3,r6
1467 msync
1468 isync
1469
1470 /* Invalidate data cache, now no longer our stack */
1471 dccci 0,0
1472 sync
1473 isync
1474 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1475
1476 /*
1477 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1478 * to speed up the boot process. Now this cache needs to be disabled.
1479 */
1480 #if defined(CONFIG_440)
1481 /* Clear all potential pending exceptions */
1482 mfspr r1,SPRN_MCSR
1483 mtspr SPRN_MCSR,r1
1484 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1485 tlbre r0,r1,0x0002 /* Read contents */
1486 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1487 tlbwe r0,r1,0x0002 /* Save it out */
1488 sync
1489 isync
1490 #endif /* defined(CONFIG_440) */
1491 mr r1, r3 /* Set new stack pointer */
1492 mr r9, r4 /* Save copy of Init Data pointer */
1493 mr r10, r5 /* Save copy of Destination Address */
1494
1495 GET_GOT
1496 mr r3, r5 /* Destination Address */
1497 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1498 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1499 lwz r5, GOT(__init_end)
1500 sub r5, r5, r4
1501 li r6, L1_CACHE_BYTES /* Cache Line Size */
1502
1503 /*
1504 * Fix GOT pointer:
1505 *
1506 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1507 *
1508 * Offset:
1509 */
1510 sub r15, r10, r4
1511
1512 /* First our own GOT */
1513 add r12, r12, r15
1514 /* then the one used by the C code */
1515 add r30, r30, r15
1516
1517 /*
1518 * Now relocate code
1519 */
1520
1521 cmplw cr1,r3,r4
1522 addi r0,r5,3
1523 srwi. r0,r0,2
1524 beq cr1,4f /* In place copy is not necessary */
1525 beq 7f /* Protect against 0 count */
1526 mtctr r0
1527 bge cr1,2f
1528
1529 la r8,-4(r4)
1530 la r7,-4(r3)
1531 1: lwzu r0,4(r8)
1532 stwu r0,4(r7)
1533 bdnz 1b
1534 b 4f
1535
1536 2: slwi r0,r0,2
1537 add r8,r4,r0
1538 add r7,r3,r0
1539 3: lwzu r0,-4(r8)
1540 stwu r0,-4(r7)
1541 bdnz 3b
1542
1543 /*
1544 * Now flush the cache: note that we must start from a cache aligned
1545 * address. Otherwise we might miss one cache line.
1546 */
1547 4: cmpwi r6,0
1548 add r5,r3,r5
1549 beq 7f /* Always flush prefetch queue in any case */
1550 subi r0,r6,1
1551 andc r3,r3,r0
1552 mr r4,r3
1553 5: dcbst 0,r4
1554 add r4,r4,r6
1555 cmplw r4,r5
1556 blt 5b
1557 sync /* Wait for all dcbst to complete on bus */
1558 mr r4,r3
1559 6: icbi 0,r4
1560 add r4,r4,r6
1561 cmplw r4,r5
1562 blt 6b
1563 7: sync /* Wait for all icbi to complete on bus */
1564 isync
1565
1566 /*
1567 * We are done. Do not return, instead branch to second part of board
1568 * initialization, now running from RAM.
1569 */
1570
1571 addi r0, r10, in_ram - _start + _START_OFFSET
1572 mtlr r0
1573 blr /* NEVER RETURNS! */
1574
1575 in_ram:
1576
1577 /*
1578 * Relocation Function, r12 point to got2+0x8000
1579 *
1580 * Adjust got2 pointers, no need to check for 0, this code
1581 * already puts a few entries in the table.
1582 */
1583 li r0,__got2_entries@sectoff@l
1584 la r3,GOT(_GOT2_TABLE_)
1585 lwz r11,GOT(_GOT2_TABLE_)
1586 mtctr r0
1587 sub r11,r3,r11
1588 addi r3,r3,-4
1589 1: lwzu r0,4(r3)
1590 cmpwi r0,0
1591 beq- 2f
1592 add r0,r0,r11
1593 stw r0,0(r3)
1594 2: bdnz 1b
1595
1596 /*
1597 * Now adjust the fixups and the pointers to the fixups
1598 * in case we need to move ourselves again.
1599 */
1600 li r0,__fixup_entries@sectoff@l
1601 lwz r3,GOT(_FIXUP_TABLE_)
1602 cmpwi r0,0
1603 mtctr r0
1604 addi r3,r3,-4
1605 beq 4f
1606 3: lwzu r4,4(r3)
1607 lwzux r0,r4,r11
1608 cmpwi r0,0
1609 add r0,r0,r11
1610 stw r4,0(r3)
1611 beq- 5f
1612 stw r0,0(r4)
1613 5: bdnz 3b
1614 4:
1615 clear_bss:
1616 /*
1617 * Now clear BSS segment
1618 */
1619 lwz r3,GOT(__bss_start)
1620 lwz r4,GOT(__bss_end__)
1621
1622 cmplw 0, r3, r4
1623 beq 7f
1624
1625 li r0, 0
1626
1627 andi. r5, r4, 3
1628 beq 6f
1629 sub r4, r4, r5
1630 mtctr r5
1631 mr r5, r4
1632 5: stb r0, 0(r5)
1633 addi r5, r5, 1
1634 bdnz 5b
1635 6:
1636 stw r0, 0(r3)
1637 addi r3, r3, 4
1638 cmplw 0, r3, r4
1639 bne 6b
1640
1641 7:
1642 mr r3, r9 /* Init Data pointer */
1643 mr r4, r10 /* Destination Address */
1644 bl board_init_r
1645
1646 /*
1647 * Copy exception vector code to low memory
1648 *
1649 * r3: dest_addr
1650 * r7: source address, r8: end address, r9: target address
1651 */
1652 .globl trap_init
1653 trap_init:
1654 mflr r4 /* save link register */
1655 GET_GOT
1656 lwz r7, GOT(_start_of_vectors)
1657 lwz r8, GOT(_end_of_vectors)
1658
1659 li r9, 0x100 /* reset vector always at 0x100 */
1660
1661 cmplw 0, r7, r8
1662 bgelr /* return if r7>=r8 - just in case */
1663 1:
1664 lwz r0, 0(r7)
1665 stw r0, 0(r9)
1666 addi r7, r7, 4
1667 addi r9, r9, 4
1668 cmplw 0, r7, r8
1669 bne 1b
1670
1671 /*
1672 * relocate `hdlr' and `int_return' entries
1673 */
1674 li r7, .L_MachineCheck - _start + _START_OFFSET
1675 li r8, Alignment - _start + _START_OFFSET
1676 2:
1677 bl trap_reloc
1678 addi r7, r7, 0x100 /* next exception vector */
1679 cmplw 0, r7, r8
1680 blt 2b
1681
1682 li r7, .L_Alignment - _start + _START_OFFSET
1683 bl trap_reloc
1684
1685 li r7, .L_ProgramCheck - _start + _START_OFFSET
1686 bl trap_reloc
1687
1688 #ifdef CONFIG_440
1689 li r7, .L_FPUnavailable - _start + _START_OFFSET
1690 bl trap_reloc
1691
1692 li r7, .L_Decrementer - _start + _START_OFFSET
1693 bl trap_reloc
1694
1695 li r7, .L_APU - _start + _START_OFFSET
1696 bl trap_reloc
1697
1698 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1699 bl trap_reloc
1700
1701 li r7, .L_DataTLBError - _start + _START_OFFSET
1702 bl trap_reloc
1703 #else /* CONFIG_440 */
1704 li r7, .L_PIT - _start + _START_OFFSET
1705 bl trap_reloc
1706
1707 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1708 bl trap_reloc
1709
1710 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1711 bl trap_reloc
1712 #endif /* CONFIG_440 */
1713
1714 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1715 bl trap_reloc
1716
1717 #if !defined(CONFIG_440)
1718 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1719 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1720 mtmsr r7 /* change MSR */
1721 #else
1722 bl __440_msr_set
1723 b __440_msr_continue
1724
1725 __440_msr_set:
1726 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1727 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1728 mtspr SPRN_SRR1,r7
1729 mflr r7
1730 mtspr SPRN_SRR0,r7
1731 rfi
1732 __440_msr_continue:
1733 #endif
1734
1735 mtlr r4 /* restore link register */
1736 blr
1737
1738 #if defined(CONFIG_440)
1739 /*----------------------------------------------------------------------------+
1740 | dcbz_area.
1741 +----------------------------------------------------------------------------*/
1742 function_prolog(dcbz_area)
1743 rlwinm. r5,r4,0,27,31
1744 rlwinm r5,r4,27,5,31
1745 beq ..d_ra2
1746 addi r5,r5,0x0001
1747 ..d_ra2:mtctr r5
1748 ..d_ag2:dcbz r0,r3
1749 addi r3,r3,32
1750 bdnz ..d_ag2
1751 sync
1752 blr
1753 function_epilog(dcbz_area)
1754 #endif /* CONFIG_440 */
1755 #endif /* CONFIG_NAND_SPL */
1756
1757 /*------------------------------------------------------------------------------- */
1758 /* Function: in8 */
1759 /* Description: Input 8 bits */
1760 /*------------------------------------------------------------------------------- */
1761 .globl in8
1762 in8:
1763 lbz r3,0x0000(r3)
1764 blr
1765
1766 /*------------------------------------------------------------------------------- */
1767 /* Function: out8 */
1768 /* Description: Output 8 bits */
1769 /*------------------------------------------------------------------------------- */
1770 .globl out8
1771 out8:
1772 stb r4,0x0000(r3)
1773 blr
1774
1775 /*------------------------------------------------------------------------------- */
1776 /* Function: out32 */
1777 /* Description: Output 32 bits */
1778 /*------------------------------------------------------------------------------- */
1779 .globl out32
1780 out32:
1781 stw r4,0x0000(r3)
1782 blr
1783
1784 /*------------------------------------------------------------------------------- */
1785 /* Function: in32 */
1786 /* Description: Input 32 bits */
1787 /*------------------------------------------------------------------------------- */
1788 .globl in32
1789 in32:
1790 lwz 3,0x0000(3)
1791 blr
1792
1793 /**************************************************************************/
1794 /* PPC405EP specific stuff */
1795 /**************************************************************************/
1796 #ifdef CONFIG_405EP
1797 ppc405ep_init:
1798
1799 #ifdef CONFIG_BUBINGA
1800 /*
1801 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1802 * function) to support FPGA and NVRAM accesses below.
1803 */
1804
1805 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1806 ori r3,r3,GPIO0_OSRH@l
1807 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1808 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1809 stw r4,0(r3)
1810 lis r3,GPIO0_OSRL@h
1811 ori r3,r3,GPIO0_OSRL@l
1812 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1813 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1814 stw r4,0(r3)
1815
1816 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1817 ori r3,r3,GPIO0_ISR1H@l
1818 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1819 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1820 stw r4,0(r3)
1821 lis r3,GPIO0_ISR1L@h
1822 ori r3,r3,GPIO0_ISR1L@l
1823 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1824 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1825 stw r4,0(r3)
1826
1827 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1828 ori r3,r3,GPIO0_TSRH@l
1829 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1830 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1831 stw r4,0(r3)
1832 lis r3,GPIO0_TSRL@h
1833 ori r3,r3,GPIO0_TSRL@l
1834 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1835 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1836 stw r4,0(r3)
1837
1838 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1839 ori r3,r3,GPIO0_TCR@l
1840 lis r4,CONFIG_SYS_GPIO0_TCR@h
1841 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1842 stw r4,0(r3)
1843
1844 li r3,PB1AP /* program EBC bank 1 for RTC access */
1845 mtdcr EBC0_CFGADDR,r3
1846 lis r3,CONFIG_SYS_EBC_PB1AP@h
1847 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1848 mtdcr EBC0_CFGDATA,r3
1849 li r3,PB1CR
1850 mtdcr EBC0_CFGADDR,r3
1851 lis r3,CONFIG_SYS_EBC_PB1CR@h
1852 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1853 mtdcr EBC0_CFGDATA,r3
1854
1855 li r3,PB1AP /* program EBC bank 1 for RTC access */
1856 mtdcr EBC0_CFGADDR,r3
1857 lis r3,CONFIG_SYS_EBC_PB1AP@h
1858 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1859 mtdcr EBC0_CFGDATA,r3
1860 li r3,PB1CR
1861 mtdcr EBC0_CFGADDR,r3
1862 lis r3,CONFIG_SYS_EBC_PB1CR@h
1863 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1864 mtdcr EBC0_CFGDATA,r3
1865
1866 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1867 mtdcr EBC0_CFGADDR,r3
1868 lis r3,CONFIG_SYS_EBC_PB4AP@h
1869 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1870 mtdcr EBC0_CFGDATA,r3
1871 li r3,PB4CR
1872 mtdcr EBC0_CFGADDR,r3
1873 lis r3,CONFIG_SYS_EBC_PB4CR@h
1874 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1875 mtdcr EBC0_CFGDATA,r3
1876 #endif
1877
1878 /*
1879 !-----------------------------------------------------------------------
1880 ! Check to see if chip is in bypass mode.
1881 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1882 ! CPU reset Otherwise, skip this step and keep going.
1883 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1884 ! will not be fast enough for the SDRAM (min 66MHz)
1885 !-----------------------------------------------------------------------
1886 */
1887 mfdcr r5, CPC0_PLLMR1
1888 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1889 cmpi cr0,0,r4,0x1
1890
1891 beq pll_done /* if SSCS =b'1' then PLL has */
1892 /* already been set */
1893 /* and CPU has been reset */
1894 /* so skip to next section */
1895
1896 #ifdef CONFIG_BUBINGA
1897 /*
1898 !-----------------------------------------------------------------------
1899 ! Read NVRAM to get value to write in PLLMR.
1900 ! If value has not been correctly saved, write default value
1901 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1902 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1903 !
1904 ! WARNING: This code assumes the first three words in the nvram_t
1905 ! structure in openbios.h. Changing the beginning of
1906 ! the structure will break this code.
1907 !
1908 !-----------------------------------------------------------------------
1909 */
1910 addis r3,0,NVRAM_BASE@h
1911 addi r3,r3,NVRAM_BASE@l
1912
1913 lwz r4, 0(r3)
1914 addis r5,0,NVRVFY1@h
1915 addi r5,r5,NVRVFY1@l
1916 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1917 bne ..no_pllset
1918 addi r3,r3,4
1919 lwz r4, 0(r3)
1920 addis r5,0,NVRVFY2@h
1921 addi r5,r5,NVRVFY2@l
1922 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1923 bne ..no_pllset
1924 addi r3,r3,8 /* Skip over conf_size */
1925 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1926 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1927 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1928 cmpi cr0,0,r5,1 /* See if PLL is locked */
1929 beq pll_write
1930 ..no_pllset:
1931 #endif /* CONFIG_BUBINGA */
1932
1933 #ifdef CONFIG_TAIHU
1934 mfdcr r4, CPC0_BOOT
1935 andi. r5, r4, CPC0_BOOT_SEP@l
1936 bne strap_1 /* serial eeprom present */
1937 addis r5,0,CPLD_REG0_ADDR@h
1938 ori r5,r5,CPLD_REG0_ADDR@l
1939 andi. r5, r5, 0x10
1940 bne _pci_66mhz
1941 #endif /* CONFIG_TAIHU */
1942
1943 #if defined(CONFIG_ZEUS)
1944 mfdcr r4, CPC0_BOOT
1945 andi. r5, r4, CPC0_BOOT_SEP@l
1946 bne strap_1 /* serial eeprom present */
1947 lis r3,0x0000
1948 addi r3,r3,0x3030
1949 lis r4,0x8042
1950 addi r4,r4,0x223e
1951 b 1f
1952 strap_1:
1953 mfdcr r3, CPC0_PLLMR0
1954 mfdcr r4, CPC0_PLLMR1
1955 b 1f
1956 #endif
1957
1958 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1959 ori r3,r3,PLLMR0_DEFAULT@l /* */
1960 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1961 ori r4,r4,PLLMR1_DEFAULT@l /* */
1962
1963 #ifdef CONFIG_TAIHU
1964 b 1f
1965 _pci_66mhz:
1966 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1967 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1968 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1969 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1970 b 1f
1971 strap_1:
1972 mfdcr r3, CPC0_PLLMR0
1973 mfdcr r4, CPC0_PLLMR1
1974 #endif /* CONFIG_TAIHU */
1975
1976 1:
1977 b pll_write /* Write the CPC0_PLLMR with new value */
1978
1979 pll_done:
1980 /*
1981 !-----------------------------------------------------------------------
1982 ! Clear Soft Reset Register
1983 ! This is needed to enable PCI if not booting from serial EPROM
1984 !-----------------------------------------------------------------------
1985 */
1986 addi r3, 0, 0x0
1987 mtdcr CPC0_SRR, r3
1988
1989 addis r3,0,0x0010
1990 mtctr r3
1991 pci_wait:
1992 bdnz pci_wait
1993
1994 blr /* return to main code */
1995
1996 /*
1997 !-----------------------------------------------------------------------------
1998 ! Function: pll_write
1999 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
2000 ! That is:
2001 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
2002 ! 2. PLL is reset
2003 ! 3. Clock dividers are set while PLL is held in reset and bypassed
2004 ! 4. PLL Reset is cleared
2005 ! 5. Wait 100us for PLL to lock
2006 ! 6. A core reset is performed
2007 ! Input: r3 = Value to write to CPC0_PLLMR0
2008 ! Input: r4 = Value to write to CPC0_PLLMR1
2009 ! Output r3 = none
2010 !-----------------------------------------------------------------------------
2011 */
2012 .globl pll_write
2013 pll_write:
2014 mfdcr r5, CPC0_UCR
2015 andis. r5,r5,0xFFFF
2016 ori r5,r5,0x0101 /* Stop the UART clocks */
2017 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2018
2019 mfdcr r5, CPC0_PLLMR1
2020 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2021 mtdcr CPC0_PLLMR1,r5
2022 oris r5,r5,0x4000 /* Set PLL Reset */
2023 mtdcr CPC0_PLLMR1,r5
2024
2025 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2026 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2027 oris r5,r5,0x4000 /* Set PLL Reset */
2028 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2029 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2030 mtdcr CPC0_PLLMR1,r5
2031
2032 /*
2033 ! Wait min of 100us for PLL to lock.
2034 ! See CMOS 27E databook for more info.
2035 ! At 200MHz, that means waiting 20,000 instructions
2036 */
2037 addi r3,0,20000 /* 2000 = 0x4e20 */
2038 mtctr r3
2039 pll_wait:
2040 bdnz pll_wait
2041
2042 oris r5,r5,0x8000 /* Enable PLL */
2043 mtdcr CPC0_PLLMR1,r5 /* Engage */
2044
2045 /*
2046 * Reset CPU to guarantee timings are OK
2047 * Not sure if this is needed...
2048 */
2049 addis r3,0,0x1000
2050 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
2051 /* execution will continue from the poweron */
2052 /* vector of 0xfffffffc */
2053 #endif /* CONFIG_405EP */
2054
2055 #if defined(CONFIG_440)
2056 /*----------------------------------------------------------------------------+
2057 | mttlb3.
2058 +----------------------------------------------------------------------------*/
2059 function_prolog(mttlb3)
2060 TLBWE(4,3,2)
2061 blr
2062 function_epilog(mttlb3)
2063
2064 /*----------------------------------------------------------------------------+
2065 | mftlb3.
2066 +----------------------------------------------------------------------------*/
2067 function_prolog(mftlb3)
2068 TLBRE(3,3,2)
2069 blr
2070 function_epilog(mftlb3)
2071
2072 /*----------------------------------------------------------------------------+
2073 | mttlb2.
2074 +----------------------------------------------------------------------------*/
2075 function_prolog(mttlb2)
2076 TLBWE(4,3,1)
2077 blr
2078 function_epilog(mttlb2)
2079
2080 /*----------------------------------------------------------------------------+
2081 | mftlb2.
2082 +----------------------------------------------------------------------------*/
2083 function_prolog(mftlb2)
2084 TLBRE(3,3,1)
2085 blr
2086 function_epilog(mftlb2)
2087
2088 /*----------------------------------------------------------------------------+
2089 | mttlb1.
2090 +----------------------------------------------------------------------------*/
2091 function_prolog(mttlb1)
2092 TLBWE(4,3,0)
2093 blr
2094 function_epilog(mttlb1)
2095
2096 /*----------------------------------------------------------------------------+
2097 | mftlb1.
2098 +----------------------------------------------------------------------------*/
2099 function_prolog(mftlb1)
2100 TLBRE(3,3,0)
2101 blr
2102 function_epilog(mftlb1)
2103 #endif /* CONFIG_440 */
2104
2105 #if defined(CONFIG_NAND_SPL)
2106 /*
2107 * void nand_boot_relocate(dst, src, bytes)
2108 *
2109 * r3 = Destination address to copy code to (in SDRAM)
2110 * r4 = Source address to copy code from
2111 * r5 = size to copy in bytes
2112 */
2113 nand_boot_relocate:
2114 mr r6,r3
2115 mr r7,r4
2116 mflr r8
2117
2118 /*
2119 * Copy SPL from icache into SDRAM
2120 */
2121 subi r3,r3,4
2122 subi r4,r4,4
2123 srwi r5,r5,2
2124 mtctr r5
2125 ..spl_loop:
2126 lwzu r0,4(r4)
2127 stwu r0,4(r3)
2128 bdnz ..spl_loop
2129
2130 /*
2131 * Calculate "corrected" link register, so that we "continue"
2132 * in execution in destination range
2133 */
2134 sub r3,r7,r6 /* r3 = src - dst */
2135 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2136 mtlr r8
2137 blr
2138
2139 nand_boot_common:
2140 /*
2141 * First initialize SDRAM. It has to be available *before* calling
2142 * nand_boot().
2143 */
2144 lis r3,CONFIG_SYS_SDRAM_BASE@h
2145 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2146 bl initdram
2147
2148 /*
2149 * Now copy the 4k SPL code into SDRAM and continue execution
2150 * from there.
2151 */
2152 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2153 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2154 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2155 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2156 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2157 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2158 bl nand_boot_relocate
2159
2160 /*
2161 * We're running from SDRAM now!!!
2162 *
2163 * It is necessary for 4xx systems to relocate from running at
2164 * the original location (0xfffffxxx) to somewhere else (SDRAM
2165 * preferably). This is because CS0 needs to be reconfigured for
2166 * NAND access. And we can't reconfigure this CS when currently
2167 * "running" from it.
2168 */
2169
2170 /*
2171 * Finally call nand_boot() to load main NAND U-Boot image from
2172 * NAND and jump to it.
2173 */
2174 bl nand_boot /* will not return */
2175 #endif /* CONFIG_NAND_SPL */
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