arch/powerpc/cpu/ppc4xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *  Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
   6  *  Copyright (c) 2008 Nuovation System Designs, LLC
   7  *    Grant Erickson <gerickson@nuovations.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0 ibm-pibs
  10  */
  11
  12 /*
  13  * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
  14  *
  15  * The following description only applies to the NOR flash style booting.
  16  * NAND booting is different. For more details about NAND booting on 4xx
  17  * take a look at doc/README.nand-boot-ppc440.
  18  *
  19  * The CPU starts at address 0xfffffffc (last word in the address space).
  20  * The U-Boot image therefore has to be located in the "upper" area of the
  21  * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
  22  * the boot chip-select (CS0) is quite big and covers this area. On the
  23  * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
  24  * reconfigure this CS0 (and other chip-selects as well when configured
  25  * this way) in the boot process to the "correct" values matching the
  26  * board layout.
  27  */
  28
  29 #include <asm-offsets.h>
  30 #include <config.h>
  31 #include <asm/ppc4xx.h>
  32 #include <version.h>
  33
  34 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  35
  36 #include <ppc_asm.tmpl>
  37 #include <ppc_defs.h>
  38
  39 #include <asm/cache.h>
  40 #include <asm/mmu.h>
  41 #include <asm/ppc4xx-isram.h>
  42
  43 #ifdef CONFIG_SYS_INIT_DCACHE_CS
  44 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
  45 #  define PBxAP PB1AP
  46 #  define PBxCR PB0CR
  47 #  if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
  48 #   define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
  49 #   define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
  50 #  endif
  51 # endif
  52 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
  53 #  define PBxAP PB1AP
  54 #  define PBxCR PB1CR
  55 #  if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
  56 #   define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
  57 #   define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
  58 #  endif
  59 # endif
  60 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
  61 #  define PBxAP PB2AP
  62 #  define PBxCR PB2CR
  63 #  if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
  64 #   define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
  65 #   define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
  66 #  endif
  67 # endif
  68 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
  69 #  define PBxAP PB3AP
  70 #  define PBxCR PB3CR
  71 #  if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
  72 #   define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
  73 #   define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
  74 #  endif
  75 # endif
  76 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
  77 #  define PBxAP PB4AP
  78 #  define PBxCR PB4CR
  79 #  if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
  80 #   define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
  81 #   define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
  82 #  endif
  83 # endif
  84 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
  85 #  define PBxAP PB5AP
  86 #  define PBxCR PB5CR
  87 #  if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
  88 #   define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
  89 #   define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
  90 #  endif
  91 # endif
  92 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
  93 #  define PBxAP PB6AP
  94 #  define PBxCR PB6CR
  95 #  if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
  96 #   define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
  97 #   define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
  98 #  endif
  99 # endif
 100 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
 101 #  define PBxAP PB7AP
 102 #  define PBxCR PB7CR
 103 #  if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
 104 #   define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
 105 #   define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
 106 #  endif
 107 # endif
 108 # ifndef PBxAP_VAL
 109 #  define PBxAP_VAL     0
 110 # endif
 111 # ifndef PBxCR_VAL
 112 #  define PBxCR_VAL     0
 113 # endif
 114 /*
 115  * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
 116  * used as temporary stack pointer for the primordial stack
 117  */
 118 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
 119 #  define CONFIG_SYS_INIT_DCACHE_PBxAR  (EBC_BXAP_BME_DISABLED                  | \
 120                                  EBC_BXAP_TWT_ENCODE(7)                 | \
 121                                  EBC_BXAP_BCE_DISABLE                   | \
 122                                  EBC_BXAP_BCT_2TRANS                    | \
 123                                  EBC_BXAP_CSN_ENCODE(0)                 | \
 124                                  EBC_BXAP_OEN_ENCODE(0)                 | \
 125                                  EBC_BXAP_WBN_ENCODE(0)                 | \
 126                                  EBC_BXAP_WBF_ENCODE(0)                 | \
 127                                  EBC_BXAP_TH_ENCODE(2)                  | \
 128                                  EBC_BXAP_RE_DISABLED                   | \
 129                                  EBC_BXAP_SOR_NONDELAYED                | \
 130                                  EBC_BXAP_BEM_WRITEONLY                 | \
 131                                  EBC_BXAP_PEN_DISABLED)
 132 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
 133 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
 134 #  define CONFIG_SYS_INIT_DCACHE_PBxCR  (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR)  | \
 135                                  EBC_BXCR_BS_64MB                       | \
 136                                  EBC_BXCR_BU_RW                         | \
 137                                  EBC_BXCR_BW_16BIT)
 138 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
 139 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
 140 #  define CONFIG_SYS_INIT_RAM_PATTERN   0xDEADDEAD
 141 # endif
 142 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
 143
 144 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
 145 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
 146 #endif
 147
 148 /*
 149  * Unless otherwise overriden, enable two 128MB cachable instruction regions
 150  * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
 151  * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
 152  */
 153 #if !defined(CONFIG_SYS_FLASH_BASE)
 154 /* If not already defined, set it to the "last" 128MByte region */
 155 # define CONFIG_SYS_FLASH_BASE          0xf8000000
 156 #endif
 157 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
 158 # define CONFIG_SYS_ICACHE_SACR_VALUE           \
 159                 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (  0 << 20)) | \
 160                  PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
 161                  PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
 162 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
 163
 164 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
 165 # define CONFIG_SYS_DCACHE_SACR_VALUE           \
 166                 (0x00000000)
 167 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
 168
 169 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
 170 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0       /* use TLB 0 as default */
 171 #endif
 172
 173 #define function_prolog(func_name)      .text; \
 174                                         .align 2; \
 175                                         .globl func_name; \
 176                                         func_name:
 177 #define function_epilog(func_name)      .type func_name,@function; \
 178                                         .size func_name,.-func_name
 179
 180 /* We don't want the  MMU yet.
 181 */
 182 #undef  MSR_KERNEL
 183 #define MSR_KERNEL ( MSR_ME  )  /* Machine Check */
 184
 185
 186         .extern ext_bus_cntlr_init
 187 #ifdef CONFIG_NAND_U_BOOT
 188         .extern reconfig_tlb0
 189 #endif
 190
 191 /*
 192  * Set up GOT: Global Offset Table
 193  *
 194  * Use r12 to access the GOT
 195  */
 196 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 197         START_GOT
 198         GOT_ENTRY(_GOT2_TABLE_)
 199         GOT_ENTRY(_FIXUP_TABLE_)
 200
 201         GOT_ENTRY(_start)
 202         GOT_ENTRY(_start_of_vectors)
 203         GOT_ENTRY(_end_of_vectors)
 204         GOT_ENTRY(transfer_to_handler)
 205
 206         GOT_ENTRY(__init_end)
 207         GOT_ENTRY(__bss_end)
 208         GOT_ENTRY(__bss_start)
 209         END_GOT
 210 #endif /* CONFIG_NAND_SPL */
 211
 212 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
 213         !defined(CONFIG_SPL_BUILD)
 214         /*
 215          * NAND U-Boot image is started from offset 0
 216          */
 217         .text
 218 #if defined(CONFIG_440)
 219         bl      reconfig_tlb0
 220 #endif
 221         GET_GOT
 222         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 223         bl      board_init_f
 224         /* NOTREACHED - board_init_f() does not return */
 225 #endif
 226
 227 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
 228         /*
 229          * 4xx RAM-booting U-Boot image is started from offset 0
 230          */
 231         .text
 232         bl      _start_440
 233 #endif
 234
 235 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 236         /*
 237          * This is the entry of the real U-Boot from a board port
 238          * that supports SPL booting on the PPC4xx. We only need
 239          * to call board_init_f() here. Everything else has already
 240          * been done in the SPL u-boot version.
 241          */
 242         GET_GOT                 /* initialize GOT access                */
 243         bl      board_init_f    /* run 1st part of board init code (in Flash)*/
 244         /* NOTREACHED - board_init_f() does not return */
 245 #endif
 246
 247 /*
 248  * 440 Startup -- on reset only the top 4k of the effective
 249  * address space is mapped in by an entry in the instruction
 250  * and data shadow TLB. The .bootpg section is located in the
 251  * top 4k & does only what's necessary to map in the the rest
 252  * of the boot rom. Once the boot rom is mapped in we can
 253  * proceed with normal startup.
 254  *
 255  * NOTE: CS0 only covers the top 2MB of the effective address
 256  * space after reset.
 257  */
 258
 259 #if defined(CONFIG_440)
 260 #if !defined(CONFIG_NAND_SPL)
 261     .section .bootpg,"ax"
 262 #endif
 263     .globl _start_440
 264
 265 /**************************************************************************/
 266 _start_440:
 267         /*--------------------------------------------------------------------+
 268         | 440EPX BUP Change - Hardware team request
 269         +--------------------------------------------------------------------*/
 270 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 271         sync
 272         nop
 273         nop
 274 #endif
 275         /*----------------------------------------------------------------+
 276         | Core bug fix.  Clear the esr
 277         +-----------------------------------------------------------------*/
 278         li      r0,0
 279         mtspr   SPRN_ESR,r0
 280         /*----------------------------------------------------------------*/
 281         /* Clear and set up some registers. */
 282         /*----------------------------------------------------------------*/
 283         iccci   r0,r0           /* NOTE: operands not used for 440 */
 284         dccci   r0,r0           /* NOTE: operands not used for 440 */
 285         sync
 286         li      r0,0
 287         mtspr   SPRN_SRR0,r0
 288         mtspr   SPRN_SRR1,r0
 289         mtspr   SPRN_CSRR0,r0
 290         mtspr   SPRN_CSRR1,r0
 291         /* NOTE: 440GX adds machine check status regs */
 292 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
 293         mtspr   SPRN_MCSRR0,r0
 294         mtspr   SPRN_MCSRR1,r0
 295         mfspr   r1,SPRN_MCSR
 296         mtspr   SPRN_MCSR,r1
 297 #endif
 298
 299         /*----------------------------------------------------------------*/
 300         /* CCR0 init */
 301         /*----------------------------------------------------------------*/
 302         /* Disable store gathering & broadcast, guarantee inst/data
 303         * cache block touch, force load/store alignment
 304         * (see errata 1.12: 440_33)
 305         */
 306         lis     r1,0x0030       /* store gathering & broadcast disable */
 307         ori     r1,r1,0x6000    /* cache touch */
 308         mtspr   SPRN_CCR0,r1
 309
 310         /*----------------------------------------------------------------*/
 311         /* Initialize debug */
 312         /*----------------------------------------------------------------*/
 313         mfspr   r1,SPRN_DBCR0
 314         andis.  r1, r1, 0x8000  /* test DBCR0[EDM] bit                  */
 315         bne     skip_debug_init /* if set, don't clear debug register   */
 316         mfspr   r1,SPRN_CCR0
 317         ori     r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
 318         mtspr   SPRN_CCR0,r1
 319         mtspr   SPRN_DBCR0,r0
 320         mtspr   SPRN_DBCR1,r0
 321         mtspr   SPRN_DBCR2,r0
 322         mtspr   SPRN_IAC1,r0
 323         mtspr   SPRN_IAC2,r0
 324         mtspr   SPRN_IAC3,r0
 325         mtspr   SPRN_DAC1,r0
 326         mtspr   SPRN_DAC2,r0
 327         mtspr   SPRN_DVC1,r0
 328         mtspr   SPRN_DVC2,r0
 329
 330         mfspr   r1,SPRN_DBSR
 331         mtspr   SPRN_DBSR,r1    /* Clear all valid bits */
 332 skip_debug_init:
 333
 334 #if defined (CONFIG_440SPE)
 335         /*----------------------------------------------------------------+
 336         | Initialize Core Configuration Reg1.
 337         | a. ICDPEI: Record even parity. Normal operation.
 338         | b. ICTPEI: Record even parity. Normal operation.
 339         | c. DCTPEI: Record even parity. Normal operation.
 340         | d. DCDPEI: Record even parity. Normal operation.
 341         | e. DCUPEI: Record even parity. Normal operation.
 342         | f. DCMPEI: Record even parity. Normal operation.
 343         | g. FCOM:   Normal operation
 344         | h. MMUPEI: Record even parity. Normal operation.
 345         | i. FFF:    Flush only as much data as necessary.
 346         | j. TCS:    Timebase increments from CPU clock.
 347         +-----------------------------------------------------------------*/
 348         li      r0,0
 349         mtspr   SPRN_CCR1, r0
 350
 351         /*----------------------------------------------------------------+
 352         | Reset the timebase.
 353         | The previous write to CCR1 sets the timebase source.
 354         +-----------------------------------------------------------------*/
 355         mtspr   SPRN_TBWL, r0
 356         mtspr   SPRN_TBWU, r0
 357 #endif
 358
 359         /*----------------------------------------------------------------*/
 360         /* Setup interrupt vectors */
 361         /*----------------------------------------------------------------*/
 362         mtspr   SPRN_IVPR,r0            /* Vectors start at 0x0000_0000 */
 363         li      r1,0x0100
 364         mtspr   SPRN_IVOR0,r1   /* Critical input */
 365         li      r1,0x0200
 366         mtspr   SPRN_IVOR1,r1   /* Machine check */
 367         li      r1,0x0300
 368         mtspr   SPRN_IVOR2,r1   /* Data storage */
 369         li      r1,0x0400
 370         mtspr   SPRN_IVOR3,r1   /* Instruction storage */
 371         li      r1,0x0500
 372         mtspr   SPRN_IVOR4,r1   /* External interrupt */
 373         li      r1,0x0600
 374         mtspr   SPRN_IVOR5,r1   /* Alignment */
 375         li      r1,0x0700
 376         mtspr   SPRN_IVOR6,r1   /* Program check */
 377         li      r1,0x0800
 378         mtspr   SPRN_IVOR7,r1   /* Floating point unavailable */
 379         li      r1,0x0c00
 380         mtspr   SPRN_IVOR8,r1   /* System call */
 381         li      r1,0x0a00
 382         mtspr   SPRN_IVOR9,r1   /* Auxiliary Processor unavailable */
 383         li      r1,0x0900
 384         mtspr   SPRN_IVOR10,r1  /* Decrementer */
 385         li      r1,0x1300
 386         mtspr   SPRN_IVOR13,r1  /* Data TLB error */
 387         li      r1,0x1400
 388         mtspr   SPRN_IVOR14,r1  /* Instr TLB error */
 389         li      r1,0x2000
 390         mtspr   SPRN_IVOR15,r1  /* Debug */
 391
 392         /*----------------------------------------------------------------*/
 393         /* Configure cache regions  */
 394         /*----------------------------------------------------------------*/
 395         mtspr   SPRN_INV0,r0
 396         mtspr   SPRN_INV1,r0
 397         mtspr   SPRN_INV2,r0
 398         mtspr   SPRN_INV3,r0
 399         mtspr   SPRN_DNV0,r0
 400         mtspr   SPRN_DNV1,r0
 401         mtspr   SPRN_DNV2,r0
 402         mtspr   SPRN_DNV3,r0
 403         mtspr   SPRN_ITV0,r0
 404         mtspr   SPRN_ITV1,r0
 405         mtspr   SPRN_ITV2,r0
 406         mtspr   SPRN_ITV3,r0
 407         mtspr   SPRN_DTV0,r0
 408         mtspr   SPRN_DTV1,r0
 409         mtspr   SPRN_DTV2,r0
 410         mtspr   SPRN_DTV3,r0
 411
 412         /*----------------------------------------------------------------*/
 413         /* Cache victim limits */
 414         /*----------------------------------------------------------------*/
 415         /* floors 0, ceiling max to use the entire cache -- nothing locked
 416         */
 417         lis     r1,0x0001
 418         ori     r1,r1,0xf800
 419         mtspr   SPRN_IVLIM,r1
 420         mtspr   SPRN_DVLIM,r1
 421
 422         /*----------------------------------------------------------------+
 423         |Initialize MMUCR[STID] = 0.
 424         +-----------------------------------------------------------------*/
 425         mfspr   r0,SPRN_MMUCR
 426         addis   r1,0,0xFFFF
 427         ori     r1,r1,0xFF00
 428         and     r0,r0,r1
 429         mtspr   SPRN_MMUCR,r0
 430
 431         /*----------------------------------------------------------------*/
 432         /* Clear all TLB entries -- TID = 0, TS = 0 */
 433         /*----------------------------------------------------------------*/
 434         addis   r0,0,0x0000
 435 #ifdef CONFIG_SYS_RAMBOOT
 436         li      r4,0            /* Start with TLB #0 */
 437 #else
 438         li      r4,1            /* Start with TLB #1 */
 439 #endif
 440         li      r1,64           /* 64 TLB entries */
 441         sub     r1,r1,r4        /* calculate last TLB # */
 442         mtctr   r1
 443 rsttlb:
 444 #ifdef CONFIG_SYS_RAMBOOT
 445         tlbre   r3,r4,0         /* Read contents from TLB word #0 to get EPN */
 446         rlwinm. r3,r3,0,0xfffffc00      /* Mask EPN */
 447         beq     tlbnxt          /* Skip EPN=0 TLB, this is the SDRAM TLB */
 448 #endif
 449         tlbwe   r0,r4,0         /* Invalidate all entries (V=0)*/
 450         tlbwe   r0,r4,1
 451         tlbwe   r0,r4,2
 452 tlbnxt: addi    r4,r4,1         /* Next TLB */
 453         bdnz    rsttlb
 454
 455         /*----------------------------------------------------------------*/
 456         /* TLB entry setup -- step thru tlbtab */
 457         /*----------------------------------------------------------------*/
 458 #if defined(CONFIG_440SPE_REVA)
 459         /*----------------------------------------------------------------*/
 460         /* We have different TLB tables for revA and rev B of 440SPe */
 461         /*----------------------------------------------------------------*/
 462         mfspr   r1, PVR
 463         lis     r0,0x5342
 464         ori     r0,r0,0x1891
 465         cmpw    r7,r1,r0
 466         bne     r7,..revA
 467         bl      tlbtabB
 468         b       ..goon
 469 ..revA:
 470         bl      tlbtabA
 471 ..goon:
 472 #else
 473         bl      tlbtab          /* Get tlbtab pointer */
 474 #endif
 475         mr      r5,r0
 476         li      r1,0x003f       /* 64 TLB entries max */
 477         mtctr   r1
 478         li      r4,0            /* TLB # */
 479
 480         addi    r5,r5,-4
 481 1:
 482 #ifdef CONFIG_SYS_RAMBOOT
 483         tlbre   r3,r4,0         /* Read contents from TLB word #0 */
 484         rlwinm. r3,r3,0,0x00000200      /* Mask V (valid) bit */
 485         bne     tlbnx2          /* Skip V=1 TLB, this is the SDRAM TLB */
 486 #endif
 487         lwzu    r0,4(r5)
 488         cmpwi   r0,0
 489         beq     2f              /* 0 marks end */
 490         lwzu    r1,4(r5)
 491         lwzu    r2,4(r5)
 492         tlbwe   r0,r4,0         /* TLB Word 0 */
 493         tlbwe   r1,r4,1         /* TLB Word 1 */
 494         tlbwe   r2,r4,2         /* TLB Word 2 */
 495 tlbnx2: addi    r4,r4,1         /* Next TLB */
 496         bdnz    1b
 497
 498         /*----------------------------------------------------------------*/
 499         /* Continue from 'normal' start */
 500         /*----------------------------------------------------------------*/
 501 2:
 502         bl      3f
 503         b       _start
 504
 505 3:      li      r0,0
 506         mtspr   SPRN_SRR1,r0            /* Keep things disabled for now */
 507         mflr    r1
 508         mtspr   SPRN_SRR0,r1
 509         rfi
 510 #endif /* CONFIG_440 */
 511
 512 /*
 513  * r3 - 1st arg to board_init(): IMMP pointer
 514  * r4 - 2nd arg to board_init(): boot flag
 515  */
 516 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 517         .text
 518         .long   0x27051956              /* U-Boot Magic Number                  */
 519         .globl  version_string
 520 version_string:
 521         .ascii U_BOOT_VERSION_STRING, "\0"
 522
 523         . = EXC_OFF_SYS_RESET
 524         .globl  _start_of_vectors
 525 _start_of_vectors:
 526
 527 /* Critical input. */
 528         CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
 529
 530 #ifdef CONFIG_440
 531 /* Machine check */
 532         MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 533 #else
 534         CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 535 #endif /* CONFIG_440 */
 536
 537 /* Data Storage exception. */
 538         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 539
 540 /* Instruction Storage exception. */
 541         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 542
 543 /* External Interrupt exception. */
 544         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 545
 546 /* Alignment exception. */
 547         . = 0x600
 548 Alignment:
 549         EXCEPTION_PROLOG(SRR0, SRR1)
 550         mfspr   r4,DAR
 551         stw     r4,_DAR(r21)
 552         mfspr   r5,DSISR
 553         stw     r5,_DSISR(r21)
 554         addi    r3,r1,STACK_FRAME_OVERHEAD
 555         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 556
 557 /* Program check exception */
 558         . = 0x700
 559 ProgramCheck:
 560         EXCEPTION_PROLOG(SRR0, SRR1)
 561         addi    r3,r1,STACK_FRAME_OVERHEAD
 562         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 563                 MSR_KERNEL, COPY_EE)
 564
 565 #ifdef CONFIG_440
 566         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 567         STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
 568         STD_EXCEPTION(0xa00, APU, UnknownException)
 569 #endif
 570         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 571
 572 #ifdef CONFIG_440
 573         STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
 574         STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
 575 #else
 576         STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
 577         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 578         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 579 #endif
 580         CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
 581
 582         .globl  _end_of_vectors
 583 _end_of_vectors:
 584         . = _START_OFFSET
 585 #endif
 586         .globl  _start
 587 _start:
 588
 589 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 590         /*
 591          * This is the entry of the real U-Boot from a board port
 592          * that supports SPL booting on the PPC4xx. We only need
 593          * to call board_init_f() here. Everything else has already
 594          * been done in the SPL u-boot version.
 595          */
 596         GET_GOT                 /* initialize GOT access                */
 597         bl      board_init_f    /* run 1st part of board init code (in Flash)*/
 598         /* NOTREACHED - board_init_f() does not return */
 599 #endif
 600
 601 /*****************************************************************************/
 602 #if defined(CONFIG_440)
 603
 604         /*----------------------------------------------------------------*/
 605         /* Clear and set up some registers. */
 606         /*----------------------------------------------------------------*/
 607         li      r0,0x0000
 608         lis     r1,0xffff
 609         mtspr   SPRN_DEC,r0                     /* prevent dec exceptions */
 610         mtspr   SPRN_TBWL,r0                    /* prevent fit & wdt exceptions */
 611         mtspr   SPRN_TBWU,r0
 612         mtspr   SPRN_TSR,r1                     /* clear all timer exception status */
 613         mtspr   SPRN_TCR,r0                     /* disable all */
 614         mtspr   SPRN_ESR,r0                     /* clear exception syndrome register */
 615         mtxer   r0                      /* clear integer exception register */
 616
 617         /*----------------------------------------------------------------*/
 618         /* Debug setup -- some (not very good) ice's need an event*/
 619         /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
 620         /* value you need in this case 0x8cff 0000 should do the trick */
 621         /*----------------------------------------------------------------*/
 622 #if defined(CONFIG_SYS_INIT_DBCR)
 623         lis     r1,0xffff
 624         ori     r1,r1,0xffff
 625         mtspr   SPRN_DBSR,r1                    /* Clear all status bits */
 626         lis     r0,CONFIG_SYS_INIT_DBCR@h
 627         ori     r0,r0,CONFIG_SYS_INIT_DBCR@l
 628         mtspr   SPRN_DBCR0,r0
 629         isync
 630 #endif
 631
 632         /*----------------------------------------------------------------*/
 633         /* Setup the internal SRAM */
 634         /*----------------------------------------------------------------*/
 635         li      r0,0
 636
 637 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
 638         /* Clear Dcache to use as RAM */
 639         addis   r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
 640         ori     r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
 641         addis   r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
 642         ori     r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
 643         rlwinm. r5,r4,0,27,31
 644         rlwinm  r5,r4,27,5,31
 645         beq     ..d_ran
 646         addi    r5,r5,0x0001
 647 ..d_ran:
 648         mtctr   r5
 649 ..d_ag:
 650         dcbz    r0,r3
 651         addi    r3,r3,32
 652         bdnz    ..d_ag
 653
 654         /*
 655          * Lock the init-ram/stack in d-cache, so that other regions
 656          * may use d-cache as well
 657          * Note, that this current implementation locks exactly 4k
 658          * of d-cache, so please make sure that you don't define a
 659          * bigger init-ram area. Take a look at the lwmon5 440EPx
 660          * implementation as a reference.
 661          */
 662         msync
 663         isync
 664         /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
 665         lis     r1,0x0201
 666         ori     r1,r1,0xf808
 667         mtspr   SPRN_DVLIM,r1
 668         lis     r1,0x0808
 669         ori     r1,r1,0x0808
 670         mtspr   SPRN_DNV0,r1
 671         mtspr   SPRN_DNV1,r1
 672         mtspr   SPRN_DNV2,r1
 673         mtspr   SPRN_DNV3,r1
 674         mtspr   SPRN_DTV0,r1
 675         mtspr   SPRN_DTV1,r1
 676         mtspr   SPRN_DTV2,r1
 677         mtspr   SPRN_DTV3,r1
 678         msync
 679         isync
 680 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 681
 682         /* 440EP & 440GR are only 440er PPC's without internal SRAM */
 683 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
 684         /* not all PPC's have internal SRAM usable as L2-cache */
 685 #if defined(CONFIG_440GX) || \
 686     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 687     defined(CONFIG_460SX)
 688         mtdcr   L2_CACHE_CFG,r0         /* Ensure L2 Cache is off */
 689 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 690       defined(CONFIG_APM821XX)
 691         lis     r1, 0x0000
 692         ori     r1,r1,0x0008            /* Set L2_CACHE_CFG[RDBW]=1 */
 693         mtdcr   L2_CACHE_CFG,r1
 694 #endif
 695
 696         lis     r2,0x7fff
 697         ori     r2,r2,0xffff
 698         mfdcr   r1,ISRAM0_DPC
 699         and     r1,r1,r2                /* Disable parity check */
 700         mtdcr   ISRAM0_DPC,r1
 701         mfdcr   r1,ISRAM0_PMEG
 702         and     r1,r1,r2                /* Disable pwr mgmt */
 703         mtdcr   ISRAM0_PMEG,r1
 704
 705         lis     r1,0x8000               /* BAS = 8000_0000 */
 706 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 707         ori     r1,r1,0x0980            /* first 64k */
 708         mtdcr   ISRAM0_SB0CR,r1
 709         lis     r1,0x8001
 710         ori     r1,r1,0x0980            /* second 64k */
 711         mtdcr   ISRAM0_SB1CR,r1
 712         lis     r1, 0x8002
 713         ori     r1,r1, 0x0980           /* third 64k */
 714         mtdcr   ISRAM0_SB2CR,r1
 715         lis     r1, 0x8003
 716         ori     r1,r1, 0x0980           /* fourth 64k */
 717         mtdcr   ISRAM0_SB3CR,r1
 718 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
 719       defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
 720         lis     r1,0x0000               /* BAS = X_0000_0000 */
 721         ori     r1,r1,0x0984            /* first 64k */
 722         mtdcr   ISRAM0_SB0CR,r1
 723         lis     r1,0x0001
 724         ori     r1,r1,0x0984            /* second 64k */
 725         mtdcr   ISRAM0_SB1CR,r1
 726         lis     r1, 0x0002
 727         ori     r1,r1, 0x0984           /* third 64k */
 728         mtdcr   ISRAM0_SB2CR,r1
 729         lis     r1, 0x0003
 730         ori     r1,r1, 0x0984           /* fourth 64k */
 731         mtdcr   ISRAM0_SB3CR,r1
 732 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 733     defined(CONFIG_APM821XX)
 734         lis     r2,0x7fff
 735         ori     r2,r2,0xffff
 736         mfdcr   r1,ISRAM1_DPC
 737         and     r1,r1,r2                /* Disable parity check */
 738         mtdcr   ISRAM1_DPC,r1
 739         mfdcr   r1,ISRAM1_PMEG
 740         and     r1,r1,r2                /* Disable pwr mgmt */
 741         mtdcr   ISRAM1_PMEG,r1
 742
 743         lis     r1,0x0004               /* BAS = 4_0004_0000 */
 744         ori     r1,r1,ISRAM1_SIZE       /* ocm size */
 745         mtdcr   ISRAM1_SB0CR,r1
 746 #endif
 747 #elif defined(CONFIG_460SX)
 748         lis     r1,0x0000               /* BAS = 0000_0000 */
 749         ori     r1,r1,0x0B84            /* first 128k */
 750         mtdcr   ISRAM0_SB0CR,r1
 751         lis     r1,0x0001
 752         ori     r1,r1,0x0B84            /* second 128k */
 753         mtdcr   ISRAM0_SB1CR,r1
 754         lis     r1, 0x0002
 755         ori     r1,r1, 0x0B84           /* third 128k */
 756         mtdcr   ISRAM0_SB2CR,r1
 757         lis     r1, 0x0003
 758         ori     r1,r1, 0x0B84           /* fourth 128k */
 759         mtdcr   ISRAM0_SB3CR,r1
 760 #elif defined(CONFIG_440GP)
 761         ori     r1,r1,0x0380            /* 8k rw */
 762         mtdcr   ISRAM0_SB0CR,r1
 763         mtdcr   ISRAM0_SB1CR,r0         /* Disable bank 1 */
 764 #endif
 765 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 766
 767         /*----------------------------------------------------------------*/
 768         /* Setup the stack in internal SRAM */
 769         /*----------------------------------------------------------------*/
 770         lis     r1,CONFIG_SYS_INIT_RAM_ADDR@h
 771         ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
 772         li      r0,0
 773         stwu    r0,-4(r1)
 774         stwu    r0,-4(r1)               /* Terminate call chain */
 775
 776         stwu    r1,-8(r1)               /* Save back chain and move SP */
 777         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 778         ori     r0,r0, RESET_VECTOR@l
 779         stwu    r1,-8(r1)               /* Save back chain and move SP */
 780         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 781
 782 #ifdef CONFIG_NAND_SPL
 783         bl      nand_boot_common        /* will not return */
 784 #else
 785 #ifndef CONFIG_SPL_BUILD
 786         GET_GOT
 787 #endif
 788
 789         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 790         bl      board_init_f
 791         /* NOTREACHED - board_init_f() does not return */
 792 #endif
 793
 794 #endif /* CONFIG_440 */
 795
 796 /*****************************************************************************/
 797 #if defined(CONFIG_405GP) || \
 798     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 799     defined(CONFIG_405EX) || defined(CONFIG_405)
 800         /*----------------------------------------------------------------------- */
 801         /* Clear and set up some registers. */
 802         /*----------------------------------------------------------------------- */
 803         addi    r4,r0,0x0000
 804 #if !defined(CONFIG_405EX)
 805         mtspr   SPRN_SGR,r4
 806 #else
 807         /*
 808          * On 405EX, completely clearing the SGR leads to PPC hangup
 809          * upon PCIe configuration access. The PCIe memory regions
 810          * need to be guarded!
 811          */
 812         lis     r3,0x0000
 813         ori     r3,r3,0x7FFC
 814         mtspr   SPRN_SGR,r3
 815 #endif
 816         mtspr   SPRN_DCWR,r4
 817         mtesr   r4                      /* clear Exception Syndrome Reg */
 818         mttcr   r4                      /* clear Timer Control Reg */
 819         mtxer   r4                      /* clear Fixed-Point Exception Reg */
 820         mtevpr  r4                      /* clear Exception Vector Prefix Reg */
 821         addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF (status in the */
 822                                         /* dbsr is cleared by setting bits to 1) */
 823         mtdbsr  r4                      /* clear/reset the dbsr */
 824
 825         /* Invalidate the i- and d-caches. */
 826         bl      invalidate_icache
 827         bl      invalidate_dcache
 828
 829         /* Set-up icache cacheability. */
 830         lis     r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
 831         ori     r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
 832         mticcr  r4
 833         isync
 834
 835         /* Set-up dcache cacheability. */
 836         lis     r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
 837         ori     r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
 838         mtdccr  r4
 839
 840 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
 841                                 && !defined (CONFIG_XILINX_405)
 842         /*----------------------------------------------------------------------- */
 843         /* Tune the speed and size for flash CS0  */
 844         /*----------------------------------------------------------------------- */
 845         bl      ext_bus_cntlr_init
 846 #endif
 847
 848 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
 849         /*
 850          * For boards that don't have OCM and can't use the data cache
 851          * for their primordial stack, setup stack here directly after the
 852          * SDRAM is initialized in ext_bus_cntlr_init.
 853          */
 854         lis     r1, CONFIG_SYS_INIT_RAM_ADDR@h
 855         ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
 856
 857         li      r0, 0                   /* Make room for stack frame header and */
 858         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 859         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 860         /*
 861          * Set up a dummy frame to store reset vector as return address.
 862          * this causes stack underflow to reset board.
 863          */
 864         stwu    r1, -8(r1)              /* Save back chain and move SP */
 865         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
 866         ori     r0, r0, RESET_VECTOR@l
 867         stwu    r1, -8(r1)              /* Save back chain and move SP */
 868         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
 869 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS   || !CONFIG_SYS_TEM_STACK_OCM) */
 870
 871 #if defined(CONFIG_405EP)
 872         /*----------------------------------------------------------------------- */
 873         /* DMA Status, clear to come up clean */
 874         /*----------------------------------------------------------------------- */
 875         addis   r3,r0, 0xFFFF           /* Clear all existing DMA status */
 876         ori     r3,r3, 0xFFFF
 877         mtdcr   DMASR, r3
 878
 879         bl      ppc405ep_init           /* do ppc405ep specific init */
 880 #endif /* CONFIG_405EP */
 881
 882 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
 883 #if defined(CONFIG_405EZ)
 884         /********************************************************************
 885          * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
 886          *******************************************************************/
 887         /*
 888          * We can map the OCM on the PLB3, so map it at
 889          * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
 890          */
 891         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 892         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 893         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 894         mtdcr   OCM0_PLBCR1,r3          /* Set PLB Access */
 895         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 896         mtdcr   OCM0_PLBCR2,r3          /* Set PLB Access */
 897         isync
 898
 899         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 900         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 901         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 902         mtdcr   OCM0_DSRC1, r3          /* Set Data Side */
 903         mtdcr   OCM0_ISRC1, r3          /* Set Instruction Side */
 904         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 905         mtdcr   OCM0_DSRC2, r3          /* Set Data Side */
 906         mtdcr   OCM0_ISRC2, r3          /* Set Instruction Side */
 907         addis   r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
 908         mtdcr   OCM0_DISDPC,r3
 909
 910         isync
 911 #else /* CONFIG_405EZ */
 912         /********************************************************************
 913          * Setup OCM - On Chip Memory
 914          *******************************************************************/
 915         /* Setup OCM */
 916         lis     r0, 0x7FFF
 917         ori     r0, r0, 0xFFFF
 918         mfdcr   r3, OCM0_ISCNTL         /* get instr-side IRAM config */
 919         mfdcr   r4, OCM0_DSCNTL         /* get data-side IRAM config */
 920         and     r3, r3, r0              /* disable data-side IRAM */
 921         and     r4, r4, r0              /* disable data-side IRAM */
 922         mtdcr   OCM0_ISCNTL, r3         /* set instr-side IRAM config */
 923         mtdcr   OCM0_DSCNTL, r4         /* set data-side IRAM config */
 924         isync
 925
 926         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 927         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 928         mtdcr   OCM0_DSARC, r3
 929         addis   r4, 0, 0xC000           /* OCM data area enabled */
 930         mtdcr   OCM0_DSCNTL, r4
 931         isync
 932 #endif /* CONFIG_405EZ */
 933 #endif
 934
 935         /*----------------------------------------------------------------------- */
 936         /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 937         /*----------------------------------------------------------------------- */
 938 #ifdef CONFIG_SYS_INIT_DCACHE_CS
 939         li      r4, PBxAP
 940         mtdcr   EBC0_CFGADDR, r4
 941         lis     r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
 942         ori     r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
 943         mtdcr   EBC0_CFGDATA, r4
 944
 945         addi    r4, 0, PBxCR
 946         mtdcr   EBC0_CFGADDR, r4
 947         lis     r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
 948         ori     r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
 949         mtdcr   EBC0_CFGDATA, r4
 950
 951         /*
 952          * Enable the data cache for the 128MB storage access control region
 953          * at CONFIG_SYS_INIT_RAM_ADDR.
 954          */
 955         mfdccr  r4
 956         oris    r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
 957         ori     r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
 958         mtdccr  r4
 959
 960         /*
 961          * Preallocate data cache lines to be used to avoid a subsequent
 962          * cache miss and an ensuing machine check exception when exceptions
 963          * are enabled.
 964          */
 965         li      r0, 0
 966
 967         lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
 968         ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 969
 970         lis     r4, CONFIG_SYS_INIT_RAM_SIZE@h
 971         ori     r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
 972
 973         /*
 974          * Convert the size, in bytes, to the number of cache lines/blocks
 975          * to preallocate.
 976          */
 977         clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
 978         srwi    r5, r4, L1_CACHE_SHIFT
 979         beq     ..load_counter
 980         addi    r5, r5, 0x0001
 981 ..load_counter:
 982         mtctr   r5
 983
 984         /* Preallocate the computed number of cache blocks. */
 985 ..alloc_dcache_block:
 986         dcba    r0, r3
 987         addi    r3, r3, L1_CACHE_BYTES
 988         bdnz    ..alloc_dcache_block
 989         sync
 990
 991         /*
 992          * Load the initial stack pointer and data area and convert the size,
 993          * in bytes, to the number of words to initialize to a known value.
 994          */
 995         lis     r1, CONFIG_SYS_INIT_RAM_ADDR@h
 996         ori     r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 997
 998         lis     r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
 999         ori     r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1000         mtctr   r4
1001
1002         lis     r2, CONFIG_SYS_INIT_RAM_ADDR@h
1003         ori     r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1004
1005         lis     r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1006         ori     r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1007
1008 ..stackloop:
1009         stwu    r4, -4(r2)
1010         bdnz    ..stackloop
1011
1012         /*
1013          * Make room for stack frame header and clear final stack frame so
1014          * that stack backtraces terminate cleanly.
1015          */
1016         stwu    r0, -4(r1)
1017         stwu    r0, -4(r1)
1018
1019         /*
1020          * Set up a dummy frame to store reset vector as return address.
1021          * this causes stack underflow to reset board.
1022          */
1023         stwu    r1, -8(r1)              /* Save back chain and move SP */
1024         addis   r0, 0, RESET_VECTOR@h   /* Address of reset vector */
1025         ori     r0, r0, RESET_VECTOR@l
1026         stwu    r1, -8(r1)              /* Save back chain and move SP */
1027         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1028
1029 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1030         (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1031         /*
1032          * Stack in OCM.
1033          */
1034
1035         /* Set up Stack at top of OCM */
1036         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1037         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1038
1039         /* Set up a zeroized stack frame so that backtrace works right */
1040         li      r0, 0
1041         stwu    r0, -4(r1)
1042         stwu    r0, -4(r1)
1043
1044         /*
1045          * Set up a dummy frame to store reset vector as return address.
1046          * this causes stack underflow to reset board.
1047          */
1048         stwu    r1, -8(r1)              /* Save back chain and move SP */
1049         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
1050         ori     r0, r0, RESET_VECTOR@l
1051         stwu    r1, -8(r1)              /* Save back chain and move SP */
1052         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1053 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1054
1055 #ifdef CONFIG_NAND_SPL
1056         bl      nand_boot_common        /* will not return */
1057 #else
1058         GET_GOT                 /* initialize GOT access                        */
1059
1060         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
1061
1062         bl      board_init_f    /* run first part of init code (from Flash)     */
1063         /* NOTREACHED - board_init_f() does not return */
1064
1065 #endif /* CONFIG_NAND_SPL */
1066
1067 #endif  /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
1068         /*----------------------------------------------------------------------- */
1069
1070
1071 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
1072 /*
1073  * This code finishes saving the registers to the exception frame
1074  * and jumps to the appropriate handler for the exception.
1075  * Register r21 is pointer into trap frame, r1 has new stack pointer.
1076  */
1077         .globl  transfer_to_handler
1078 transfer_to_handler:
1079         stw     r22,_NIP(r21)
1080         lis     r22,MSR_POW@h
1081         andc    r23,r23,r22
1082         stw     r23,_MSR(r21)
1083         SAVE_GPR(7, r21)
1084         SAVE_4GPRS(8, r21)
1085         SAVE_8GPRS(12, r21)
1086         SAVE_8GPRS(24, r21)
1087         mflr    r23
1088         andi.   r24,r23,0x3f00          /* get vector offset */
1089         stw     r24,TRAP(r21)
1090         li      r22,0
1091         stw     r22,RESULT(r21)
1092         mtspr   SPRG2,r22               /* r1 is now kernel sp */
1093         lwz     r24,0(r23)              /* virtual address of handler */
1094         lwz     r23,4(r23)              /* where to go when done */
1095         mtspr   SRR0,r24
1096         mtspr   SRR1,r20
1097         mtlr    r23
1098         SYNC
1099         rfi                             /* jump to handler, enable MMU */
1100
1101 int_return:
1102         mfmsr   r28             /* Disable interrupts */
1103         li      r4,0
1104         ori     r4,r4,MSR_EE
1105         andc    r28,r28,r4
1106         SYNC                    /* Some chip revs need this... */
1107         mtmsr   r28
1108         SYNC
1109         lwz     r2,_CTR(r1)
1110         lwz     r0,_LINK(r1)
1111         mtctr   r2
1112         mtlr    r0
1113         lwz     r2,_XER(r1)
1114         lwz     r0,_CCR(r1)
1115         mtspr   XER,r2
1116         mtcrf   0xFF,r0
1117         REST_10GPRS(3, r1)
1118         REST_10GPRS(13, r1)
1119         REST_8GPRS(23, r1)
1120         REST_GPR(31, r1)
1121         lwz     r2,_NIP(r1)     /* Restore environment */
1122         lwz     r0,_MSR(r1)
1123         mtspr   SRR0,r2
1124         mtspr   SRR1,r0
1125         lwz     r0,GPR0(r1)
1126         lwz     r2,GPR2(r1)
1127         lwz     r1,GPR1(r1)
1128         SYNC
1129         rfi
1130
1131 crit_return:
1132         mfmsr   r28             /* Disable interrupts */
1133         li      r4,0
1134         ori     r4,r4,MSR_EE
1135         andc    r28,r28,r4
1136         SYNC                    /* Some chip revs need this... */
1137         mtmsr   r28
1138         SYNC
1139         lwz     r2,_CTR(r1)
1140         lwz     r0,_LINK(r1)
1141         mtctr   r2
1142         mtlr    r0
1143         lwz     r2,_XER(r1)
1144         lwz     r0,_CCR(r1)
1145         mtspr   XER,r2
1146         mtcrf   0xFF,r0
1147         REST_10GPRS(3, r1)
1148         REST_10GPRS(13, r1)
1149         REST_8GPRS(23, r1)
1150         REST_GPR(31, r1)
1151         lwz     r2,_NIP(r1)     /* Restore environment */
1152         lwz     r0,_MSR(r1)
1153         mtspr   SPRN_CSRR0,r2
1154         mtspr   SPRN_CSRR1,r0
1155         lwz     r0,GPR0(r1)
1156         lwz     r2,GPR2(r1)
1157         lwz     r1,GPR1(r1)
1158         SYNC
1159         rfci
1160
1161 #ifdef CONFIG_440
1162 mck_return:
1163         mfmsr   r28             /* Disable interrupts */
1164         li      r4,0
1165         ori     r4,r4,MSR_EE
1166         andc    r28,r28,r4
1167         SYNC                    /* Some chip revs need this... */
1168         mtmsr   r28
1169         SYNC
1170         lwz     r2,_CTR(r1)
1171         lwz     r0,_LINK(r1)
1172         mtctr   r2
1173         mtlr    r0
1174         lwz     r2,_XER(r1)
1175         lwz     r0,_CCR(r1)
1176         mtspr   XER,r2
1177         mtcrf   0xFF,r0
1178         REST_10GPRS(3, r1)
1179         REST_10GPRS(13, r1)
1180         REST_8GPRS(23, r1)
1181         REST_GPR(31, r1)
1182         lwz     r2,_NIP(r1)     /* Restore environment */
1183         lwz     r0,_MSR(r1)
1184         mtspr   SPRN_MCSRR0,r2
1185         mtspr   SPRN_MCSRR1,r0
1186         lwz     r0,GPR0(r1)
1187         lwz     r2,GPR2(r1)
1188         lwz     r1,GPR1(r1)
1189         SYNC
1190         rfmci
1191 #endif /* CONFIG_440 */
1192
1193
1194         .globl get_pvr
1195 get_pvr:
1196         mfspr   r3, PVR
1197         blr
1198
1199 /*------------------------------------------------------------------------------- */
1200 /* Function:     out16 */
1201 /* Description:  Output 16 bits */
1202 /*------------------------------------------------------------------------------- */
1203         .globl  out16
1204 out16:
1205         sth     r4,0x0000(r3)
1206         blr
1207
1208 /*------------------------------------------------------------------------------- */
1209 /* Function:     out16r */
1210 /* Description:  Byte reverse and output 16 bits */
1211 /*------------------------------------------------------------------------------- */
1212         .globl  out16r
1213 out16r:
1214         sthbrx  r4,r0,r3
1215         blr
1216
1217 /*------------------------------------------------------------------------------- */
1218 /* Function:     out32r */
1219 /* Description:  Byte reverse and output 32 bits */
1220 /*------------------------------------------------------------------------------- */
1221         .globl  out32r
1222 out32r:
1223         stwbrx  r4,r0,r3
1224         blr
1225
1226 /*------------------------------------------------------------------------------- */
1227 /* Function:     in16 */
1228 /* Description:  Input 16 bits */
1229 /*------------------------------------------------------------------------------- */
1230         .globl  in16
1231 in16:
1232         lhz     r3,0x0000(r3)
1233         blr
1234
1235 /*------------------------------------------------------------------------------- */
1236 /* Function:     in16r */
1237 /* Description:  Input 16 bits and byte reverse */
1238 /*------------------------------------------------------------------------------- */
1239         .globl  in16r
1240 in16r:
1241         lhbrx   r3,r0,r3
1242         blr
1243
1244 /*------------------------------------------------------------------------------- */
1245 /* Function:     in32r */
1246 /* Description:  Input 32 bits and byte reverse */
1247 /*------------------------------------------------------------------------------- */
1248         .globl  in32r
1249 in32r:
1250         lwbrx   r3,r0,r3
1251         blr
1252
1253 #if !defined(CONFIG_SPL_BUILD)
1254 /*
1255  * void relocate_code (addr_sp, gd, addr_moni)
1256  *
1257  * This "function" does not return, instead it continues in RAM
1258  * after relocating the monitor code.
1259  *
1260  * r3 = Relocated stack pointer
1261  * r4 = Relocated global data pointer
1262  * r5 = Relocated text pointer
1263  */
1264         .globl  relocate_code
1265 relocate_code:
1266 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1267         /*
1268          * We need to flush the initial global data (gd_t) and bd_info
1269          * before the dcache will be invalidated.
1270          */
1271
1272         /* Save registers */
1273         mr      r9, r3
1274         mr      r10, r4
1275         mr      r11, r5
1276
1277         /*
1278          * Flush complete dcache, this is faster than flushing the
1279          * ranges for global_data and bd_info instead.
1280          */
1281         bl      flush_dcache
1282
1283 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1284         /*
1285          * Undo the earlier data cache set-up for the primordial stack and
1286          * data area. First, invalidate the data cache and then disable data
1287          * cacheability for that area. Finally, restore the EBC values, if
1288          * any.
1289          */
1290
1291         /* Invalidate the primordial stack and data area in cache */
1292         lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
1293         ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1294
1295         lis     r4, CONFIG_SYS_INIT_RAM_SIZE@h
1296         ori     r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1297         add     r4, r4, r3
1298
1299         bl      invalidate_dcache_range
1300
1301         /* Disable cacheability for the region */
1302         mfdccr  r3
1303         lis     r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1304         ori     r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1305         and     r3, r3, r4
1306         mtdccr  r3
1307
1308         /* Restore the EBC parameters */
1309         li      r3, PBxAP
1310         mtdcr   EBC0_CFGADDR, r3
1311         lis     r3, PBxAP_VAL@h
1312         ori     r3, r3, PBxAP_VAL@l
1313         mtdcr   EBC0_CFGDATA, r3
1314
1315         li      r3, PBxCR
1316         mtdcr   EBC0_CFGADDR, r3
1317         lis     r3, PBxCR_VAL@h
1318         ori     r3, r3, PBxCR_VAL@l
1319         mtdcr   EBC0_CFGDATA, r3
1320 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1321
1322         /* Restore registers */
1323         mr      r3, r9
1324         mr      r4, r10
1325         mr      r5, r11
1326 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1327
1328 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1329         /*
1330          * Unlock the previously locked d-cache
1331          */
1332         msync
1333         isync
1334         /* set TFLOOR/NFLOOR to 0 again */
1335         lis     r6,0x0001
1336         ori     r6,r6,0xf800
1337         mtspr   SPRN_DVLIM,r6
1338         lis     r6,0x0000
1339         ori     r6,r6,0x0000
1340         mtspr   SPRN_DNV0,r6
1341         mtspr   SPRN_DNV1,r6
1342         mtspr   SPRN_DNV2,r6
1343         mtspr   SPRN_DNV3,r6
1344         mtspr   SPRN_DTV0,r6
1345         mtspr   SPRN_DTV1,r6
1346         mtspr   SPRN_DTV2,r6
1347         mtspr   SPRN_DTV3,r6
1348         msync
1349         isync
1350
1351         /* Invalidate data cache, now no longer our stack */
1352         dccci   0,0
1353         sync
1354         isync
1355 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1356
1357         /*
1358          * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1359          * to speed up the boot process. Now this cache needs to be disabled.
1360          */
1361 #if defined(CONFIG_440)
1362         /* Clear all potential pending exceptions */
1363         mfspr   r1,SPRN_MCSR
1364         mtspr   SPRN_MCSR,r1
1365         addi    r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH     /* Use defined TLB */
1366         tlbre   r0,r1,0x0002            /* Read contents */
1367         ori     r0,r0,0x0c00            /* Or in the inhibit, write through bit */
1368         tlbwe   r0,r1,0x0002            /* Save it out */
1369         sync
1370         isync
1371 #endif /* defined(CONFIG_440) */
1372         mr      r1,  r3         /* Set new stack pointer                */
1373         mr      r9,  r4         /* Save copy of Init Data pointer       */
1374         mr      r10, r5         /* Save copy of Destination Address     */
1375
1376         GET_GOT
1377         mr      r3,  r5                         /* Destination Address  */
1378         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
1379         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
1380         lwz     r5, GOT(__init_end)
1381         sub     r5, r5, r4
1382         li      r6, L1_CACHE_BYTES              /* Cache Line Size      */
1383
1384         /*
1385          * Fix GOT pointer:
1386          *
1387          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1388          *
1389          * Offset:
1390          */
1391         sub     r15, r10, r4
1392
1393         /* First our own GOT */
1394         add     r12, r12, r15
1395         /* then the one used by the C code */
1396         add     r30, r30, r15
1397
1398         /*
1399          * Now relocate code
1400          */
1401
1402         cmplw   cr1,r3,r4
1403         addi    r0,r5,3
1404         srwi.   r0,r0,2
1405         beq     cr1,4f          /* In place copy is not necessary       */
1406         beq     7f              /* Protect against 0 count              */
1407         mtctr   r0
1408         bge     cr1,2f
1409
1410         la      r8,-4(r4)
1411         la      r7,-4(r3)
1412 1:      lwzu    r0,4(r8)
1413         stwu    r0,4(r7)
1414         bdnz    1b
1415         b       4f
1416
1417 2:      slwi    r0,r0,2
1418         add     r8,r4,r0
1419         add     r7,r3,r0
1420 3:      lwzu    r0,-4(r8)
1421         stwu    r0,-4(r7)
1422         bdnz    3b
1423
1424 /*
1425  * Now flush the cache: note that we must start from a cache aligned
1426  * address. Otherwise we might miss one cache line.
1427  */
1428 4:      cmpwi   r6,0
1429         add     r5,r3,r5
1430         beq     7f              /* Always flush prefetch queue in any case */
1431         subi    r0,r6,1
1432         andc    r3,r3,r0
1433         mr      r4,r3
1434 5:      dcbst   0,r4
1435         add     r4,r4,r6
1436         cmplw   r4,r5
1437         blt     5b
1438         sync                    /* Wait for all dcbst to complete on bus */
1439         mr      r4,r3
1440 6:      icbi    0,r4
1441         add     r4,r4,r6
1442         cmplw   r4,r5
1443         blt     6b
1444 7:      sync                    /* Wait for all icbi to complete on bus */
1445         isync
1446
1447 /*
1448  * We are done. Do not return, instead branch to second part of board
1449  * initialization, now running from RAM.
1450  */
1451
1452         addi    r0, r10, in_ram - _start + _START_OFFSET
1453         mtlr    r0
1454         blr                             /* NEVER RETURNS! */
1455
1456 in_ram:
1457
1458         /*
1459          * Relocation Function, r12 point to got2+0x8000
1460          *
1461          * Adjust got2 pointers, no need to check for 0, this code
1462          * already puts a few entries in the table.
1463          */
1464         li      r0,__got2_entries@sectoff@l
1465         la      r3,GOT(_GOT2_TABLE_)
1466         lwz     r11,GOT(_GOT2_TABLE_)
1467         mtctr   r0
1468         sub     r11,r3,r11
1469         addi    r3,r3,-4
1470 1:      lwzu    r0,4(r3)
1471         cmpwi   r0,0
1472         beq-    2f
1473         add     r0,r0,r11
1474         stw     r0,0(r3)
1475 2:      bdnz    1b
1476
1477         /*
1478          * Now adjust the fixups and the pointers to the fixups
1479          * in case we need to move ourselves again.
1480          */
1481         li      r0,__fixup_entries@sectoff@l
1482         lwz     r3,GOT(_FIXUP_TABLE_)
1483         cmpwi   r0,0
1484         mtctr   r0
1485         addi    r3,r3,-4
1486         beq     4f
1487 3:      lwzu    r4,4(r3)
1488         lwzux   r0,r4,r11
1489         cmpwi   r0,0
1490         add     r0,r0,r11
1491         stw     r4,0(r3)
1492         beq-    5f
1493         stw     r0,0(r4)
1494 5:      bdnz    3b
1495 4:
1496 clear_bss:
1497         /*
1498          * Now clear BSS segment
1499          */
1500         lwz     r3,GOT(__bss_start)
1501         lwz     r4,GOT(__bss_end)
1502
1503         cmplw   0, r3, r4
1504         beq     7f
1505
1506         li      r0, 0
1507
1508         andi.   r5, r4, 3
1509         beq     6f
1510         sub     r4, r4, r5
1511         mtctr   r5
1512         mr      r5, r4
1513 5:      stb     r0, 0(r5)
1514         addi    r5, r5, 1
1515         bdnz    5b
1516 6:
1517         stw     r0, 0(r3)
1518         addi    r3, r3, 4
1519         cmplw   0, r3, r4
1520         bne     6b
1521
1522 7:
1523         mr      r3, r9          /* Init Data pointer            */
1524         mr      r4, r10         /* Destination Address          */
1525         bl      board_init_r
1526
1527         /*
1528          * Copy exception vector code to low memory
1529          *
1530          * r3: dest_addr
1531          * r7: source address, r8: end address, r9: target address
1532          */
1533         .globl  trap_init
1534 trap_init:
1535         mflr    r4                      /* save link register           */
1536         GET_GOT
1537         lwz     r7, GOT(_start_of_vectors)
1538         lwz     r8, GOT(_end_of_vectors)
1539
1540         li      r9, 0x100               /* reset vector always at 0x100 */
1541
1542         cmplw   0, r7, r8
1543         bgelr                           /* return if r7>=r8 - just in case */
1544 1:
1545         lwz     r0, 0(r7)
1546         stw     r0, 0(r9)
1547         addi    r7, r7, 4
1548         addi    r9, r9, 4
1549         cmplw   0, r7, r8
1550         bne     1b
1551
1552         /*
1553          * relocate `hdlr' and `int_return' entries
1554          */
1555         li      r7, .L_MachineCheck - _start + _START_OFFSET
1556         li      r8, Alignment - _start + _START_OFFSET
1557 2:
1558         bl      trap_reloc
1559         addi    r7, r7, 0x100           /* next exception vector */
1560         cmplw   0, r7, r8
1561         blt     2b
1562
1563         li      r7, .L_Alignment - _start + _START_OFFSET
1564         bl      trap_reloc
1565
1566         li      r7, .L_ProgramCheck - _start + _START_OFFSET
1567         bl      trap_reloc
1568
1569 #ifdef CONFIG_440
1570         li      r7, .L_FPUnavailable - _start + _START_OFFSET
1571         bl      trap_reloc
1572
1573         li      r7, .L_Decrementer - _start + _START_OFFSET
1574         bl      trap_reloc
1575
1576         li      r7, .L_APU - _start + _START_OFFSET
1577         bl      trap_reloc
1578
1579         li      r7, .L_InstructionTLBError - _start + _START_OFFSET
1580         bl      trap_reloc
1581
1582         li      r7, .L_DataTLBError - _start + _START_OFFSET
1583         bl      trap_reloc
1584 #else /* CONFIG_440 */
1585         li      r7, .L_PIT - _start + _START_OFFSET
1586         bl      trap_reloc
1587
1588         li      r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1589         bl      trap_reloc
1590
1591         li      r7, .L_DataTLBMiss - _start + _START_OFFSET
1592         bl      trap_reloc
1593 #endif /* CONFIG_440 */
1594
1595         li      r7, .L_DebugBreakpoint - _start + _START_OFFSET
1596         bl      trap_reloc
1597
1598 #if !defined(CONFIG_440)
1599         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1600         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1601         mtmsr   r7                      /* change MSR */
1602 #else
1603         bl      __440_msr_set
1604         b       __440_msr_continue
1605
1606 __440_msr_set:
1607         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1608         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1609         mtspr   SPRN_SRR1,r7
1610         mflr    r7
1611         mtspr   SPRN_SRR0,r7
1612         rfi
1613 __440_msr_continue:
1614 #endif
1615
1616         mtlr    r4                      /* restore link register        */
1617         blr
1618 #endif /* CONFIG_SPL_BUILD */
1619
1620 #if defined(CONFIG_440)
1621 /*----------------------------------------------------------------------------+
1622 | dcbz_area.
1623 +----------------------------------------------------------------------------*/
1624         function_prolog(dcbz_area)
1625         rlwinm. r5,r4,0,27,31
1626         rlwinm  r5,r4,27,5,31
1627         beq     ..d_ra2
1628         addi    r5,r5,0x0001
1629 ..d_ra2:mtctr   r5
1630 ..d_ag2:dcbz    r0,r3
1631         addi    r3,r3,32
1632         bdnz    ..d_ag2
1633         sync
1634         blr
1635         function_epilog(dcbz_area)
1636 #endif /* CONFIG_440 */
1637 #endif /* CONFIG_NAND_SPL */
1638
1639 /*------------------------------------------------------------------------------- */
1640 /* Function:     in8 */
1641 /* Description:  Input 8 bits */
1642 /*------------------------------------------------------------------------------- */
1643         .globl  in8
1644 in8:
1645         lbz     r3,0x0000(r3)
1646         blr
1647
1648 /*------------------------------------------------------------------------------- */
1649 /* Function:     out8 */
1650 /* Description:  Output 8 bits */
1651 /*------------------------------------------------------------------------------- */
1652         .globl  out8
1653 out8:
1654         stb     r4,0x0000(r3)
1655         blr
1656
1657 /*------------------------------------------------------------------------------- */
1658 /* Function:     out32 */
1659 /* Description:  Output 32 bits */
1660 /*------------------------------------------------------------------------------- */
1661         .globl  out32
1662 out32:
1663         stw     r4,0x0000(r3)
1664         blr
1665
1666 /*------------------------------------------------------------------------------- */
1667 /* Function:     in32 */
1668 /* Description:  Input 32 bits */
1669 /*------------------------------------------------------------------------------- */
1670         .globl  in32
1671 in32:
1672         lwz     3,0x0000(3)
1673         blr
1674
1675 /**************************************************************************/
1676 /* PPC405EP specific stuff                                                */
1677 /**************************************************************************/
1678 #ifdef CONFIG_405EP
1679 ppc405ep_init:
1680
1681 #ifdef CONFIG_BUBINGA
1682         /*
1683          * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1684          * function) to support FPGA and NVRAM accesses below.
1685          */
1686
1687         lis     r3,GPIO0_OSRH@h         /* config GPIO output select */
1688         ori     r3,r3,GPIO0_OSRH@l
1689         lis     r4,CONFIG_SYS_GPIO0_OSRH@h
1690         ori     r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1691         stw     r4,0(r3)
1692         lis     r3,GPIO0_OSRL@h
1693         ori     r3,r3,GPIO0_OSRL@l
1694         lis     r4,CONFIG_SYS_GPIO0_OSRL@h
1695         ori     r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1696         stw     r4,0(r3)
1697
1698         lis     r3,GPIO0_ISR1H@h        /* config GPIO input select */
1699         ori     r3,r3,GPIO0_ISR1H@l
1700         lis     r4,CONFIG_SYS_GPIO0_ISR1H@h
1701         ori     r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1702         stw     r4,0(r3)
1703         lis     r3,GPIO0_ISR1L@h
1704         ori     r3,r3,GPIO0_ISR1L@l
1705         lis     r4,CONFIG_SYS_GPIO0_ISR1L@h
1706         ori     r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1707         stw     r4,0(r3)
1708
1709         lis     r3,GPIO0_TSRH@h         /* config GPIO three-state select */
1710         ori     r3,r3,GPIO0_TSRH@l
1711         lis     r4,CONFIG_SYS_GPIO0_TSRH@h
1712         ori     r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1713         stw     r4,0(r3)
1714         lis     r3,GPIO0_TSRL@h
1715         ori     r3,r3,GPIO0_TSRL@l
1716         lis     r4,CONFIG_SYS_GPIO0_TSRL@h
1717         ori     r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1718         stw     r4,0(r3)
1719
1720         lis     r3,GPIO0_TCR@h          /* config GPIO driver output enables */
1721         ori     r3,r3,GPIO0_TCR@l
1722         lis     r4,CONFIG_SYS_GPIO0_TCR@h
1723         ori     r4,r4,CONFIG_SYS_GPIO0_TCR@l
1724         stw     r4,0(r3)
1725
1726         li      r3,PB1AP                /* program EBC bank 1 for RTC access */
1727         mtdcr   EBC0_CFGADDR,r3
1728         lis     r3,CONFIG_SYS_EBC_PB1AP@h
1729         ori     r3,r3,CONFIG_SYS_EBC_PB1AP@l
1730         mtdcr   EBC0_CFGDATA,r3
1731         li      r3,PB1CR
1732         mtdcr   EBC0_CFGADDR,r3
1733         lis     r3,CONFIG_SYS_EBC_PB1CR@h
1734         ori     r3,r3,CONFIG_SYS_EBC_PB1CR@l
1735         mtdcr   EBC0_CFGDATA,r3
1736
1737         li      r3,PB1AP                /* program EBC bank 1 for RTC access */
1738         mtdcr   EBC0_CFGADDR,r3
1739         lis     r3,CONFIG_SYS_EBC_PB1AP@h
1740         ori     r3,r3,CONFIG_SYS_EBC_PB1AP@l
1741         mtdcr   EBC0_CFGDATA,r3
1742         li      r3,PB1CR
1743         mtdcr   EBC0_CFGADDR,r3
1744         lis     r3,CONFIG_SYS_EBC_PB1CR@h
1745         ori     r3,r3,CONFIG_SYS_EBC_PB1CR@l
1746         mtdcr   EBC0_CFGDATA,r3
1747
1748         li      r3,PB4AP                /* program EBC bank 4 for FPGA access */
1749         mtdcr   EBC0_CFGADDR,r3
1750         lis     r3,CONFIG_SYS_EBC_PB4AP@h
1751         ori     r3,r3,CONFIG_SYS_EBC_PB4AP@l
1752         mtdcr   EBC0_CFGDATA,r3
1753         li      r3,PB4CR
1754         mtdcr   EBC0_CFGADDR,r3
1755         lis     r3,CONFIG_SYS_EBC_PB4CR@h
1756         ori     r3,r3,CONFIG_SYS_EBC_PB4CR@l
1757         mtdcr   EBC0_CFGDATA,r3
1758 #endif
1759
1760         /*
1761         !-----------------------------------------------------------------------
1762         ! Check to see if chip is in bypass mode.
1763         ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1764         ! CPU reset   Otherwise, skip this step and keep going.
1765         ! Note:  Running BIOS in bypass mode is not supported since PLB speed
1766         !        will not be fast enough for the SDRAM (min 66MHz)
1767         !-----------------------------------------------------------------------
1768         */
1769         mfdcr   r5, CPC0_PLLMR1
1770         rlwinm  r4,r5,1,0x1             /* get system clock source (SSCS) */
1771         cmpi    cr0,0,r4,0x1
1772
1773         beq    pll_done                 /* if SSCS =b'1' then PLL has */
1774                                         /* already been set */
1775                                         /* and CPU has been reset */
1776                                         /* so skip to next section */
1777
1778 #ifdef CONFIG_BUBINGA
1779         /*
1780         !-----------------------------------------------------------------------
1781         ! Read NVRAM to get value to write in PLLMR.
1782         ! If value has not been correctly saved, write default value
1783         ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1784         ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1785         !
1786         ! WARNING:  This code assumes the first three words in the nvram_t
1787         !           structure in openbios.h.  Changing the beginning of
1788         !           the structure will break this code.
1789         !
1790         !-----------------------------------------------------------------------
1791         */
1792         addis   r3,0,NVRAM_BASE@h
1793         addi    r3,r3,NVRAM_BASE@l
1794
1795         lwz     r4, 0(r3)
1796         addis   r5,0,NVRVFY1@h
1797         addi    r5,r5,NVRVFY1@l
1798         cmp     cr0,0,r4,r5             /* Compare 1st NVRAM Magic number*/
1799         bne     ..no_pllset
1800         addi    r3,r3,4
1801         lwz     r4, 0(r3)
1802         addis   r5,0,NVRVFY2@h
1803         addi    r5,r5,NVRVFY2@l
1804         cmp     cr0,0,r4,r5             /* Compare 2 NVRAM Magic number */
1805         bne     ..no_pllset
1806         addi    r3,r3,8                 /* Skip over conf_size */
1807         lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
1808         lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
1809         rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
1810         cmpi     cr0,0,r5,1             /* See if PLL is locked */
1811         beq     pll_write
1812 ..no_pllset:
1813 #endif /* CONFIG_BUBINGA */
1814
1815 #ifdef CONFIG_TAIHU
1816         mfdcr   r4, CPC0_BOOT
1817         andi.   r5, r4, CPC0_BOOT_SEP@l
1818         bne     strap_1                 /* serial eeprom present */
1819         addis   r5,0,CPLD_REG0_ADDR@h
1820         ori     r5,r5,CPLD_REG0_ADDR@l
1821         andi.   r5, r5, 0x10
1822         bne     _pci_66mhz
1823 #endif /* CONFIG_TAIHU */
1824
1825 #if defined(CONFIG_ZEUS)
1826         mfdcr   r4, CPC0_BOOT
1827         andi.   r5, r4, CPC0_BOOT_SEP@l
1828         bne     strap_1                 /* serial eeprom present */
1829         lis     r3,0x0000
1830         addi    r3,r3,0x3030
1831         lis     r4,0x8042
1832         addi    r4,r4,0x223e
1833         b       1f
1834 strap_1:
1835         mfdcr   r3, CPC0_PLLMR0
1836         mfdcr   r4, CPC0_PLLMR1
1837         b       1f
1838 #endif
1839
1840         addis   r3,0,PLLMR0_DEFAULT@h   /* PLLMR0 default value */
1841         ori     r3,r3,PLLMR0_DEFAULT@l  /* */
1842         addis   r4,0,PLLMR1_DEFAULT@h   /* PLLMR1 default value */
1843         ori     r4,r4,PLLMR1_DEFAULT@l  /* */
1844
1845 #ifdef CONFIG_TAIHU
1846         b       1f
1847 _pci_66mhz:
1848         addis   r3,0,PLLMR0_DEFAULT_PCI66@h
1849         ori     r3,r3,PLLMR0_DEFAULT_PCI66@l
1850         addis   r4,0,PLLMR1_DEFAULT_PCI66@h
1851         ori     r4,r4,PLLMR1_DEFAULT_PCI66@l
1852         b       1f
1853 strap_1:
1854         mfdcr   r3, CPC0_PLLMR0
1855         mfdcr   r4, CPC0_PLLMR1
1856 #endif /* CONFIG_TAIHU */
1857
1858 1:
1859         b       pll_write               /* Write the CPC0_PLLMR with new value */
1860
1861 pll_done:
1862         /*
1863         !-----------------------------------------------------------------------
1864         ! Clear Soft Reset Register
1865         ! This is needed to enable PCI if not booting from serial EPROM
1866         !-----------------------------------------------------------------------
1867                 */
1868         addi    r3, 0, 0x0
1869         mtdcr   CPC0_SRR, r3
1870
1871         addis    r3,0,0x0010
1872         mtctr   r3
1873 pci_wait:
1874         bdnz    pci_wait
1875
1876         blr                             /* return to main code */
1877
1878 /*
1879 !-----------------------------------------------------------------------------
1880 ! Function:     pll_write
1881 ! Description:  Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1882 !               That is:
1883 !                         1.  Pll is first disabled (de-activated by putting in bypass mode)
1884 !                         2.  PLL is reset
1885 !                         3.  Clock dividers are set while PLL is held in reset and bypassed
1886 !                         4.  PLL Reset is cleared
1887 !                         5.  Wait 100us for PLL to lock
1888 !                         6.  A core reset is performed
1889 ! Input: r3 = Value to write to CPC0_PLLMR0
1890 ! Input: r4 = Value to write to CPC0_PLLMR1
1891 ! Output r3 = none
1892 !-----------------------------------------------------------------------------
1893 */
1894         .globl  pll_write
1895 pll_write:
1896         mfdcr  r5, CPC0_UCR
1897         andis. r5,r5,0xFFFF
1898         ori    r5,r5,0x0101             /* Stop the UART clocks */
1899         mtdcr  CPC0_UCR,r5              /* Before changing PLL */
1900
1901         mfdcr  r5, CPC0_PLLMR1
1902         rlwinm r5,r5,0,0x7FFFFFFF       /* Disable PLL */
1903         mtdcr   CPC0_PLLMR1,r5
1904         oris   r5,r5,0x4000             /* Set PLL Reset */
1905         mtdcr   CPC0_PLLMR1,r5
1906
1907         mtdcr   CPC0_PLLMR0,r3          /* Set clock dividers */
1908         rlwinm r5,r4,0,0x3FFFFFFF       /* Reset & Bypass new PLL dividers */
1909         oris   r5,r5,0x4000             /* Set PLL Reset */
1910         mtdcr   CPC0_PLLMR1,r5          /* Set clock dividers */
1911         rlwinm r5,r5,0,0xBFFFFFFF       /* Clear PLL Reset */
1912         mtdcr   CPC0_PLLMR1,r5
1913
1914                 /*
1915         ! Wait min of 100us for PLL to lock.
1916         ! See CMOS 27E databook for more info.
1917         ! At 200MHz, that means waiting 20,000 instructions
1918                  */
1919         addi    r3,0,20000              /* 2000 = 0x4e20 */
1920         mtctr   r3
1921 pll_wait:
1922         bdnz    pll_wait
1923
1924         oris   r5,r5,0x8000             /* Enable PLL */
1925         mtdcr   CPC0_PLLMR1,r5          /* Engage */
1926
1927         /*
1928          * Reset CPU to guarantee timings are OK
1929          * Not sure if this is needed...
1930          */
1931         addis r3,0,0x1000
1932         mtspr SPRN_DBCR0,r3             /* This will cause a CPU core reset, and */
1933                                         /* execution will continue from the poweron */
1934                                         /* vector of 0xfffffffc */
1935 #endif /* CONFIG_405EP */
1936
1937 #if defined(CONFIG_440)
1938 /*----------------------------------------------------------------------------+
1939 | mttlb3.
1940 +----------------------------------------------------------------------------*/
1941         function_prolog(mttlb3)
1942         TLBWE(4,3,2)
1943         blr
1944         function_epilog(mttlb3)
1945
1946 /*----------------------------------------------------------------------------+
1947 | mftlb3.
1948 +----------------------------------------------------------------------------*/
1949         function_prolog(mftlb3)
1950         TLBRE(3,3,2)
1951         blr
1952         function_epilog(mftlb3)
1953
1954 /*----------------------------------------------------------------------------+
1955 | mttlb2.
1956 +----------------------------------------------------------------------------*/
1957         function_prolog(mttlb2)
1958         TLBWE(4,3,1)
1959         blr
1960         function_epilog(mttlb2)
1961
1962 /*----------------------------------------------------------------------------+
1963 | mftlb2.
1964 +----------------------------------------------------------------------------*/
1965         function_prolog(mftlb2)
1966         TLBRE(3,3,1)
1967         blr
1968         function_epilog(mftlb2)
1969
1970 /*----------------------------------------------------------------------------+
1971 | mttlb1.
1972 +----------------------------------------------------------------------------*/
1973         function_prolog(mttlb1)
1974         TLBWE(4,3,0)
1975         blr
1976         function_epilog(mttlb1)
1977
1978 /*----------------------------------------------------------------------------+
1979 | mftlb1.
1980 +----------------------------------------------------------------------------*/
1981         function_prolog(mftlb1)
1982         TLBRE(3,3,0)
1983         blr
1984         function_epilog(mftlb1)
1985 #endif /* CONFIG_440 */
1986
1987 #if defined(CONFIG_NAND_SPL)
1988 /*
1989  * void nand_boot_relocate(dst, src, bytes)
1990  *
1991  * r3 = Destination address to copy code to (in SDRAM)
1992  * r4 = Source address to copy code from
1993  * r5 = size to copy in bytes
1994  */
1995 nand_boot_relocate:
1996         mr      r6,r3
1997         mr      r7,r4
1998         mflr    r8
1999
2000         /*
2001          * Copy SPL from icache into SDRAM
2002          */
2003         subi    r3,r3,4
2004         subi    r4,r4,4
2005         srwi    r5,r5,2
2006         mtctr   r5
2007 ..spl_loop:
2008         lwzu    r0,4(r4)
2009         stwu    r0,4(r3)
2010         bdnz    ..spl_loop
2011
2012         /*
2013          * Calculate "corrected" link register, so that we "continue"
2014          * in execution in destination range
2015          */
2016         sub     r3,r7,r6        /* r3 = src - dst */
2017         sub     r8,r8,r3        /* r8 = link-reg - (src - dst) */
2018         mtlr    r8
2019         blr
2020
2021 nand_boot_common:
2022         /*
2023          * First initialize SDRAM. It has to be available *before* calling
2024          * nand_boot().
2025          */
2026         lis     r3,CONFIG_SYS_SDRAM_BASE@h
2027         ori     r3,r3,CONFIG_SYS_SDRAM_BASE@l
2028         bl      initdram
2029
2030         /*
2031          * Now copy the 4k SPL code into SDRAM and continue execution
2032          * from there.
2033          */
2034         lis     r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2035         ori     r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2036         lis     r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2037         ori     r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2038         lis     r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2039         ori     r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2040         bl      nand_boot_relocate
2041
2042         /*
2043          * We're running from SDRAM now!!!
2044          *
2045          * It is necessary for 4xx systems to relocate from running at
2046          * the original location (0xfffffxxx) to somewhere else (SDRAM
2047          * preferably). This is because CS0 needs to be reconfigured for
2048          * NAND access. And we can't reconfigure this CS when currently
2049          * "running" from it.
2050          */
2051
2052         /*
2053          * Finally call nand_boot() to load main NAND U-Boot image from
2054          * NAND and jump to it.
2055          */
2056         bl      nand_boot               /* will not return */
2057 #endif /* CONFIG_NAND_SPL */