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Merge branch 'master' of git://git.denx.de/u-boot-arm
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / start.S
1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
10 */
11
12 /*
13 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
14 *
15 * The following description only applies to the NOR flash style booting.
16 * NAND booting is different. For more details about NAND booting on 4xx
17 * take a look at doc/README.nand-boot-ppc440.
18 *
19 * The CPU starts at address 0xfffffffc (last word in the address space).
20 * The U-Boot image therefore has to be located in the "upper" area of the
21 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
22 * the boot chip-select (CS0) is quite big and covers this area. On the
23 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
24 * reconfigure this CS0 (and other chip-selects as well when configured
25 * this way) in the boot process to the "correct" values matching the
26 * board layout.
27 */
28
29 #include <asm-offsets.h>
30 #include <config.h>
31 #include <asm/ppc4xx.h>
32 #include <version.h>
33
34 #include <ppc_asm.tmpl>
35 #include <ppc_defs.h>
36
37 #include <asm/cache.h>
38 #include <asm/mmu.h>
39 #include <asm/ppc4xx-isram.h>
40
41 #ifdef CONFIG_SYS_INIT_DCACHE_CS
42 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
43 # define PBxAP PB1AP
44 # define PBxCR PB0CR
45 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
46 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
47 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
48 # endif
49 # endif
50 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
51 # define PBxAP PB1AP
52 # define PBxCR PB1CR
53 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
54 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
55 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
56 # endif
57 # endif
58 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
59 # define PBxAP PB2AP
60 # define PBxCR PB2CR
61 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
62 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
63 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
64 # endif
65 # endif
66 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
67 # define PBxAP PB3AP
68 # define PBxCR PB3CR
69 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
70 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
71 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
72 # endif
73 # endif
74 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
75 # define PBxAP PB4AP
76 # define PBxCR PB4CR
77 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
78 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
79 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
80 # endif
81 # endif
82 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
83 # define PBxAP PB5AP
84 # define PBxCR PB5CR
85 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
86 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
87 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
88 # endif
89 # endif
90 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
91 # define PBxAP PB6AP
92 # define PBxCR PB6CR
93 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
94 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
95 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
96 # endif
97 # endif
98 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
99 # define PBxAP PB7AP
100 # define PBxCR PB7CR
101 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
102 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
103 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
104 # endif
105 # endif
106 # ifndef PBxAP_VAL
107 # define PBxAP_VAL 0
108 # endif
109 # ifndef PBxCR_VAL
110 # define PBxCR_VAL 0
111 # endif
112 /*
113 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
114 * used as temporary stack pointer for the primordial stack
115 */
116 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
117 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
118 EBC_BXAP_TWT_ENCODE(7) | \
119 EBC_BXAP_BCE_DISABLE | \
120 EBC_BXAP_BCT_2TRANS | \
121 EBC_BXAP_CSN_ENCODE(0) | \
122 EBC_BXAP_OEN_ENCODE(0) | \
123 EBC_BXAP_WBN_ENCODE(0) | \
124 EBC_BXAP_WBF_ENCODE(0) | \
125 EBC_BXAP_TH_ENCODE(2) | \
126 EBC_BXAP_RE_DISABLED | \
127 EBC_BXAP_SOR_NONDELAYED | \
128 EBC_BXAP_BEM_WRITEONLY | \
129 EBC_BXAP_PEN_DISABLED)
130 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
131 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
132 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
133 EBC_BXCR_BS_64MB | \
134 EBC_BXCR_BU_RW | \
135 EBC_BXCR_BW_16BIT)
136 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
137 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
138 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
139 # endif
140 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
141
142 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
143 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
144 #endif
145
146 /*
147 * Unless otherwise overriden, enable two 128MB cachable instruction regions
148 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
149 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
150 */
151 #if !defined(CONFIG_SYS_FLASH_BASE)
152 /* If not already defined, set it to the "last" 128MByte region */
153 # define CONFIG_SYS_FLASH_BASE 0xf8000000
154 #endif
155 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
156 # define CONFIG_SYS_ICACHE_SACR_VALUE \
157 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
158 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
159 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
160 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
161
162 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
163 # define CONFIG_SYS_DCACHE_SACR_VALUE \
164 (0x00000000)
165 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
166
167 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
168 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
169 #endif
170
171 #define function_prolog(func_name) .text; \
172 .align 2; \
173 .globl func_name; \
174 func_name:
175 #define function_epilog(func_name) .type func_name,@function; \
176 .size func_name,.-func_name
177
178 /* We don't want the MMU yet.
179 */
180 #undef MSR_KERNEL
181 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
182
183
184 .extern ext_bus_cntlr_init
185
186 /*
187 * Set up GOT: Global Offset Table
188 *
189 * Use r12 to access the GOT
190 */
191 #if !defined(CONFIG_SPL_BUILD)
192 START_GOT
193 GOT_ENTRY(_GOT2_TABLE_)
194 GOT_ENTRY(_FIXUP_TABLE_)
195
196 GOT_ENTRY(_start)
197 GOT_ENTRY(_start_of_vectors)
198 GOT_ENTRY(_end_of_vectors)
199 GOT_ENTRY(transfer_to_handler)
200
201 GOT_ENTRY(__init_end)
202 GOT_ENTRY(__bss_end)
203 GOT_ENTRY(__bss_start)
204 END_GOT
205 #endif /* CONFIG_SPL_BUILD */
206
207 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
208 /*
209 * 4xx RAM-booting U-Boot image is started from offset 0
210 */
211 .text
212 bl _start_440
213 #endif
214
215 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
216 /*
217 * This is the entry of the real U-Boot from a board port
218 * that supports SPL booting on the PPC4xx. We only need
219 * to call board_init_f() here. Everything else has already
220 * been done in the SPL u-boot version.
221 */
222 GET_GOT /* initialize GOT access */
223 bl board_init_f /* run 1st part of board init code (in Flash)*/
224 /* NOTREACHED - board_init_f() does not return */
225 #endif
226
227 /*
228 * 440 Startup -- on reset only the top 4k of the effective
229 * address space is mapped in by an entry in the instruction
230 * and data shadow TLB. The .bootpg section is located in the
231 * top 4k & does only what's necessary to map in the the rest
232 * of the boot rom. Once the boot rom is mapped in we can
233 * proceed with normal startup.
234 *
235 * NOTE: CS0 only covers the top 2MB of the effective address
236 * space after reset.
237 */
238
239 #if defined(CONFIG_440)
240 .section .bootpg,"ax"
241 .globl _start_440
242
243 /**************************************************************************/
244 _start_440:
245 /*--------------------------------------------------------------------+
246 | 440EPX BUP Change - Hardware team request
247 +--------------------------------------------------------------------*/
248 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
249 sync
250 nop
251 nop
252 #endif
253 /*----------------------------------------------------------------+
254 | Core bug fix. Clear the esr
255 +-----------------------------------------------------------------*/
256 li r0,0
257 mtspr SPRN_ESR,r0
258 /*----------------------------------------------------------------*/
259 /* Clear and set up some registers. */
260 /*----------------------------------------------------------------*/
261 iccci r0,r0 /* NOTE: operands not used for 440 */
262 dccci r0,r0 /* NOTE: operands not used for 440 */
263 sync
264 li r0,0
265 mtspr SPRN_SRR0,r0
266 mtspr SPRN_SRR1,r0
267 mtspr SPRN_CSRR0,r0
268 mtspr SPRN_CSRR1,r0
269 /* NOTE: 440GX adds machine check status regs */
270 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
271 mtspr SPRN_MCSRR0,r0
272 mtspr SPRN_MCSRR1,r0
273 mfspr r1,SPRN_MCSR
274 mtspr SPRN_MCSR,r1
275 #endif
276
277 /*----------------------------------------------------------------*/
278 /* CCR0 init */
279 /*----------------------------------------------------------------*/
280 /* Disable store gathering & broadcast, guarantee inst/data
281 * cache block touch, force load/store alignment
282 * (see errata 1.12: 440_33)
283 */
284 lis r1,0x0030 /* store gathering & broadcast disable */
285 ori r1,r1,0x6000 /* cache touch */
286 mtspr SPRN_CCR0,r1
287
288 /*----------------------------------------------------------------*/
289 /* Initialize debug */
290 /*----------------------------------------------------------------*/
291 mfspr r1,SPRN_DBCR0
292 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
293 bne skip_debug_init /* if set, don't clear debug register */
294 mfspr r1,SPRN_CCR0
295 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
296 mtspr SPRN_CCR0,r1
297 mtspr SPRN_DBCR0,r0
298 mtspr SPRN_DBCR1,r0
299 mtspr SPRN_DBCR2,r0
300 mtspr SPRN_IAC1,r0
301 mtspr SPRN_IAC2,r0
302 mtspr SPRN_IAC3,r0
303 mtspr SPRN_DAC1,r0
304 mtspr SPRN_DAC2,r0
305 mtspr SPRN_DVC1,r0
306 mtspr SPRN_DVC2,r0
307
308 mfspr r1,SPRN_DBSR
309 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
310 skip_debug_init:
311
312 #if defined (CONFIG_440SPE)
313 /*----------------------------------------------------------------+
314 | Initialize Core Configuration Reg1.
315 | a. ICDPEI: Record even parity. Normal operation.
316 | b. ICTPEI: Record even parity. Normal operation.
317 | c. DCTPEI: Record even parity. Normal operation.
318 | d. DCDPEI: Record even parity. Normal operation.
319 | e. DCUPEI: Record even parity. Normal operation.
320 | f. DCMPEI: Record even parity. Normal operation.
321 | g. FCOM: Normal operation
322 | h. MMUPEI: Record even parity. Normal operation.
323 | i. FFF: Flush only as much data as necessary.
324 | j. TCS: Timebase increments from CPU clock.
325 +-----------------------------------------------------------------*/
326 li r0,0
327 mtspr SPRN_CCR1, r0
328
329 /*----------------------------------------------------------------+
330 | Reset the timebase.
331 | The previous write to CCR1 sets the timebase source.
332 +-----------------------------------------------------------------*/
333 mtspr SPRN_TBWL, r0
334 mtspr SPRN_TBWU, r0
335 #endif
336
337 /*----------------------------------------------------------------*/
338 /* Setup interrupt vectors */
339 /*----------------------------------------------------------------*/
340 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
341 li r1,0x0100
342 mtspr SPRN_IVOR0,r1 /* Critical input */
343 li r1,0x0200
344 mtspr SPRN_IVOR1,r1 /* Machine check */
345 li r1,0x0300
346 mtspr SPRN_IVOR2,r1 /* Data storage */
347 li r1,0x0400
348 mtspr SPRN_IVOR3,r1 /* Instruction storage */
349 li r1,0x0500
350 mtspr SPRN_IVOR4,r1 /* External interrupt */
351 li r1,0x0600
352 mtspr SPRN_IVOR5,r1 /* Alignment */
353 li r1,0x0700
354 mtspr SPRN_IVOR6,r1 /* Program check */
355 li r1,0x0800
356 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
357 li r1,0x0c00
358 mtspr SPRN_IVOR8,r1 /* System call */
359 li r1,0x0a00
360 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
361 li r1,0x0900
362 mtspr SPRN_IVOR10,r1 /* Decrementer */
363 li r1,0x1300
364 mtspr SPRN_IVOR13,r1 /* Data TLB error */
365 li r1,0x1400
366 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
367 li r1,0x2000
368 mtspr SPRN_IVOR15,r1 /* Debug */
369
370 /*----------------------------------------------------------------*/
371 /* Configure cache regions */
372 /*----------------------------------------------------------------*/
373 mtspr SPRN_INV0,r0
374 mtspr SPRN_INV1,r0
375 mtspr SPRN_INV2,r0
376 mtspr SPRN_INV3,r0
377 mtspr SPRN_DNV0,r0
378 mtspr SPRN_DNV1,r0
379 mtspr SPRN_DNV2,r0
380 mtspr SPRN_DNV3,r0
381 mtspr SPRN_ITV0,r0
382 mtspr SPRN_ITV1,r0
383 mtspr SPRN_ITV2,r0
384 mtspr SPRN_ITV3,r0
385 mtspr SPRN_DTV0,r0
386 mtspr SPRN_DTV1,r0
387 mtspr SPRN_DTV2,r0
388 mtspr SPRN_DTV3,r0
389
390 /*----------------------------------------------------------------*/
391 /* Cache victim limits */
392 /*----------------------------------------------------------------*/
393 /* floors 0, ceiling max to use the entire cache -- nothing locked
394 */
395 lis r1,0x0001
396 ori r1,r1,0xf800
397 mtspr SPRN_IVLIM,r1
398 mtspr SPRN_DVLIM,r1
399
400 /*----------------------------------------------------------------+
401 |Initialize MMUCR[STID] = 0.
402 +-----------------------------------------------------------------*/
403 mfspr r0,SPRN_MMUCR
404 addis r1,0,0xFFFF
405 ori r1,r1,0xFF00
406 and r0,r0,r1
407 mtspr SPRN_MMUCR,r0
408
409 /*----------------------------------------------------------------*/
410 /* Clear all TLB entries -- TID = 0, TS = 0 */
411 /*----------------------------------------------------------------*/
412 addis r0,0,0x0000
413 #ifdef CONFIG_SYS_RAMBOOT
414 li r4,0 /* Start with TLB #0 */
415 #else
416 li r4,1 /* Start with TLB #1 */
417 #endif
418 li r1,64 /* 64 TLB entries */
419 sub r1,r1,r4 /* calculate last TLB # */
420 mtctr r1
421 rsttlb:
422 #ifdef CONFIG_SYS_RAMBOOT
423 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
424 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
425 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
426 #endif
427 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
428 tlbwe r0,r4,1
429 tlbwe r0,r4,2
430 tlbnxt: addi r4,r4,1 /* Next TLB */
431 bdnz rsttlb
432
433 /*----------------------------------------------------------------*/
434 /* TLB entry setup -- step thru tlbtab */
435 /*----------------------------------------------------------------*/
436 #if defined(CONFIG_440SPE_REVA)
437 /*----------------------------------------------------------------*/
438 /* We have different TLB tables for revA and rev B of 440SPe */
439 /*----------------------------------------------------------------*/
440 mfspr r1, PVR
441 lis r0,0x5342
442 ori r0,r0,0x1891
443 cmpw r7,r1,r0
444 bne r7,..revA
445 bl tlbtabB
446 b ..goon
447 ..revA:
448 bl tlbtabA
449 ..goon:
450 #else
451 bl tlbtab /* Get tlbtab pointer */
452 #endif
453 mr r5,r0
454 li r1,0x003f /* 64 TLB entries max */
455 mtctr r1
456 li r4,0 /* TLB # */
457
458 addi r5,r5,-4
459 1:
460 #ifdef CONFIG_SYS_RAMBOOT
461 tlbre r3,r4,0 /* Read contents from TLB word #0 */
462 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
463 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
464 #endif
465 lwzu r0,4(r5)
466 cmpwi r0,0
467 beq 2f /* 0 marks end */
468 lwzu r1,4(r5)
469 lwzu r2,4(r5)
470 tlbwe r0,r4,0 /* TLB Word 0 */
471 tlbwe r1,r4,1 /* TLB Word 1 */
472 tlbwe r2,r4,2 /* TLB Word 2 */
473 tlbnx2: addi r4,r4,1 /* Next TLB */
474 bdnz 1b
475
476 /*----------------------------------------------------------------*/
477 /* Continue from 'normal' start */
478 /*----------------------------------------------------------------*/
479 2:
480 bl 3f
481 b _start
482
483 3: li r0,0
484 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
485 mflr r1
486 mtspr SPRN_SRR0,r1
487 rfi
488 #endif /* CONFIG_440 */
489
490 /*
491 * r3 - 1st arg to board_init(): IMMP pointer
492 * r4 - 2nd arg to board_init(): boot flag
493 */
494 #if !defined(CONFIG_SPL_BUILD)
495 .text
496 .long 0x27051956 /* U-Boot Magic Number */
497 .globl version_string
498 version_string:
499 .ascii U_BOOT_VERSION_STRING, "\0"
500
501 . = EXC_OFF_SYS_RESET
502 .globl _start_of_vectors
503 _start_of_vectors:
504
505 /* Critical input. */
506 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
507
508 #ifdef CONFIG_440
509 /* Machine check */
510 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
511 #else
512 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
513 #endif /* CONFIG_440 */
514
515 /* Data Storage exception. */
516 STD_EXCEPTION(0x300, DataStorage, UnknownException)
517
518 /* Instruction Storage exception. */
519 STD_EXCEPTION(0x400, InstStorage, UnknownException)
520
521 /* External Interrupt exception. */
522 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
523
524 /* Alignment exception. */
525 . = 0x600
526 Alignment:
527 EXCEPTION_PROLOG(SRR0, SRR1)
528 mfspr r4,DAR
529 stw r4,_DAR(r21)
530 mfspr r5,DSISR
531 stw r5,_DSISR(r21)
532 addi r3,r1,STACK_FRAME_OVERHEAD
533 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
534
535 /* Program check exception */
536 . = 0x700
537 ProgramCheck:
538 EXCEPTION_PROLOG(SRR0, SRR1)
539 addi r3,r1,STACK_FRAME_OVERHEAD
540 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
541 MSR_KERNEL, COPY_EE)
542
543 #ifdef CONFIG_440
544 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
545 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
546 STD_EXCEPTION(0xa00, APU, UnknownException)
547 #endif
548 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
549
550 #ifdef CONFIG_440
551 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
552 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
553 #else
554 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
555 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
556 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
557 #endif
558 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
559
560 .globl _end_of_vectors
561 _end_of_vectors:
562 . = _START_OFFSET
563 #endif
564 .globl _start
565 _start:
566
567 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
568 /*
569 * This is the entry of the real U-Boot from a board port
570 * that supports SPL booting on the PPC4xx. We only need
571 * to call board_init_f() here. Everything else has already
572 * been done in the SPL u-boot version.
573 */
574 GET_GOT /* initialize GOT access */
575 bl board_init_f /* run 1st part of board init code (in Flash)*/
576 /* NOTREACHED - board_init_f() does not return */
577 #endif
578
579 /*****************************************************************************/
580 #if defined(CONFIG_440)
581
582 /*----------------------------------------------------------------*/
583 /* Clear and set up some registers. */
584 /*----------------------------------------------------------------*/
585 li r0,0x0000
586 lis r1,0xffff
587 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
588 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
589 mtspr SPRN_TBWU,r0
590 mtspr SPRN_TSR,r1 /* clear all timer exception status */
591 mtspr SPRN_TCR,r0 /* disable all */
592 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
593 mtxer r0 /* clear integer exception register */
594
595 /*----------------------------------------------------------------*/
596 /* Debug setup -- some (not very good) ice's need an event*/
597 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
598 /* value you need in this case 0x8cff 0000 should do the trick */
599 /*----------------------------------------------------------------*/
600 #if defined(CONFIG_SYS_INIT_DBCR)
601 lis r1,0xffff
602 ori r1,r1,0xffff
603 mtspr SPRN_DBSR,r1 /* Clear all status bits */
604 lis r0,CONFIG_SYS_INIT_DBCR@h
605 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
606 mtspr SPRN_DBCR0,r0
607 isync
608 #endif
609
610 /*----------------------------------------------------------------*/
611 /* Setup the internal SRAM */
612 /*----------------------------------------------------------------*/
613 li r0,0
614
615 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
616 /* Clear Dcache to use as RAM */
617 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
618 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
619 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
620 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
621 rlwinm. r5,r4,0,27,31
622 rlwinm r5,r4,27,5,31
623 beq ..d_ran
624 addi r5,r5,0x0001
625 ..d_ran:
626 mtctr r5
627 ..d_ag:
628 dcbz r0,r3
629 addi r3,r3,32
630 bdnz ..d_ag
631
632 /*
633 * Lock the init-ram/stack in d-cache, so that other regions
634 * may use d-cache as well
635 * Note, that this current implementation locks exactly 4k
636 * of d-cache, so please make sure that you don't define a
637 * bigger init-ram area. Take a look at the lwmon5 440EPx
638 * implementation as a reference.
639 */
640 msync
641 isync
642 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
643 lis r1,0x0201
644 ori r1,r1,0xf808
645 mtspr SPRN_DVLIM,r1
646 lis r1,0x0808
647 ori r1,r1,0x0808
648 mtspr SPRN_DNV0,r1
649 mtspr SPRN_DNV1,r1
650 mtspr SPRN_DNV2,r1
651 mtspr SPRN_DNV3,r1
652 mtspr SPRN_DTV0,r1
653 mtspr SPRN_DTV1,r1
654 mtspr SPRN_DTV2,r1
655 mtspr SPRN_DTV3,r1
656 msync
657 isync
658 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
659
660 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
661 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
662 /* not all PPC's have internal SRAM usable as L2-cache */
663 #if defined(CONFIG_440GX) || \
664 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
665 defined(CONFIG_460SX)
666 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
667 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
668 defined(CONFIG_APM821XX)
669 lis r1, 0x0000
670 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
671 mtdcr L2_CACHE_CFG,r1
672 #endif
673
674 lis r2,0x7fff
675 ori r2,r2,0xffff
676 mfdcr r1,ISRAM0_DPC
677 and r1,r1,r2 /* Disable parity check */
678 mtdcr ISRAM0_DPC,r1
679 mfdcr r1,ISRAM0_PMEG
680 and r1,r1,r2 /* Disable pwr mgmt */
681 mtdcr ISRAM0_PMEG,r1
682
683 lis r1,0x8000 /* BAS = 8000_0000 */
684 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
685 ori r1,r1,0x0980 /* first 64k */
686 mtdcr ISRAM0_SB0CR,r1
687 lis r1,0x8001
688 ori r1,r1,0x0980 /* second 64k */
689 mtdcr ISRAM0_SB1CR,r1
690 lis r1, 0x8002
691 ori r1,r1, 0x0980 /* third 64k */
692 mtdcr ISRAM0_SB2CR,r1
693 lis r1, 0x8003
694 ori r1,r1, 0x0980 /* fourth 64k */
695 mtdcr ISRAM0_SB3CR,r1
696 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
697 defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
698 lis r1,0x0000 /* BAS = X_0000_0000 */
699 ori r1,r1,0x0984 /* first 64k */
700 mtdcr ISRAM0_SB0CR,r1
701 lis r1,0x0001
702 ori r1,r1,0x0984 /* second 64k */
703 mtdcr ISRAM0_SB1CR,r1
704 lis r1, 0x0002
705 ori r1,r1, 0x0984 /* third 64k */
706 mtdcr ISRAM0_SB2CR,r1
707 lis r1, 0x0003
708 ori r1,r1, 0x0984 /* fourth 64k */
709 mtdcr ISRAM0_SB3CR,r1
710 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
711 defined(CONFIG_APM821XX)
712 lis r2,0x7fff
713 ori r2,r2,0xffff
714 mfdcr r1,ISRAM1_DPC
715 and r1,r1,r2 /* Disable parity check */
716 mtdcr ISRAM1_DPC,r1
717 mfdcr r1,ISRAM1_PMEG
718 and r1,r1,r2 /* Disable pwr mgmt */
719 mtdcr ISRAM1_PMEG,r1
720
721 lis r1,0x0004 /* BAS = 4_0004_0000 */
722 ori r1,r1,ISRAM1_SIZE /* ocm size */
723 mtdcr ISRAM1_SB0CR,r1
724 #endif
725 #elif defined(CONFIG_460SX)
726 lis r1,0x0000 /* BAS = 0000_0000 */
727 ori r1,r1,0x0B84 /* first 128k */
728 mtdcr ISRAM0_SB0CR,r1
729 lis r1,0x0001
730 ori r1,r1,0x0B84 /* second 128k */
731 mtdcr ISRAM0_SB1CR,r1
732 lis r1, 0x0002
733 ori r1,r1, 0x0B84 /* third 128k */
734 mtdcr ISRAM0_SB2CR,r1
735 lis r1, 0x0003
736 ori r1,r1, 0x0B84 /* fourth 128k */
737 mtdcr ISRAM0_SB3CR,r1
738 #elif defined(CONFIG_440GP)
739 ori r1,r1,0x0380 /* 8k rw */
740 mtdcr ISRAM0_SB0CR,r1
741 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
742 #endif
743 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
744
745 /*----------------------------------------------------------------*/
746 /* Setup the stack in internal SRAM */
747 /*----------------------------------------------------------------*/
748 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
749 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
750 li r0,0
751 stwu r0,-4(r1)
752 stwu r0,-4(r1) /* Terminate call chain */
753
754 stwu r1,-8(r1) /* Save back chain and move SP */
755 lis r0,RESET_VECTOR@h /* Address of reset vector */
756 ori r0,r0, RESET_VECTOR@l
757 stwu r1,-8(r1) /* Save back chain and move SP */
758 stw r0,+12(r1) /* Save return addr (underflow vect) */
759
760 #ifndef CONFIG_SPL_BUILD
761 GET_GOT
762 #endif
763
764 bl cpu_init_f /* run low-level CPU init code (from Flash) */
765 bl board_init_f
766 /* NOTREACHED - board_init_f() does not return */
767
768 #endif /* CONFIG_440 */
769
770 /*****************************************************************************/
771 #if defined(CONFIG_405GP) || \
772 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
773 defined(CONFIG_405EX) || defined(CONFIG_405)
774 /*----------------------------------------------------------------------- */
775 /* Clear and set up some registers. */
776 /*----------------------------------------------------------------------- */
777 addi r4,r0,0x0000
778 #if !defined(CONFIG_405EX)
779 mtspr SPRN_SGR,r4
780 #else
781 /*
782 * On 405EX, completely clearing the SGR leads to PPC hangup
783 * upon PCIe configuration access. The PCIe memory regions
784 * need to be guarded!
785 */
786 lis r3,0x0000
787 ori r3,r3,0x7FFC
788 mtspr SPRN_SGR,r3
789 #endif
790 mtspr SPRN_DCWR,r4
791 mtesr r4 /* clear Exception Syndrome Reg */
792 mttcr r4 /* clear Timer Control Reg */
793 mtxer r4 /* clear Fixed-Point Exception Reg */
794 mtevpr r4 /* clear Exception Vector Prefix Reg */
795 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
796 /* dbsr is cleared by setting bits to 1) */
797 mtdbsr r4 /* clear/reset the dbsr */
798
799 /* Invalidate the i- and d-caches. */
800 bl invalidate_icache
801 bl invalidate_dcache
802
803 /* Set-up icache cacheability. */
804 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
805 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
806 mticcr r4
807 isync
808
809 /* Set-up dcache cacheability. */
810 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
811 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
812 mtdccr r4
813
814 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
815 && !defined (CONFIG_XILINX_405)
816 /*----------------------------------------------------------------------- */
817 /* Tune the speed and size for flash CS0 */
818 /*----------------------------------------------------------------------- */
819 bl ext_bus_cntlr_init
820 #endif
821
822 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
823 /*
824 * For boards that don't have OCM and can't use the data cache
825 * for their primordial stack, setup stack here directly after the
826 * SDRAM is initialized in ext_bus_cntlr_init.
827 */
828 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
829 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
830
831 li r0, 0 /* Make room for stack frame header and */
832 stwu r0, -4(r1) /* clear final stack frame so that */
833 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
834 /*
835 * Set up a dummy frame to store reset vector as return address.
836 * this causes stack underflow to reset board.
837 */
838 stwu r1, -8(r1) /* Save back chain and move SP */
839 lis r0, RESET_VECTOR@h /* Address of reset vector */
840 ori r0, r0, RESET_VECTOR@l
841 stwu r1, -8(r1) /* Save back chain and move SP */
842 stw r0, +12(r1) /* Save return addr (underflow vect) */
843 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
844
845 #if defined(CONFIG_405EP)
846 /*----------------------------------------------------------------------- */
847 /* DMA Status, clear to come up clean */
848 /*----------------------------------------------------------------------- */
849 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
850 ori r3,r3, 0xFFFF
851 mtdcr DMASR, r3
852
853 bl ppc405ep_init /* do ppc405ep specific init */
854 #endif /* CONFIG_405EP */
855
856 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
857 #if defined(CONFIG_405EZ)
858 /********************************************************************
859 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
860 *******************************************************************/
861 /*
862 * We can map the OCM on the PLB3, so map it at
863 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
864 */
865 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
866 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
867 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
868 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
869 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
870 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
871 isync
872
873 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
874 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
875 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
876 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
877 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
878 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
879 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
880 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
881 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
882 mtdcr OCM0_DISDPC,r3
883
884 isync
885 #else /* CONFIG_405EZ */
886 /********************************************************************
887 * Setup OCM - On Chip Memory
888 *******************************************************************/
889 /* Setup OCM */
890 lis r0, 0x7FFF
891 ori r0, r0, 0xFFFF
892 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
893 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
894 and r3, r3, r0 /* disable data-side IRAM */
895 and r4, r4, r0 /* disable data-side IRAM */
896 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
897 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
898 isync
899
900 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
901 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
902 mtdcr OCM0_DSARC, r3
903 addis r4, 0, 0xC000 /* OCM data area enabled */
904 mtdcr OCM0_DSCNTL, r4
905 isync
906 #endif /* CONFIG_405EZ */
907 #endif
908
909 /*----------------------------------------------------------------------- */
910 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
911 /*----------------------------------------------------------------------- */
912 #ifdef CONFIG_SYS_INIT_DCACHE_CS
913 li r4, PBxAP
914 mtdcr EBC0_CFGADDR, r4
915 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
916 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
917 mtdcr EBC0_CFGDATA, r4
918
919 addi r4, 0, PBxCR
920 mtdcr EBC0_CFGADDR, r4
921 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
922 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
923 mtdcr EBC0_CFGDATA, r4
924
925 /*
926 * Enable the data cache for the 128MB storage access control region
927 * at CONFIG_SYS_INIT_RAM_ADDR.
928 */
929 mfdccr r4
930 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
931 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
932 mtdccr r4
933
934 /*
935 * Preallocate data cache lines to be used to avoid a subsequent
936 * cache miss and an ensuing machine check exception when exceptions
937 * are enabled.
938 */
939 li r0, 0
940
941 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
942 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
943
944 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
945 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
946
947 /*
948 * Convert the size, in bytes, to the number of cache lines/blocks
949 * to preallocate.
950 */
951 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
952 srwi r5, r4, L1_CACHE_SHIFT
953 beq ..load_counter
954 addi r5, r5, 0x0001
955 ..load_counter:
956 mtctr r5
957
958 /* Preallocate the computed number of cache blocks. */
959 ..alloc_dcache_block:
960 dcba r0, r3
961 addi r3, r3, L1_CACHE_BYTES
962 bdnz ..alloc_dcache_block
963 sync
964
965 /*
966 * Load the initial stack pointer and data area and convert the size,
967 * in bytes, to the number of words to initialize to a known value.
968 */
969 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
970 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
971
972 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
973 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
974 mtctr r4
975
976 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
977 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
978
979 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
980 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
981
982 ..stackloop:
983 stwu r4, -4(r2)
984 bdnz ..stackloop
985
986 /*
987 * Make room for stack frame header and clear final stack frame so
988 * that stack backtraces terminate cleanly.
989 */
990 stwu r0, -4(r1)
991 stwu r0, -4(r1)
992
993 /*
994 * Set up a dummy frame to store reset vector as return address.
995 * this causes stack underflow to reset board.
996 */
997 stwu r1, -8(r1) /* Save back chain and move SP */
998 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
999 ori r0, r0, RESET_VECTOR@l
1000 stwu r1, -8(r1) /* Save back chain and move SP */
1001 stw r0, +12(r1) /* Save return addr (underflow vect) */
1002
1003 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1004 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1005 /*
1006 * Stack in OCM.
1007 */
1008
1009 /* Set up Stack at top of OCM */
1010 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1011 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1012
1013 /* Set up a zeroized stack frame so that backtrace works right */
1014 li r0, 0
1015 stwu r0, -4(r1)
1016 stwu r0, -4(r1)
1017
1018 /*
1019 * Set up a dummy frame to store reset vector as return address.
1020 * this causes stack underflow to reset board.
1021 */
1022 stwu r1, -8(r1) /* Save back chain and move SP */
1023 lis r0, RESET_VECTOR@h /* Address of reset vector */
1024 ori r0, r0, RESET_VECTOR@l
1025 stwu r1, -8(r1) /* Save back chain and move SP */
1026 stw r0, +12(r1) /* Save return addr (underflow vect) */
1027 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1028
1029 GET_GOT /* initialize GOT access */
1030
1031 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1032
1033 bl board_init_f /* run first part of init code (from Flash) */
1034 /* NOTREACHED - board_init_f() does not return */
1035
1036 #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
1037 /*----------------------------------------------------------------------- */
1038
1039
1040 #if !defined(CONFIG_SPL_BUILD)
1041 /*
1042 * This code finishes saving the registers to the exception frame
1043 * and jumps to the appropriate handler for the exception.
1044 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1045 */
1046 .globl transfer_to_handler
1047 transfer_to_handler:
1048 stw r22,_NIP(r21)
1049 lis r22,MSR_POW@h
1050 andc r23,r23,r22
1051 stw r23,_MSR(r21)
1052 SAVE_GPR(7, r21)
1053 SAVE_4GPRS(8, r21)
1054 SAVE_8GPRS(12, r21)
1055 SAVE_8GPRS(24, r21)
1056 mflr r23
1057 andi. r24,r23,0x3f00 /* get vector offset */
1058 stw r24,TRAP(r21)
1059 li r22,0
1060 stw r22,RESULT(r21)
1061 mtspr SPRG2,r22 /* r1 is now kernel sp */
1062 lwz r24,0(r23) /* virtual address of handler */
1063 lwz r23,4(r23) /* where to go when done */
1064 mtspr SRR0,r24
1065 mtspr SRR1,r20
1066 mtlr r23
1067 SYNC
1068 rfi /* jump to handler, enable MMU */
1069
1070 int_return:
1071 mfmsr r28 /* Disable interrupts */
1072 li r4,0
1073 ori r4,r4,MSR_EE
1074 andc r28,r28,r4
1075 SYNC /* Some chip revs need this... */
1076 mtmsr r28
1077 SYNC
1078 lwz r2,_CTR(r1)
1079 lwz r0,_LINK(r1)
1080 mtctr r2
1081 mtlr r0
1082 lwz r2,_XER(r1)
1083 lwz r0,_CCR(r1)
1084 mtspr XER,r2
1085 mtcrf 0xFF,r0
1086 REST_10GPRS(3, r1)
1087 REST_10GPRS(13, r1)
1088 REST_8GPRS(23, r1)
1089 REST_GPR(31, r1)
1090 lwz r2,_NIP(r1) /* Restore environment */
1091 lwz r0,_MSR(r1)
1092 mtspr SRR0,r2
1093 mtspr SRR1,r0
1094 lwz r0,GPR0(r1)
1095 lwz r2,GPR2(r1)
1096 lwz r1,GPR1(r1)
1097 SYNC
1098 rfi
1099
1100 crit_return:
1101 mfmsr r28 /* Disable interrupts */
1102 li r4,0
1103 ori r4,r4,MSR_EE
1104 andc r28,r28,r4
1105 SYNC /* Some chip revs need this... */
1106 mtmsr r28
1107 SYNC
1108 lwz r2,_CTR(r1)
1109 lwz r0,_LINK(r1)
1110 mtctr r2
1111 mtlr r0
1112 lwz r2,_XER(r1)
1113 lwz r0,_CCR(r1)
1114 mtspr XER,r2
1115 mtcrf 0xFF,r0
1116 REST_10GPRS(3, r1)
1117 REST_10GPRS(13, r1)
1118 REST_8GPRS(23, r1)
1119 REST_GPR(31, r1)
1120 lwz r2,_NIP(r1) /* Restore environment */
1121 lwz r0,_MSR(r1)
1122 mtspr SPRN_CSRR0,r2
1123 mtspr SPRN_CSRR1,r0
1124 lwz r0,GPR0(r1)
1125 lwz r2,GPR2(r1)
1126 lwz r1,GPR1(r1)
1127 SYNC
1128 rfci
1129
1130 #ifdef CONFIG_440
1131 mck_return:
1132 mfmsr r28 /* Disable interrupts */
1133 li r4,0
1134 ori r4,r4,MSR_EE
1135 andc r28,r28,r4
1136 SYNC /* Some chip revs need this... */
1137 mtmsr r28
1138 SYNC
1139 lwz r2,_CTR(r1)
1140 lwz r0,_LINK(r1)
1141 mtctr r2
1142 mtlr r0
1143 lwz r2,_XER(r1)
1144 lwz r0,_CCR(r1)
1145 mtspr XER,r2
1146 mtcrf 0xFF,r0
1147 REST_10GPRS(3, r1)
1148 REST_10GPRS(13, r1)
1149 REST_8GPRS(23, r1)
1150 REST_GPR(31, r1)
1151 lwz r2,_NIP(r1) /* Restore environment */
1152 lwz r0,_MSR(r1)
1153 mtspr SPRN_MCSRR0,r2
1154 mtspr SPRN_MCSRR1,r0
1155 lwz r0,GPR0(r1)
1156 lwz r2,GPR2(r1)
1157 lwz r1,GPR1(r1)
1158 SYNC
1159 rfmci
1160 #endif /* CONFIG_440 */
1161
1162
1163 .globl get_pvr
1164 get_pvr:
1165 mfspr r3, PVR
1166 blr
1167
1168 /*------------------------------------------------------------------------------- */
1169 /* Function: out16 */
1170 /* Description: Output 16 bits */
1171 /*------------------------------------------------------------------------------- */
1172 .globl out16
1173 out16:
1174 sth r4,0x0000(r3)
1175 blr
1176
1177 /*------------------------------------------------------------------------------- */
1178 /* Function: out16r */
1179 /* Description: Byte reverse and output 16 bits */
1180 /*------------------------------------------------------------------------------- */
1181 .globl out16r
1182 out16r:
1183 sthbrx r4,r0,r3
1184 blr
1185
1186 /*------------------------------------------------------------------------------- */
1187 /* Function: out32r */
1188 /* Description: Byte reverse and output 32 bits */
1189 /*------------------------------------------------------------------------------- */
1190 .globl out32r
1191 out32r:
1192 stwbrx r4,r0,r3
1193 blr
1194
1195 /*------------------------------------------------------------------------------- */
1196 /* Function: in16 */
1197 /* Description: Input 16 bits */
1198 /*------------------------------------------------------------------------------- */
1199 .globl in16
1200 in16:
1201 lhz r3,0x0000(r3)
1202 blr
1203
1204 /*------------------------------------------------------------------------------- */
1205 /* Function: in16r */
1206 /* Description: Input 16 bits and byte reverse */
1207 /*------------------------------------------------------------------------------- */
1208 .globl in16r
1209 in16r:
1210 lhbrx r3,r0,r3
1211 blr
1212
1213 /*------------------------------------------------------------------------------- */
1214 /* Function: in32r */
1215 /* Description: Input 32 bits and byte reverse */
1216 /*------------------------------------------------------------------------------- */
1217 .globl in32r
1218 in32r:
1219 lwbrx r3,r0,r3
1220 blr
1221
1222 #if !defined(CONFIG_SPL_BUILD)
1223 /*
1224 * void relocate_code (addr_sp, gd, addr_moni)
1225 *
1226 * This "function" does not return, instead it continues in RAM
1227 * after relocating the monitor code.
1228 *
1229 * r3 = Relocated stack pointer
1230 * r4 = Relocated global data pointer
1231 * r5 = Relocated text pointer
1232 */
1233 .globl relocate_code
1234 relocate_code:
1235 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1236 /*
1237 * We need to flush the initial global data (gd_t) and bd_info
1238 * before the dcache will be invalidated.
1239 */
1240
1241 /* Save registers */
1242 mr r9, r3
1243 mr r10, r4
1244 mr r11, r5
1245
1246 /*
1247 * Flush complete dcache, this is faster than flushing the
1248 * ranges for global_data and bd_info instead.
1249 */
1250 bl flush_dcache
1251
1252 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1253 /*
1254 * Undo the earlier data cache set-up for the primordial stack and
1255 * data area. First, invalidate the data cache and then disable data
1256 * cacheability for that area. Finally, restore the EBC values, if
1257 * any.
1258 */
1259
1260 /* Invalidate the primordial stack and data area in cache */
1261 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1262 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1263
1264 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1265 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1266 add r4, r4, r3
1267
1268 bl invalidate_dcache_range
1269
1270 /* Disable cacheability for the region */
1271 mfdccr r3
1272 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1273 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1274 and r3, r3, r4
1275 mtdccr r3
1276
1277 /* Restore the EBC parameters */
1278 li r3, PBxAP
1279 mtdcr EBC0_CFGADDR, r3
1280 lis r3, PBxAP_VAL@h
1281 ori r3, r3, PBxAP_VAL@l
1282 mtdcr EBC0_CFGDATA, r3
1283
1284 li r3, PBxCR
1285 mtdcr EBC0_CFGADDR, r3
1286 lis r3, PBxCR_VAL@h
1287 ori r3, r3, PBxCR_VAL@l
1288 mtdcr EBC0_CFGDATA, r3
1289 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1290
1291 /* Restore registers */
1292 mr r3, r9
1293 mr r4, r10
1294 mr r5, r11
1295 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1296
1297 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1298 /*
1299 * Unlock the previously locked d-cache
1300 */
1301 msync
1302 isync
1303 /* set TFLOOR/NFLOOR to 0 again */
1304 lis r6,0x0001
1305 ori r6,r6,0xf800
1306 mtspr SPRN_DVLIM,r6
1307 lis r6,0x0000
1308 ori r6,r6,0x0000
1309 mtspr SPRN_DNV0,r6
1310 mtspr SPRN_DNV1,r6
1311 mtspr SPRN_DNV2,r6
1312 mtspr SPRN_DNV3,r6
1313 mtspr SPRN_DTV0,r6
1314 mtspr SPRN_DTV1,r6
1315 mtspr SPRN_DTV2,r6
1316 mtspr SPRN_DTV3,r6
1317 msync
1318 isync
1319
1320 /* Invalidate data cache, now no longer our stack */
1321 dccci 0,0
1322 sync
1323 isync
1324 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1325
1326 /*
1327 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1328 * to speed up the boot process. Now this cache needs to be disabled.
1329 */
1330 #if defined(CONFIG_440)
1331 /* Clear all potential pending exceptions */
1332 mfspr r1,SPRN_MCSR
1333 mtspr SPRN_MCSR,r1
1334 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1335 tlbre r0,r1,0x0002 /* Read contents */
1336 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1337 tlbwe r0,r1,0x0002 /* Save it out */
1338 sync
1339 isync
1340 #endif /* defined(CONFIG_440) */
1341 mr r1, r3 /* Set new stack pointer */
1342 mr r9, r4 /* Save copy of Init Data pointer */
1343 mr r10, r5 /* Save copy of Destination Address */
1344
1345 GET_GOT
1346 mr r3, r5 /* Destination Address */
1347 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1348 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1349 lwz r5, GOT(__init_end)
1350 sub r5, r5, r4
1351 li r6, L1_CACHE_BYTES /* Cache Line Size */
1352
1353 /*
1354 * Fix GOT pointer:
1355 *
1356 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1357 *
1358 * Offset:
1359 */
1360 sub r15, r10, r4
1361
1362 /* First our own GOT */
1363 add r12, r12, r15
1364 /* then the one used by the C code */
1365 add r30, r30, r15
1366
1367 /*
1368 * Now relocate code
1369 */
1370
1371 cmplw cr1,r3,r4
1372 addi r0,r5,3
1373 srwi. r0,r0,2
1374 beq cr1,4f /* In place copy is not necessary */
1375 beq 7f /* Protect against 0 count */
1376 mtctr r0
1377 bge cr1,2f
1378
1379 la r8,-4(r4)
1380 la r7,-4(r3)
1381 1: lwzu r0,4(r8)
1382 stwu r0,4(r7)
1383 bdnz 1b
1384 b 4f
1385
1386 2: slwi r0,r0,2
1387 add r8,r4,r0
1388 add r7,r3,r0
1389 3: lwzu r0,-4(r8)
1390 stwu r0,-4(r7)
1391 bdnz 3b
1392
1393 /*
1394 * Now flush the cache: note that we must start from a cache aligned
1395 * address. Otherwise we might miss one cache line.
1396 */
1397 4: cmpwi r6,0
1398 add r5,r3,r5
1399 beq 7f /* Always flush prefetch queue in any case */
1400 subi r0,r6,1
1401 andc r3,r3,r0
1402 mr r4,r3
1403 5: dcbst 0,r4
1404 add r4,r4,r6
1405 cmplw r4,r5
1406 blt 5b
1407 sync /* Wait for all dcbst to complete on bus */
1408 mr r4,r3
1409 6: icbi 0,r4
1410 add r4,r4,r6
1411 cmplw r4,r5
1412 blt 6b
1413 7: sync /* Wait for all icbi to complete on bus */
1414 isync
1415
1416 /*
1417 * We are done. Do not return, instead branch to second part of board
1418 * initialization, now running from RAM.
1419 */
1420
1421 addi r0, r10, in_ram - _start + _START_OFFSET
1422 mtlr r0
1423 blr /* NEVER RETURNS! */
1424
1425 in_ram:
1426
1427 /*
1428 * Relocation Function, r12 point to got2+0x8000
1429 *
1430 * Adjust got2 pointers, no need to check for 0, this code
1431 * already puts a few entries in the table.
1432 */
1433 li r0,__got2_entries@sectoff@l
1434 la r3,GOT(_GOT2_TABLE_)
1435 lwz r11,GOT(_GOT2_TABLE_)
1436 mtctr r0
1437 sub r11,r3,r11
1438 addi r3,r3,-4
1439 1: lwzu r0,4(r3)
1440 cmpwi r0,0
1441 beq- 2f
1442 add r0,r0,r11
1443 stw r0,0(r3)
1444 2: bdnz 1b
1445
1446 /*
1447 * Now adjust the fixups and the pointers to the fixups
1448 * in case we need to move ourselves again.
1449 */
1450 li r0,__fixup_entries@sectoff@l
1451 lwz r3,GOT(_FIXUP_TABLE_)
1452 cmpwi r0,0
1453 mtctr r0
1454 addi r3,r3,-4
1455 beq 4f
1456 3: lwzu r4,4(r3)
1457 lwzux r0,r4,r11
1458 cmpwi r0,0
1459 add r0,r0,r11
1460 stw r4,0(r3)
1461 beq- 5f
1462 stw r0,0(r4)
1463 5: bdnz 3b
1464 4:
1465 clear_bss:
1466 /*
1467 * Now clear BSS segment
1468 */
1469 lwz r3,GOT(__bss_start)
1470 lwz r4,GOT(__bss_end)
1471
1472 cmplw 0, r3, r4
1473 beq 7f
1474
1475 li r0, 0
1476
1477 andi. r5, r4, 3
1478 beq 6f
1479 sub r4, r4, r5
1480 mtctr r5
1481 mr r5, r4
1482 5: stb r0, 0(r5)
1483 addi r5, r5, 1
1484 bdnz 5b
1485 6:
1486 stw r0, 0(r3)
1487 addi r3, r3, 4
1488 cmplw 0, r3, r4
1489 bne 6b
1490
1491 7:
1492 mr r3, r9 /* Init Data pointer */
1493 mr r4, r10 /* Destination Address */
1494 bl board_init_r
1495
1496 /*
1497 * Copy exception vector code to low memory
1498 *
1499 * r3: dest_addr
1500 * r7: source address, r8: end address, r9: target address
1501 */
1502 .globl trap_init
1503 trap_init:
1504 mflr r4 /* save link register */
1505 GET_GOT
1506 lwz r7, GOT(_start_of_vectors)
1507 lwz r8, GOT(_end_of_vectors)
1508
1509 li r9, 0x100 /* reset vector always at 0x100 */
1510
1511 cmplw 0, r7, r8
1512 bgelr /* return if r7>=r8 - just in case */
1513 1:
1514 lwz r0, 0(r7)
1515 stw r0, 0(r9)
1516 addi r7, r7, 4
1517 addi r9, r9, 4
1518 cmplw 0, r7, r8
1519 bne 1b
1520
1521 /*
1522 * relocate `hdlr' and `int_return' entries
1523 */
1524 li r7, .L_MachineCheck - _start + _START_OFFSET
1525 li r8, Alignment - _start + _START_OFFSET
1526 2:
1527 bl trap_reloc
1528 addi r7, r7, 0x100 /* next exception vector */
1529 cmplw 0, r7, r8
1530 blt 2b
1531
1532 li r7, .L_Alignment - _start + _START_OFFSET
1533 bl trap_reloc
1534
1535 li r7, .L_ProgramCheck - _start + _START_OFFSET
1536 bl trap_reloc
1537
1538 #ifdef CONFIG_440
1539 li r7, .L_FPUnavailable - _start + _START_OFFSET
1540 bl trap_reloc
1541
1542 li r7, .L_Decrementer - _start + _START_OFFSET
1543 bl trap_reloc
1544
1545 li r7, .L_APU - _start + _START_OFFSET
1546 bl trap_reloc
1547
1548 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1549 bl trap_reloc
1550
1551 li r7, .L_DataTLBError - _start + _START_OFFSET
1552 bl trap_reloc
1553 #else /* CONFIG_440 */
1554 li r7, .L_PIT - _start + _START_OFFSET
1555 bl trap_reloc
1556
1557 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1558 bl trap_reloc
1559
1560 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1561 bl trap_reloc
1562 #endif /* CONFIG_440 */
1563
1564 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1565 bl trap_reloc
1566
1567 #if !defined(CONFIG_440)
1568 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1569 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1570 mtmsr r7 /* change MSR */
1571 #else
1572 bl __440_msr_set
1573 b __440_msr_continue
1574
1575 __440_msr_set:
1576 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1577 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1578 mtspr SPRN_SRR1,r7
1579 mflr r7
1580 mtspr SPRN_SRR0,r7
1581 rfi
1582 __440_msr_continue:
1583 #endif
1584
1585 mtlr r4 /* restore link register */
1586 blr
1587 #endif /* CONFIG_SPL_BUILD */
1588
1589 #if defined(CONFIG_440)
1590 /*----------------------------------------------------------------------------+
1591 | dcbz_area.
1592 +----------------------------------------------------------------------------*/
1593 function_prolog(dcbz_area)
1594 rlwinm. r5,r4,0,27,31
1595 rlwinm r5,r4,27,5,31
1596 beq ..d_ra2
1597 addi r5,r5,0x0001
1598 ..d_ra2:mtctr r5
1599 ..d_ag2:dcbz r0,r3
1600 addi r3,r3,32
1601 bdnz ..d_ag2
1602 sync
1603 blr
1604 function_epilog(dcbz_area)
1605 #endif /* CONFIG_440 */
1606 #endif /* CONFIG_SPL_BUILD */
1607
1608 /*------------------------------------------------------------------------------- */
1609 /* Function: in8 */
1610 /* Description: Input 8 bits */
1611 /*------------------------------------------------------------------------------- */
1612 .globl in8
1613 in8:
1614 lbz r3,0x0000(r3)
1615 blr
1616
1617 /*------------------------------------------------------------------------------- */
1618 /* Function: out8 */
1619 /* Description: Output 8 bits */
1620 /*------------------------------------------------------------------------------- */
1621 .globl out8
1622 out8:
1623 stb r4,0x0000(r3)
1624 blr
1625
1626 /*------------------------------------------------------------------------------- */
1627 /* Function: out32 */
1628 /* Description: Output 32 bits */
1629 /*------------------------------------------------------------------------------- */
1630 .globl out32
1631 out32:
1632 stw r4,0x0000(r3)
1633 blr
1634
1635 /*------------------------------------------------------------------------------- */
1636 /* Function: in32 */
1637 /* Description: Input 32 bits */
1638 /*------------------------------------------------------------------------------- */
1639 .globl in32
1640 in32:
1641 lwz 3,0x0000(3)
1642 blr
1643
1644 /**************************************************************************/
1645 /* PPC405EP specific stuff */
1646 /**************************************************************************/
1647 #ifdef CONFIG_405EP
1648 ppc405ep_init:
1649
1650 #ifdef CONFIG_BUBINGA
1651 /*
1652 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1653 * function) to support FPGA and NVRAM accesses below.
1654 */
1655
1656 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1657 ori r3,r3,GPIO0_OSRH@l
1658 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1659 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1660 stw r4,0(r3)
1661 lis r3,GPIO0_OSRL@h
1662 ori r3,r3,GPIO0_OSRL@l
1663 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1664 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1665 stw r4,0(r3)
1666
1667 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1668 ori r3,r3,GPIO0_ISR1H@l
1669 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1670 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1671 stw r4,0(r3)
1672 lis r3,GPIO0_ISR1L@h
1673 ori r3,r3,GPIO0_ISR1L@l
1674 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1675 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1676 stw r4,0(r3)
1677
1678 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1679 ori r3,r3,GPIO0_TSRH@l
1680 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1681 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1682 stw r4,0(r3)
1683 lis r3,GPIO0_TSRL@h
1684 ori r3,r3,GPIO0_TSRL@l
1685 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1686 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1687 stw r4,0(r3)
1688
1689 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1690 ori r3,r3,GPIO0_TCR@l
1691 lis r4,CONFIG_SYS_GPIO0_TCR@h
1692 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1693 stw r4,0(r3)
1694
1695 li r3,PB1AP /* program EBC bank 1 for RTC access */
1696 mtdcr EBC0_CFGADDR,r3
1697 lis r3,CONFIG_SYS_EBC_PB1AP@h
1698 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1699 mtdcr EBC0_CFGDATA,r3
1700 li r3,PB1CR
1701 mtdcr EBC0_CFGADDR,r3
1702 lis r3,CONFIG_SYS_EBC_PB1CR@h
1703 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1704 mtdcr EBC0_CFGDATA,r3
1705
1706 li r3,PB1AP /* program EBC bank 1 for RTC access */
1707 mtdcr EBC0_CFGADDR,r3
1708 lis r3,CONFIG_SYS_EBC_PB1AP@h
1709 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1710 mtdcr EBC0_CFGDATA,r3
1711 li r3,PB1CR
1712 mtdcr EBC0_CFGADDR,r3
1713 lis r3,CONFIG_SYS_EBC_PB1CR@h
1714 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1715 mtdcr EBC0_CFGDATA,r3
1716
1717 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1718 mtdcr EBC0_CFGADDR,r3
1719 lis r3,CONFIG_SYS_EBC_PB4AP@h
1720 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1721 mtdcr EBC0_CFGDATA,r3
1722 li r3,PB4CR
1723 mtdcr EBC0_CFGADDR,r3
1724 lis r3,CONFIG_SYS_EBC_PB4CR@h
1725 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1726 mtdcr EBC0_CFGDATA,r3
1727 #endif
1728
1729 /*
1730 !-----------------------------------------------------------------------
1731 ! Check to see if chip is in bypass mode.
1732 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1733 ! CPU reset Otherwise, skip this step and keep going.
1734 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1735 ! will not be fast enough for the SDRAM (min 66MHz)
1736 !-----------------------------------------------------------------------
1737 */
1738 mfdcr r5, CPC0_PLLMR1
1739 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1740 cmpi cr0,0,r4,0x1
1741
1742 beq pll_done /* if SSCS =b'1' then PLL has */
1743 /* already been set */
1744 /* and CPU has been reset */
1745 /* so skip to next section */
1746
1747 #ifdef CONFIG_BUBINGA
1748 /*
1749 !-----------------------------------------------------------------------
1750 ! Read NVRAM to get value to write in PLLMR.
1751 ! If value has not been correctly saved, write default value
1752 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1753 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1754 !
1755 ! WARNING: This code assumes the first three words in the nvram_t
1756 ! structure in openbios.h. Changing the beginning of
1757 ! the structure will break this code.
1758 !
1759 !-----------------------------------------------------------------------
1760 */
1761 addis r3,0,NVRAM_BASE@h
1762 addi r3,r3,NVRAM_BASE@l
1763
1764 lwz r4, 0(r3)
1765 addis r5,0,NVRVFY1@h
1766 addi r5,r5,NVRVFY1@l
1767 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1768 bne ..no_pllset
1769 addi r3,r3,4
1770 lwz r4, 0(r3)
1771 addis r5,0,NVRVFY2@h
1772 addi r5,r5,NVRVFY2@l
1773 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1774 bne ..no_pllset
1775 addi r3,r3,8 /* Skip over conf_size */
1776 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1777 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1778 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1779 cmpi cr0,0,r5,1 /* See if PLL is locked */
1780 beq pll_write
1781 ..no_pllset:
1782 #endif /* CONFIG_BUBINGA */
1783
1784 #ifdef CONFIG_TAIHU
1785 mfdcr r4, CPC0_BOOT
1786 andi. r5, r4, CPC0_BOOT_SEP@l
1787 bne strap_1 /* serial eeprom present */
1788 addis r5,0,CPLD_REG0_ADDR@h
1789 ori r5,r5,CPLD_REG0_ADDR@l
1790 andi. r5, r5, 0x10
1791 bne _pci_66mhz
1792 #endif /* CONFIG_TAIHU */
1793
1794 #if defined(CONFIG_ZEUS)
1795 mfdcr r4, CPC0_BOOT
1796 andi. r5, r4, CPC0_BOOT_SEP@l
1797 bne strap_1 /* serial eeprom present */
1798 lis r3,0x0000
1799 addi r3,r3,0x3030
1800 lis r4,0x8042
1801 addi r4,r4,0x223e
1802 b 1f
1803 strap_1:
1804 mfdcr r3, CPC0_PLLMR0
1805 mfdcr r4, CPC0_PLLMR1
1806 b 1f
1807 #endif
1808
1809 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1810 ori r3,r3,PLLMR0_DEFAULT@l /* */
1811 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1812 ori r4,r4,PLLMR1_DEFAULT@l /* */
1813
1814 #ifdef CONFIG_TAIHU
1815 b 1f
1816 _pci_66mhz:
1817 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1818 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1819 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1820 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1821 b 1f
1822 strap_1:
1823 mfdcr r3, CPC0_PLLMR0
1824 mfdcr r4, CPC0_PLLMR1
1825 #endif /* CONFIG_TAIHU */
1826
1827 1:
1828 b pll_write /* Write the CPC0_PLLMR with new value */
1829
1830 pll_done:
1831 /*
1832 !-----------------------------------------------------------------------
1833 ! Clear Soft Reset Register
1834 ! This is needed to enable PCI if not booting from serial EPROM
1835 !-----------------------------------------------------------------------
1836 */
1837 addi r3, 0, 0x0
1838 mtdcr CPC0_SRR, r3
1839
1840 addis r3,0,0x0010
1841 mtctr r3
1842 pci_wait:
1843 bdnz pci_wait
1844
1845 blr /* return to main code */
1846
1847 /*
1848 !-----------------------------------------------------------------------------
1849 ! Function: pll_write
1850 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1851 ! That is:
1852 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1853 ! 2. PLL is reset
1854 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1855 ! 4. PLL Reset is cleared
1856 ! 5. Wait 100us for PLL to lock
1857 ! 6. A core reset is performed
1858 ! Input: r3 = Value to write to CPC0_PLLMR0
1859 ! Input: r4 = Value to write to CPC0_PLLMR1
1860 ! Output r3 = none
1861 !-----------------------------------------------------------------------------
1862 */
1863 .globl pll_write
1864 pll_write:
1865 mfdcr r5, CPC0_UCR
1866 andis. r5,r5,0xFFFF
1867 ori r5,r5,0x0101 /* Stop the UART clocks */
1868 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1869
1870 mfdcr r5, CPC0_PLLMR1
1871 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1872 mtdcr CPC0_PLLMR1,r5
1873 oris r5,r5,0x4000 /* Set PLL Reset */
1874 mtdcr CPC0_PLLMR1,r5
1875
1876 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1877 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1878 oris r5,r5,0x4000 /* Set PLL Reset */
1879 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1880 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1881 mtdcr CPC0_PLLMR1,r5
1882
1883 /*
1884 ! Wait min of 100us for PLL to lock.
1885 ! See CMOS 27E databook for more info.
1886 ! At 200MHz, that means waiting 20,000 instructions
1887 */
1888 addi r3,0,20000 /* 2000 = 0x4e20 */
1889 mtctr r3
1890 pll_wait:
1891 bdnz pll_wait
1892
1893 oris r5,r5,0x8000 /* Enable PLL */
1894 mtdcr CPC0_PLLMR1,r5 /* Engage */
1895
1896 /*
1897 * Reset CPU to guarantee timings are OK
1898 * Not sure if this is needed...
1899 */
1900 addis r3,0,0x1000
1901 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
1902 /* execution will continue from the poweron */
1903 /* vector of 0xfffffffc */
1904 #endif /* CONFIG_405EP */
1905
1906 #if defined(CONFIG_440)
1907 /*----------------------------------------------------------------------------+
1908 | mttlb3.
1909 +----------------------------------------------------------------------------*/
1910 function_prolog(mttlb3)
1911 TLBWE(4,3,2)
1912 blr
1913 function_epilog(mttlb3)
1914
1915 /*----------------------------------------------------------------------------+
1916 | mftlb3.
1917 +----------------------------------------------------------------------------*/
1918 function_prolog(mftlb3)
1919 TLBRE(3,3,2)
1920 blr
1921 function_epilog(mftlb3)
1922
1923 /*----------------------------------------------------------------------------+
1924 | mttlb2.
1925 +----------------------------------------------------------------------------*/
1926 function_prolog(mttlb2)
1927 TLBWE(4,3,1)
1928 blr
1929 function_epilog(mttlb2)
1930
1931 /*----------------------------------------------------------------------------+
1932 | mftlb2.
1933 +----------------------------------------------------------------------------*/
1934 function_prolog(mftlb2)
1935 TLBRE(3,3,1)
1936 blr
1937 function_epilog(mftlb2)
1938
1939 /*----------------------------------------------------------------------------+
1940 | mttlb1.
1941 +----------------------------------------------------------------------------*/
1942 function_prolog(mttlb1)
1943 TLBWE(4,3,0)
1944 blr
1945 function_epilog(mttlb1)
1946
1947 /*----------------------------------------------------------------------------+
1948 | mftlb1.
1949 +----------------------------------------------------------------------------*/
1950 function_prolog(mftlb1)
1951 TLBRE(3,3,0)
1952 blr
1953 function_epilog(mftlb1)
1954 #endif /* CONFIG_440 */
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