arch/powerpc/cpu/ppc4xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *  Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
   6  *  Copyright (c) 2008 Nuovation System Designs, LLC
   7  *    Grant Erickson <gerickson@nuovations.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 /*------------------------------------------------------------------------------+
  28  *   This source code is dual-licensed.  You may use it under the terms of the
  29  *   GNU General Public License version 2, or under the license below.
  30  *
  31  *       This source code has been made available to you by IBM on an AS-IS
  32  *       basis.  Anyone receiving this source is licensed under IBM
  33  *       copyrights to use it in any way he or she deems fit, including
  34  *       copying it, modifying it, compiling it, and redistributing it either
  35  *       with or without modifications.  No license under IBM patents or
  36  *       patent applications is to be implied by the copyright license.
  37  *
  38  *       Any user of this software should understand that IBM cannot provide
  39  *       technical support for this software and will not be responsible for
  40  *       any consequences resulting from the use of this software.
  41  *
  42  *       Any person who transfers this source code or any derivative work
  43  *       must include the IBM copyright notice, this paragraph, and the
  44  *       preceding two paragraphs in the transferred software.
  45  *
  46  *       COPYRIGHT   I B M   CORPORATION 1995
  47  *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  48  *-------------------------------------------------------------------------------
  49  */
  50
  51 /*
  52  * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
  53  *
  54  * The following description only applies to the NOR flash style booting.
  55  * NAND booting is different. For more details about NAND booting on 4xx
  56  * take a look at doc/README.nand-boot-ppc440.
  57  *
  58  * The CPU starts at address 0xfffffffc (last word in the address space).
  59  * The U-Boot image therefore has to be located in the "upper" area of the
  60  * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
  61  * the boot chip-select (CS0) is quite big and covers this area. On the
  62  * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
  63  * reconfigure this CS0 (and other chip-selects as well when configured
  64  * this way) in the boot process to the "correct" values matching the
  65  * board layout.
  66  */
  67
  68 #include <asm-offsets.h>
  69 #include <config.h>
  70 #include <asm/ppc4xx.h>
  71 #include <version.h>
  72
  73 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  74
  75 #include <ppc_asm.tmpl>
  76 #include <ppc_defs.h>
  77
  78 #include <asm/cache.h>
  79 #include <asm/mmu.h>
  80 #include <asm/ppc4xx-isram.h>
  81
  82 #ifdef CONFIG_SYS_INIT_DCACHE_CS
  83 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
  84 #  define PBxAP PB1AP
  85 #  define PBxCR PB0CR
  86 #  if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
  87 #   define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
  88 #   define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
  89 #  endif
  90 # endif
  91 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
  92 #  define PBxAP PB1AP
  93 #  define PBxCR PB1CR
  94 #  if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
  95 #   define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
  96 #   define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
  97 #  endif
  98 # endif
  99 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
 100 #  define PBxAP PB2AP
 101 #  define PBxCR PB2CR
 102 #  if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
 103 #   define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
 104 #   define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
 105 #  endif
 106 # endif
 107 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
 108 #  define PBxAP PB3AP
 109 #  define PBxCR PB3CR
 110 #  if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
 111 #   define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
 112 #   define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
 113 #  endif
 114 # endif
 115 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
 116 #  define PBxAP PB4AP
 117 #  define PBxCR PB4CR
 118 #  if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
 119 #   define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
 120 #   define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
 121 #  endif
 122 # endif
 123 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
 124 #  define PBxAP PB5AP
 125 #  define PBxCR PB5CR
 126 #  if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
 127 #   define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
 128 #   define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
 129 #  endif
 130 # endif
 131 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
 132 #  define PBxAP PB6AP
 133 #  define PBxCR PB6CR
 134 #  if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
 135 #   define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
 136 #   define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
 137 #  endif
 138 # endif
 139 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
 140 #  define PBxAP PB7AP
 141 #  define PBxCR PB7CR
 142 #  if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
 143 #   define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
 144 #   define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
 145 #  endif
 146 # endif
 147 # ifndef PBxAP_VAL
 148 #  define PBxAP_VAL     0
 149 # endif
 150 # ifndef PBxCR_VAL
 151 #  define PBxCR_VAL     0
 152 # endif
 153 /*
 154  * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
 155  * used as temporary stack pointer for the primordial stack
 156  */
 157 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
 158 #  define CONFIG_SYS_INIT_DCACHE_PBxAR  (EBC_BXAP_BME_DISABLED                  | \
 159                                  EBC_BXAP_TWT_ENCODE(7)                 | \
 160                                  EBC_BXAP_BCE_DISABLE                   | \
 161                                  EBC_BXAP_BCT_2TRANS                    | \
 162                                  EBC_BXAP_CSN_ENCODE(0)                 | \
 163                                  EBC_BXAP_OEN_ENCODE(0)                 | \
 164                                  EBC_BXAP_WBN_ENCODE(0)                 | \
 165                                  EBC_BXAP_WBF_ENCODE(0)                 | \
 166                                  EBC_BXAP_TH_ENCODE(2)                  | \
 167                                  EBC_BXAP_RE_DISABLED                   | \
 168                                  EBC_BXAP_SOR_NONDELAYED                | \
 169                                  EBC_BXAP_BEM_WRITEONLY                 | \
 170                                  EBC_BXAP_PEN_DISABLED)
 171 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
 172 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
 173 #  define CONFIG_SYS_INIT_DCACHE_PBxCR  (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR)  | \
 174                                  EBC_BXCR_BS_64MB                       | \
 175                                  EBC_BXCR_BU_RW                         | \
 176                                  EBC_BXCR_BW_16BIT)
 177 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
 178 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
 179 #  define CONFIG_SYS_INIT_RAM_PATTERN   0xDEADDEAD
 180 # endif
 181 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
 182
 183 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
 184 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
 185 #endif
 186
 187 /*
 188  * Unless otherwise overriden, enable two 128MB cachable instruction regions
 189  * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
 190  * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
 191  */
 192 #if !defined(CONFIG_SYS_FLASH_BASE)
 193 /* If not already defined, set it to the "last" 128MByte region */
 194 # define CONFIG_SYS_FLASH_BASE          0xf8000000
 195 #endif
 196 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
 197 # define CONFIG_SYS_ICACHE_SACR_VALUE           \
 198                 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (  0 << 20)) | \
 199                  PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
 200                  PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
 201 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
 202
 203 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
 204 # define CONFIG_SYS_DCACHE_SACR_VALUE           \
 205                 (0x00000000)
 206 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
 207
 208 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
 209 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0       /* use TLB 0 as default */
 210 #endif
 211
 212 #define function_prolog(func_name)      .text; \
 213                                         .align 2; \
 214                                         .globl func_name; \
 215                                         func_name:
 216 #define function_epilog(func_name)      .type func_name,@function; \
 217                                         .size func_name,.-func_name
 218
 219 /* We don't want the  MMU yet.
 220 */
 221 #undef  MSR_KERNEL
 222 #define MSR_KERNEL ( MSR_ME  )  /* Machine Check */
 223
 224
 225         .extern ext_bus_cntlr_init
 226 #ifdef CONFIG_NAND_U_BOOT
 227         .extern reconfig_tlb0
 228 #endif
 229
 230 /*
 231  * Set up GOT: Global Offset Table
 232  *
 233  * Use r12 to access the GOT
 234  */
 235 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 236         START_GOT
 237         GOT_ENTRY(_GOT2_TABLE_)
 238         GOT_ENTRY(_FIXUP_TABLE_)
 239
 240         GOT_ENTRY(_start)
 241         GOT_ENTRY(_start_of_vectors)
 242         GOT_ENTRY(_end_of_vectors)
 243         GOT_ENTRY(transfer_to_handler)
 244
 245         GOT_ENTRY(__init_end)
 246         GOT_ENTRY(__bss_end)
 247         GOT_ENTRY(__bss_start)
 248         END_GOT
 249 #endif /* CONFIG_NAND_SPL */
 250
 251 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
 252         !defined(CONFIG_SPL_BUILD)
 253         /*
 254          * NAND U-Boot image is started from offset 0
 255          */
 256         .text
 257 #if defined(CONFIG_440)
 258         bl      reconfig_tlb0
 259 #endif
 260         GET_GOT
 261         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 262         bl      board_init_f
 263         /* NOTREACHED - board_init_f() does not return */
 264 #endif
 265
 266 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
 267         /*
 268          * 4xx RAM-booting U-Boot image is started from offset 0
 269          */
 270         .text
 271         bl      _start_440
 272 #endif
 273
 274 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 275         /*
 276          * This is the entry of the real U-Boot from a board port
 277          * that supports SPL booting on the PPC4xx. We only need
 278          * to call board_init_f() here. Everything else has already
 279          * been done in the SPL u-boot version.
 280          */
 281         GET_GOT                 /* initialize GOT access                */
 282         bl      board_init_f    /* run 1st part of board init code (in Flash)*/
 283         /* NOTREACHED - board_init_f() does not return */
 284 #endif
 285
 286 /*
 287  * 440 Startup -- on reset only the top 4k of the effective
 288  * address space is mapped in by an entry in the instruction
 289  * and data shadow TLB. The .bootpg section is located in the
 290  * top 4k & does only what's necessary to map in the the rest
 291  * of the boot rom. Once the boot rom is mapped in we can
 292  * proceed with normal startup.
 293  *
 294  * NOTE: CS0 only covers the top 2MB of the effective address
 295  * space after reset.
 296  */
 297
 298 #if defined(CONFIG_440)
 299 #if !defined(CONFIG_NAND_SPL)
 300     .section .bootpg,"ax"
 301 #endif
 302     .globl _start_440
 303
 304 /**************************************************************************/
 305 _start_440:
 306         /*--------------------------------------------------------------------+
 307         | 440EPX BUP Change - Hardware team request
 308         +--------------------------------------------------------------------*/
 309 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 310         sync
 311         nop
 312         nop
 313 #endif
 314         /*----------------------------------------------------------------+
 315         | Core bug fix.  Clear the esr
 316         +-----------------------------------------------------------------*/
 317         li      r0,0
 318         mtspr   SPRN_ESR,r0
 319         /*----------------------------------------------------------------*/
 320         /* Clear and set up some registers. */
 321         /*----------------------------------------------------------------*/
 322         iccci   r0,r0           /* NOTE: operands not used for 440 */
 323         dccci   r0,r0           /* NOTE: operands not used for 440 */
 324         sync
 325         li      r0,0
 326         mtspr   SPRN_SRR0,r0
 327         mtspr   SPRN_SRR1,r0
 328         mtspr   SPRN_CSRR0,r0
 329         mtspr   SPRN_CSRR1,r0
 330         /* NOTE: 440GX adds machine check status regs */
 331 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
 332         mtspr   SPRN_MCSRR0,r0
 333         mtspr   SPRN_MCSRR1,r0
 334         mfspr   r1,SPRN_MCSR
 335         mtspr   SPRN_MCSR,r1
 336 #endif
 337
 338         /*----------------------------------------------------------------*/
 339         /* CCR0 init */
 340         /*----------------------------------------------------------------*/
 341         /* Disable store gathering & broadcast, guarantee inst/data
 342         * cache block touch, force load/store alignment
 343         * (see errata 1.12: 440_33)
 344         */
 345         lis     r1,0x0030       /* store gathering & broadcast disable */
 346         ori     r1,r1,0x6000    /* cache touch */
 347         mtspr   SPRN_CCR0,r1
 348
 349         /*----------------------------------------------------------------*/
 350         /* Initialize debug */
 351         /*----------------------------------------------------------------*/
 352         mfspr   r1,SPRN_DBCR0
 353         andis.  r1, r1, 0x8000  /* test DBCR0[EDM] bit                  */
 354         bne     skip_debug_init /* if set, don't clear debug register   */
 355         mfspr   r1,SPRN_CCR0
 356         ori     r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
 357         mtspr   SPRN_CCR0,r1
 358         mtspr   SPRN_DBCR0,r0
 359         mtspr   SPRN_DBCR1,r0
 360         mtspr   SPRN_DBCR2,r0
 361         mtspr   SPRN_IAC1,r0
 362         mtspr   SPRN_IAC2,r0
 363         mtspr   SPRN_IAC3,r0
 364         mtspr   SPRN_DAC1,r0
 365         mtspr   SPRN_DAC2,r0
 366         mtspr   SPRN_DVC1,r0
 367         mtspr   SPRN_DVC2,r0
 368
 369         mfspr   r1,SPRN_DBSR
 370         mtspr   SPRN_DBSR,r1    /* Clear all valid bits */
 371 skip_debug_init:
 372
 373 #if defined (CONFIG_440SPE)
 374         /*----------------------------------------------------------------+
 375         | Initialize Core Configuration Reg1.
 376         | a. ICDPEI: Record even parity. Normal operation.
 377         | b. ICTPEI: Record even parity. Normal operation.
 378         | c. DCTPEI: Record even parity. Normal operation.
 379         | d. DCDPEI: Record even parity. Normal operation.
 380         | e. DCUPEI: Record even parity. Normal operation.
 381         | f. DCMPEI: Record even parity. Normal operation.
 382         | g. FCOM:   Normal operation
 383         | h. MMUPEI: Record even parity. Normal operation.
 384         | i. FFF:    Flush only as much data as necessary.
 385         | j. TCS:    Timebase increments from CPU clock.
 386         +-----------------------------------------------------------------*/
 387         li      r0,0
 388         mtspr   SPRN_CCR1, r0
 389
 390         /*----------------------------------------------------------------+
 391         | Reset the timebase.
 392         | The previous write to CCR1 sets the timebase source.
 393         +-----------------------------------------------------------------*/
 394         mtspr   SPRN_TBWL, r0
 395         mtspr   SPRN_TBWU, r0
 396 #endif
 397
 398         /*----------------------------------------------------------------*/
 399         /* Setup interrupt vectors */
 400         /*----------------------------------------------------------------*/
 401         mtspr   SPRN_IVPR,r0            /* Vectors start at 0x0000_0000 */
 402         li      r1,0x0100
 403         mtspr   SPRN_IVOR0,r1   /* Critical input */
 404         li      r1,0x0200
 405         mtspr   SPRN_IVOR1,r1   /* Machine check */
 406         li      r1,0x0300
 407         mtspr   SPRN_IVOR2,r1   /* Data storage */
 408         li      r1,0x0400
 409         mtspr   SPRN_IVOR3,r1   /* Instruction storage */
 410         li      r1,0x0500
 411         mtspr   SPRN_IVOR4,r1   /* External interrupt */
 412         li      r1,0x0600
 413         mtspr   SPRN_IVOR5,r1   /* Alignment */
 414         li      r1,0x0700
 415         mtspr   SPRN_IVOR6,r1   /* Program check */
 416         li      r1,0x0800
 417         mtspr   SPRN_IVOR7,r1   /* Floating point unavailable */
 418         li      r1,0x0c00
 419         mtspr   SPRN_IVOR8,r1   /* System call */
 420         li      r1,0x0a00
 421         mtspr   SPRN_IVOR9,r1   /* Auxiliary Processor unavailable */
 422         li      r1,0x0900
 423         mtspr   SPRN_IVOR10,r1  /* Decrementer */
 424         li      r1,0x1300
 425         mtspr   SPRN_IVOR13,r1  /* Data TLB error */
 426         li      r1,0x1400
 427         mtspr   SPRN_IVOR14,r1  /* Instr TLB error */
 428         li      r1,0x2000
 429         mtspr   SPRN_IVOR15,r1  /* Debug */
 430
 431         /*----------------------------------------------------------------*/
 432         /* Configure cache regions  */
 433         /*----------------------------------------------------------------*/
 434         mtspr   SPRN_INV0,r0
 435         mtspr   SPRN_INV1,r0
 436         mtspr   SPRN_INV2,r0
 437         mtspr   SPRN_INV3,r0
 438         mtspr   SPRN_DNV0,r0
 439         mtspr   SPRN_DNV1,r0
 440         mtspr   SPRN_DNV2,r0
 441         mtspr   SPRN_DNV3,r0
 442         mtspr   SPRN_ITV0,r0
 443         mtspr   SPRN_ITV1,r0
 444         mtspr   SPRN_ITV2,r0
 445         mtspr   SPRN_ITV3,r0
 446         mtspr   SPRN_DTV0,r0
 447         mtspr   SPRN_DTV1,r0
 448         mtspr   SPRN_DTV2,r0
 449         mtspr   SPRN_DTV3,r0
 450
 451         /*----------------------------------------------------------------*/
 452         /* Cache victim limits */
 453         /*----------------------------------------------------------------*/
 454         /* floors 0, ceiling max to use the entire cache -- nothing locked
 455         */
 456         lis     r1,0x0001
 457         ori     r1,r1,0xf800
 458         mtspr   SPRN_IVLIM,r1
 459         mtspr   SPRN_DVLIM,r1
 460
 461         /*----------------------------------------------------------------+
 462         |Initialize MMUCR[STID] = 0.
 463         +-----------------------------------------------------------------*/
 464         mfspr   r0,SPRN_MMUCR
 465         addis   r1,0,0xFFFF
 466         ori     r1,r1,0xFF00
 467         and     r0,r0,r1
 468         mtspr   SPRN_MMUCR,r0
 469
 470         /*----------------------------------------------------------------*/
 471         /* Clear all TLB entries -- TID = 0, TS = 0 */
 472         /*----------------------------------------------------------------*/
 473         addis   r0,0,0x0000
 474 #ifdef CONFIG_SYS_RAMBOOT
 475         li      r4,0            /* Start with TLB #0 */
 476 #else
 477         li      r4,1            /* Start with TLB #1 */
 478 #endif
 479         li      r1,64           /* 64 TLB entries */
 480         sub     r1,r1,r4        /* calculate last TLB # */
 481         mtctr   r1
 482 rsttlb:
 483 #ifdef CONFIG_SYS_RAMBOOT
 484         tlbre   r3,r4,0         /* Read contents from TLB word #0 to get EPN */
 485         rlwinm. r3,r3,0,0xfffffc00      /* Mask EPN */
 486         beq     tlbnxt          /* Skip EPN=0 TLB, this is the SDRAM TLB */
 487 #endif
 488         tlbwe   r0,r4,0         /* Invalidate all entries (V=0)*/
 489         tlbwe   r0,r4,1
 490         tlbwe   r0,r4,2
 491 tlbnxt: addi    r4,r4,1         /* Next TLB */
 492         bdnz    rsttlb
 493
 494         /*----------------------------------------------------------------*/
 495         /* TLB entry setup -- step thru tlbtab */
 496         /*----------------------------------------------------------------*/
 497 #if defined(CONFIG_440SPE_REVA)
 498         /*----------------------------------------------------------------*/
 499         /* We have different TLB tables for revA and rev B of 440SPe */
 500         /*----------------------------------------------------------------*/
 501         mfspr   r1, PVR
 502         lis     r0,0x5342
 503         ori     r0,r0,0x1891
 504         cmpw    r7,r1,r0
 505         bne     r7,..revA
 506         bl      tlbtabB
 507         b       ..goon
 508 ..revA:
 509         bl      tlbtabA
 510 ..goon:
 511 #else
 512         bl      tlbtab          /* Get tlbtab pointer */
 513 #endif
 514         mr      r5,r0
 515         li      r1,0x003f       /* 64 TLB entries max */
 516         mtctr   r1
 517         li      r4,0            /* TLB # */
 518
 519         addi    r5,r5,-4
 520 1:
 521 #ifdef CONFIG_SYS_RAMBOOT
 522         tlbre   r3,r4,0         /* Read contents from TLB word #0 */
 523         rlwinm. r3,r3,0,0x00000200      /* Mask V (valid) bit */
 524         bne     tlbnx2          /* Skip V=1 TLB, this is the SDRAM TLB */
 525 #endif
 526         lwzu    r0,4(r5)
 527         cmpwi   r0,0
 528         beq     2f              /* 0 marks end */
 529         lwzu    r1,4(r5)
 530         lwzu    r2,4(r5)
 531         tlbwe   r0,r4,0         /* TLB Word 0 */
 532         tlbwe   r1,r4,1         /* TLB Word 1 */
 533         tlbwe   r2,r4,2         /* TLB Word 2 */
 534 tlbnx2: addi    r4,r4,1         /* Next TLB */
 535         bdnz    1b
 536
 537         /*----------------------------------------------------------------*/
 538         /* Continue from 'normal' start */
 539         /*----------------------------------------------------------------*/
 540 2:
 541         bl      3f
 542         b       _start
 543
 544 3:      li      r0,0
 545         mtspr   SPRN_SRR1,r0            /* Keep things disabled for now */
 546         mflr    r1
 547         mtspr   SPRN_SRR0,r1
 548         rfi
 549 #endif /* CONFIG_440 */
 550
 551 /*
 552  * r3 - 1st arg to board_init(): IMMP pointer
 553  * r4 - 2nd arg to board_init(): boot flag
 554  */
 555 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 556         .text
 557         .long   0x27051956              /* U-Boot Magic Number                  */
 558         .globl  version_string
 559 version_string:
 560         .ascii U_BOOT_VERSION_STRING, "\0"
 561
 562         . = EXC_OFF_SYS_RESET
 563         .globl  _start_of_vectors
 564 _start_of_vectors:
 565
 566 /* Critical input. */
 567         CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
 568
 569 #ifdef CONFIG_440
 570 /* Machine check */
 571         MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 572 #else
 573         CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 574 #endif /* CONFIG_440 */
 575
 576 /* Data Storage exception. */
 577         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 578
 579 /* Instruction Storage exception. */
 580         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 581
 582 /* External Interrupt exception. */
 583         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 584
 585 /* Alignment exception. */
 586         . = 0x600
 587 Alignment:
 588         EXCEPTION_PROLOG(SRR0, SRR1)
 589         mfspr   r4,DAR
 590         stw     r4,_DAR(r21)
 591         mfspr   r5,DSISR
 592         stw     r5,_DSISR(r21)
 593         addi    r3,r1,STACK_FRAME_OVERHEAD
 594         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 595
 596 /* Program check exception */
 597         . = 0x700
 598 ProgramCheck:
 599         EXCEPTION_PROLOG(SRR0, SRR1)
 600         addi    r3,r1,STACK_FRAME_OVERHEAD
 601         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 602                 MSR_KERNEL, COPY_EE)
 603
 604 #ifdef CONFIG_440
 605         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 606         STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
 607         STD_EXCEPTION(0xa00, APU, UnknownException)
 608 #endif
 609         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 610
 611 #ifdef CONFIG_440
 612         STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
 613         STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
 614 #else
 615         STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
 616         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 617         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 618 #endif
 619         CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
 620
 621         .globl  _end_of_vectors
 622 _end_of_vectors:
 623         . = _START_OFFSET
 624 #endif
 625         .globl  _start
 626 _start:
 627
 628 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 629         /*
 630          * This is the entry of the real U-Boot from a board port
 631          * that supports SPL booting on the PPC4xx. We only need
 632          * to call board_init_f() here. Everything else has already
 633          * been done in the SPL u-boot version.
 634          */
 635         GET_GOT                 /* initialize GOT access                */
 636         bl      board_init_f    /* run 1st part of board init code (in Flash)*/
 637         /* NOTREACHED - board_init_f() does not return */
 638 #endif
 639
 640 /*****************************************************************************/
 641 #if defined(CONFIG_440)
 642
 643         /*----------------------------------------------------------------*/
 644         /* Clear and set up some registers. */
 645         /*----------------------------------------------------------------*/
 646         li      r0,0x0000
 647         lis     r1,0xffff
 648         mtspr   SPRN_DEC,r0                     /* prevent dec exceptions */
 649         mtspr   SPRN_TBWL,r0                    /* prevent fit & wdt exceptions */
 650         mtspr   SPRN_TBWU,r0
 651         mtspr   SPRN_TSR,r1                     /* clear all timer exception status */
 652         mtspr   SPRN_TCR,r0                     /* disable all */
 653         mtspr   SPRN_ESR,r0                     /* clear exception syndrome register */
 654         mtxer   r0                      /* clear integer exception register */
 655
 656         /*----------------------------------------------------------------*/
 657         /* Debug setup -- some (not very good) ice's need an event*/
 658         /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
 659         /* value you need in this case 0x8cff 0000 should do the trick */
 660         /*----------------------------------------------------------------*/
 661 #if defined(CONFIG_SYS_INIT_DBCR)
 662         lis     r1,0xffff
 663         ori     r1,r1,0xffff
 664         mtspr   SPRN_DBSR,r1                    /* Clear all status bits */
 665         lis     r0,CONFIG_SYS_INIT_DBCR@h
 666         ori     r0,r0,CONFIG_SYS_INIT_DBCR@l
 667         mtspr   SPRN_DBCR0,r0
 668         isync
 669 #endif
 670
 671         /*----------------------------------------------------------------*/
 672         /* Setup the internal SRAM */
 673         /*----------------------------------------------------------------*/
 674         li      r0,0
 675
 676 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
 677         /* Clear Dcache to use as RAM */
 678         addis   r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
 679         ori     r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
 680         addis   r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
 681         ori     r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
 682         rlwinm. r5,r4,0,27,31
 683         rlwinm  r5,r4,27,5,31
 684         beq     ..d_ran
 685         addi    r5,r5,0x0001
 686 ..d_ran:
 687         mtctr   r5
 688 ..d_ag:
 689         dcbz    r0,r3
 690         addi    r3,r3,32
 691         bdnz    ..d_ag
 692
 693         /*
 694          * Lock the init-ram/stack in d-cache, so that other regions
 695          * may use d-cache as well
 696          * Note, that this current implementation locks exactly 4k
 697          * of d-cache, so please make sure that you don't define a
 698          * bigger init-ram area. Take a look at the lwmon5 440EPx
 699          * implementation as a reference.
 700          */
 701         msync
 702         isync
 703         /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
 704         lis     r1,0x0201
 705         ori     r1,r1,0xf808
 706         mtspr   SPRN_DVLIM,r1
 707         lis     r1,0x0808
 708         ori     r1,r1,0x0808
 709         mtspr   SPRN_DNV0,r1
 710         mtspr   SPRN_DNV1,r1
 711         mtspr   SPRN_DNV2,r1
 712         mtspr   SPRN_DNV3,r1
 713         mtspr   SPRN_DTV0,r1
 714         mtspr   SPRN_DTV1,r1
 715         mtspr   SPRN_DTV2,r1
 716         mtspr   SPRN_DTV3,r1
 717         msync
 718         isync
 719 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 720
 721         /* 440EP & 440GR are only 440er PPC's without internal SRAM */
 722 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
 723         /* not all PPC's have internal SRAM usable as L2-cache */
 724 #if defined(CONFIG_440GX) || \
 725     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 726     defined(CONFIG_460SX)
 727         mtdcr   L2_CACHE_CFG,r0         /* Ensure L2 Cache is off */
 728 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 729       defined(CONFIG_APM821XX)
 730         lis     r1, 0x0000
 731         ori     r1,r1,0x0008            /* Set L2_CACHE_CFG[RDBW]=1 */
 732         mtdcr   L2_CACHE_CFG,r1
 733 #endif
 734
 735         lis     r2,0x7fff
 736         ori     r2,r2,0xffff
 737         mfdcr   r1,ISRAM0_DPC
 738         and     r1,r1,r2                /* Disable parity check */
 739         mtdcr   ISRAM0_DPC,r1
 740         mfdcr   r1,ISRAM0_PMEG
 741         and     r1,r1,r2                /* Disable pwr mgmt */
 742         mtdcr   ISRAM0_PMEG,r1
 743
 744         lis     r1,0x8000               /* BAS = 8000_0000 */
 745 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 746         ori     r1,r1,0x0980            /* first 64k */
 747         mtdcr   ISRAM0_SB0CR,r1
 748         lis     r1,0x8001
 749         ori     r1,r1,0x0980            /* second 64k */
 750         mtdcr   ISRAM0_SB1CR,r1
 751         lis     r1, 0x8002
 752         ori     r1,r1, 0x0980           /* third 64k */
 753         mtdcr   ISRAM0_SB2CR,r1
 754         lis     r1, 0x8003
 755         ori     r1,r1, 0x0980           /* fourth 64k */
 756         mtdcr   ISRAM0_SB3CR,r1
 757 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
 758       defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
 759         lis     r1,0x0000               /* BAS = X_0000_0000 */
 760         ori     r1,r1,0x0984            /* first 64k */
 761         mtdcr   ISRAM0_SB0CR,r1
 762         lis     r1,0x0001
 763         ori     r1,r1,0x0984            /* second 64k */
 764         mtdcr   ISRAM0_SB1CR,r1
 765         lis     r1, 0x0002
 766         ori     r1,r1, 0x0984           /* third 64k */
 767         mtdcr   ISRAM0_SB2CR,r1
 768         lis     r1, 0x0003
 769         ori     r1,r1, 0x0984           /* fourth 64k */
 770         mtdcr   ISRAM0_SB3CR,r1
 771 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 772     defined(CONFIG_APM821XX)
 773         lis     r2,0x7fff
 774         ori     r2,r2,0xffff
 775         mfdcr   r1,ISRAM1_DPC
 776         and     r1,r1,r2                /* Disable parity check */
 777         mtdcr   ISRAM1_DPC,r1
 778         mfdcr   r1,ISRAM1_PMEG
 779         and     r1,r1,r2                /* Disable pwr mgmt */
 780         mtdcr   ISRAM1_PMEG,r1
 781
 782         lis     r1,0x0004               /* BAS = 4_0004_0000 */
 783         ori     r1,r1,ISRAM1_SIZE       /* ocm size */
 784         mtdcr   ISRAM1_SB0CR,r1
 785 #endif
 786 #elif defined(CONFIG_460SX)
 787         lis     r1,0x0000               /* BAS = 0000_0000 */
 788         ori     r1,r1,0x0B84            /* first 128k */
 789         mtdcr   ISRAM0_SB0CR,r1
 790         lis     r1,0x0001
 791         ori     r1,r1,0x0B84            /* second 128k */
 792         mtdcr   ISRAM0_SB1CR,r1
 793         lis     r1, 0x0002
 794         ori     r1,r1, 0x0B84           /* third 128k */
 795         mtdcr   ISRAM0_SB2CR,r1
 796         lis     r1, 0x0003
 797         ori     r1,r1, 0x0B84           /* fourth 128k */
 798         mtdcr   ISRAM0_SB3CR,r1
 799 #elif defined(CONFIG_440GP)
 800         ori     r1,r1,0x0380            /* 8k rw */
 801         mtdcr   ISRAM0_SB0CR,r1
 802         mtdcr   ISRAM0_SB1CR,r0         /* Disable bank 1 */
 803 #endif
 804 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 805
 806         /*----------------------------------------------------------------*/
 807         /* Setup the stack in internal SRAM */
 808         /*----------------------------------------------------------------*/
 809         lis     r1,CONFIG_SYS_INIT_RAM_ADDR@h
 810         ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
 811         li      r0,0
 812         stwu    r0,-4(r1)
 813         stwu    r0,-4(r1)               /* Terminate call chain */
 814
 815         stwu    r1,-8(r1)               /* Save back chain and move SP */
 816         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 817         ori     r0,r0, RESET_VECTOR@l
 818         stwu    r1,-8(r1)               /* Save back chain and move SP */
 819         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 820
 821 #ifdef CONFIG_NAND_SPL
 822         bl      nand_boot_common        /* will not return */
 823 #else
 824 #ifndef CONFIG_SPL_BUILD
 825         GET_GOT
 826 #endif
 827
 828         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 829         bl      board_init_f
 830         /* NOTREACHED - board_init_f() does not return */
 831 #endif
 832
 833 #endif /* CONFIG_440 */
 834
 835 /*****************************************************************************/
 836 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
 837     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 838     defined(CONFIG_405EX) || defined(CONFIG_405)
 839         /*----------------------------------------------------------------------- */
 840         /* Clear and set up some registers. */
 841         /*----------------------------------------------------------------------- */
 842         addi    r4,r0,0x0000
 843 #if !defined(CONFIG_405EX)
 844         mtspr   SPRN_SGR,r4
 845 #else
 846         /*
 847          * On 405EX, completely clearing the SGR leads to PPC hangup
 848          * upon PCIe configuration access. The PCIe memory regions
 849          * need to be guarded!
 850          */
 851         lis     r3,0x0000
 852         ori     r3,r3,0x7FFC
 853         mtspr   SPRN_SGR,r3
 854 #endif
 855         mtspr   SPRN_DCWR,r4
 856         mtesr   r4                      /* clear Exception Syndrome Reg */
 857         mttcr   r4                      /* clear Timer Control Reg */
 858         mtxer   r4                      /* clear Fixed-Point Exception Reg */
 859         mtevpr  r4                      /* clear Exception Vector Prefix Reg */
 860         addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF (status in the */
 861                                         /* dbsr is cleared by setting bits to 1) */
 862         mtdbsr  r4                      /* clear/reset the dbsr */
 863
 864         /* Invalidate the i- and d-caches. */
 865         bl      invalidate_icache
 866         bl      invalidate_dcache
 867
 868         /* Set-up icache cacheability. */
 869         lis     r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
 870         ori     r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
 871         mticcr  r4
 872         isync
 873
 874         /* Set-up dcache cacheability. */
 875         lis     r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
 876         ori     r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
 877         mtdccr  r4
 878
 879 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
 880                                 && !defined (CONFIG_XILINX_405)
 881         /*----------------------------------------------------------------------- */
 882         /* Tune the speed and size for flash CS0  */
 883         /*----------------------------------------------------------------------- */
 884         bl      ext_bus_cntlr_init
 885 #endif
 886
 887 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
 888         /*
 889          * For boards that don't have OCM and can't use the data cache
 890          * for their primordial stack, setup stack here directly after the
 891          * SDRAM is initialized in ext_bus_cntlr_init.
 892          */
 893         lis     r1, CONFIG_SYS_INIT_RAM_ADDR@h
 894         ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
 895
 896         li      r0, 0                   /* Make room for stack frame header and */
 897         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 898         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 899         /*
 900          * Set up a dummy frame to store reset vector as return address.
 901          * this causes stack underflow to reset board.
 902          */
 903         stwu    r1, -8(r1)              /* Save back chain and move SP */
 904         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
 905         ori     r0, r0, RESET_VECTOR@l
 906         stwu    r1, -8(r1)              /* Save back chain and move SP */
 907         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
 908 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS   || !CONFIG_SYS_TEM_STACK_OCM) */
 909
 910 #if defined(CONFIG_405EP)
 911         /*----------------------------------------------------------------------- */
 912         /* DMA Status, clear to come up clean */
 913         /*----------------------------------------------------------------------- */
 914         addis   r3,r0, 0xFFFF           /* Clear all existing DMA status */
 915         ori     r3,r3, 0xFFFF
 916         mtdcr   DMASR, r3
 917
 918         bl      ppc405ep_init           /* do ppc405ep specific init */
 919 #endif /* CONFIG_405EP */
 920
 921 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
 922 #if defined(CONFIG_405EZ)
 923         /********************************************************************
 924          * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
 925          *******************************************************************/
 926         /*
 927          * We can map the OCM on the PLB3, so map it at
 928          * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
 929          */
 930         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 931         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 932         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 933         mtdcr   OCM0_PLBCR1,r3          /* Set PLB Access */
 934         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 935         mtdcr   OCM0_PLBCR2,r3          /* Set PLB Access */
 936         isync
 937
 938         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 939         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 940         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 941         mtdcr   OCM0_DSRC1, r3          /* Set Data Side */
 942         mtdcr   OCM0_ISRC1, r3          /* Set Instruction Side */
 943         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 944         mtdcr   OCM0_DSRC2, r3          /* Set Data Side */
 945         mtdcr   OCM0_ISRC2, r3          /* Set Instruction Side */
 946         addis   r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
 947         mtdcr   OCM0_DISDPC,r3
 948
 949         isync
 950 #else /* CONFIG_405EZ */
 951         /********************************************************************
 952          * Setup OCM - On Chip Memory
 953          *******************************************************************/
 954         /* Setup OCM */
 955         lis     r0, 0x7FFF
 956         ori     r0, r0, 0xFFFF
 957         mfdcr   r3, OCM0_ISCNTL         /* get instr-side IRAM config */
 958         mfdcr   r4, OCM0_DSCNTL         /* get data-side IRAM config */
 959         and     r3, r3, r0              /* disable data-side IRAM */
 960         and     r4, r4, r0              /* disable data-side IRAM */
 961         mtdcr   OCM0_ISCNTL, r3         /* set instr-side IRAM config */
 962         mtdcr   OCM0_DSCNTL, r4         /* set data-side IRAM config */
 963         isync
 964
 965         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 966         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 967         mtdcr   OCM0_DSARC, r3
 968         addis   r4, 0, 0xC000           /* OCM data area enabled */
 969         mtdcr   OCM0_DSCNTL, r4
 970         isync
 971 #endif /* CONFIG_405EZ */
 972 #endif
 973
 974         /*----------------------------------------------------------------------- */
 975         /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 976         /*----------------------------------------------------------------------- */
 977 #ifdef CONFIG_SYS_INIT_DCACHE_CS
 978         li      r4, PBxAP
 979         mtdcr   EBC0_CFGADDR, r4
 980         lis     r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
 981         ori     r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
 982         mtdcr   EBC0_CFGDATA, r4
 983
 984         addi    r4, 0, PBxCR
 985         mtdcr   EBC0_CFGADDR, r4
 986         lis     r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
 987         ori     r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
 988         mtdcr   EBC0_CFGDATA, r4
 989
 990         /*
 991          * Enable the data cache for the 128MB storage access control region
 992          * at CONFIG_SYS_INIT_RAM_ADDR.
 993          */
 994         mfdccr  r4
 995         oris    r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
 996         ori     r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
 997         mtdccr  r4
 998
 999         /*
1000          * Preallocate data cache lines to be used to avoid a subsequent
1001          * cache miss and an ensuing machine check exception when exceptions
1002          * are enabled.
1003          */
1004         li      r0, 0
1005
1006         lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
1007         ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1008
1009         lis     r4, CONFIG_SYS_INIT_RAM_SIZE@h
1010         ori     r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1011
1012         /*
1013          * Convert the size, in bytes, to the number of cache lines/blocks
1014          * to preallocate.
1015          */
1016         clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1017         srwi    r5, r4, L1_CACHE_SHIFT
1018         beq     ..load_counter
1019         addi    r5, r5, 0x0001
1020 ..load_counter:
1021         mtctr   r5
1022
1023         /* Preallocate the computed number of cache blocks. */
1024 ..alloc_dcache_block:
1025         dcba    r0, r3
1026         addi    r3, r3, L1_CACHE_BYTES
1027         bdnz    ..alloc_dcache_block
1028         sync
1029
1030         /*
1031          * Load the initial stack pointer and data area and convert the size,
1032          * in bytes, to the number of words to initialize to a known value.
1033          */
1034         lis     r1, CONFIG_SYS_INIT_RAM_ADDR@h
1035         ori     r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1036
1037         lis     r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
1038         ori     r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1039         mtctr   r4
1040
1041         lis     r2, CONFIG_SYS_INIT_RAM_ADDR@h
1042         ori     r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1043
1044         lis     r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1045         ori     r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1046
1047 ..stackloop:
1048         stwu    r4, -4(r2)
1049         bdnz    ..stackloop
1050
1051         /*
1052          * Make room for stack frame header and clear final stack frame so
1053          * that stack backtraces terminate cleanly.
1054          */
1055         stwu    r0, -4(r1)
1056         stwu    r0, -4(r1)
1057
1058         /*
1059          * Set up a dummy frame to store reset vector as return address.
1060          * this causes stack underflow to reset board.
1061          */
1062         stwu    r1, -8(r1)              /* Save back chain and move SP */
1063         addis   r0, 0, RESET_VECTOR@h   /* Address of reset vector */
1064         ori     r0, r0, RESET_VECTOR@l
1065         stwu    r1, -8(r1)              /* Save back chain and move SP */
1066         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1067
1068 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1069         (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1070         /*
1071          * Stack in OCM.
1072          */
1073
1074         /* Set up Stack at top of OCM */
1075         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1076         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1077
1078         /* Set up a zeroized stack frame so that backtrace works right */
1079         li      r0, 0
1080         stwu    r0, -4(r1)
1081         stwu    r0, -4(r1)
1082
1083         /*
1084          * Set up a dummy frame to store reset vector as return address.
1085          * this causes stack underflow to reset board.
1086          */
1087         stwu    r1, -8(r1)              /* Save back chain and move SP */
1088         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
1089         ori     r0, r0, RESET_VECTOR@l
1090         stwu    r1, -8(r1)              /* Save back chain and move SP */
1091         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1092 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1093
1094 #ifdef CONFIG_NAND_SPL
1095         bl      nand_boot_common        /* will not return */
1096 #else
1097         GET_GOT                 /* initialize GOT access                        */
1098
1099         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
1100
1101         bl      board_init_f    /* run first part of init code (from Flash)     */
1102         /* NOTREACHED - board_init_f() does not return */
1103
1104 #endif /* CONFIG_NAND_SPL */
1105
1106 #endif  /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1107         /*----------------------------------------------------------------------- */
1108
1109
1110 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
1111 /*
1112  * This code finishes saving the registers to the exception frame
1113  * and jumps to the appropriate handler for the exception.
1114  * Register r21 is pointer into trap frame, r1 has new stack pointer.
1115  */
1116         .globl  transfer_to_handler
1117 transfer_to_handler:
1118         stw     r22,_NIP(r21)
1119         lis     r22,MSR_POW@h
1120         andc    r23,r23,r22
1121         stw     r23,_MSR(r21)
1122         SAVE_GPR(7, r21)
1123         SAVE_4GPRS(8, r21)
1124         SAVE_8GPRS(12, r21)
1125         SAVE_8GPRS(24, r21)
1126         mflr    r23
1127         andi.   r24,r23,0x3f00          /* get vector offset */
1128         stw     r24,TRAP(r21)
1129         li      r22,0
1130         stw     r22,RESULT(r21)
1131         mtspr   SPRG2,r22               /* r1 is now kernel sp */
1132         lwz     r24,0(r23)              /* virtual address of handler */
1133         lwz     r23,4(r23)              /* where to go when done */
1134         mtspr   SRR0,r24
1135         mtspr   SRR1,r20
1136         mtlr    r23
1137         SYNC
1138         rfi                             /* jump to handler, enable MMU */
1139
1140 int_return:
1141         mfmsr   r28             /* Disable interrupts */
1142         li      r4,0
1143         ori     r4,r4,MSR_EE
1144         andc    r28,r28,r4
1145         SYNC                    /* Some chip revs need this... */
1146         mtmsr   r28
1147         SYNC
1148         lwz     r2,_CTR(r1)
1149         lwz     r0,_LINK(r1)
1150         mtctr   r2
1151         mtlr    r0
1152         lwz     r2,_XER(r1)
1153         lwz     r0,_CCR(r1)
1154         mtspr   XER,r2
1155         mtcrf   0xFF,r0
1156         REST_10GPRS(3, r1)
1157         REST_10GPRS(13, r1)
1158         REST_8GPRS(23, r1)
1159         REST_GPR(31, r1)
1160         lwz     r2,_NIP(r1)     /* Restore environment */
1161         lwz     r0,_MSR(r1)
1162         mtspr   SRR0,r2
1163         mtspr   SRR1,r0
1164         lwz     r0,GPR0(r1)
1165         lwz     r2,GPR2(r1)
1166         lwz     r1,GPR1(r1)
1167         SYNC
1168         rfi
1169
1170 crit_return:
1171         mfmsr   r28             /* Disable interrupts */
1172         li      r4,0
1173         ori     r4,r4,MSR_EE
1174         andc    r28,r28,r4
1175         SYNC                    /* Some chip revs need this... */
1176         mtmsr   r28
1177         SYNC
1178         lwz     r2,_CTR(r1)
1179         lwz     r0,_LINK(r1)
1180         mtctr   r2
1181         mtlr    r0
1182         lwz     r2,_XER(r1)
1183         lwz     r0,_CCR(r1)
1184         mtspr   XER,r2
1185         mtcrf   0xFF,r0
1186         REST_10GPRS(3, r1)
1187         REST_10GPRS(13, r1)
1188         REST_8GPRS(23, r1)
1189         REST_GPR(31, r1)
1190         lwz     r2,_NIP(r1)     /* Restore environment */
1191         lwz     r0,_MSR(r1)
1192         mtspr   SPRN_CSRR0,r2
1193         mtspr   SPRN_CSRR1,r0
1194         lwz     r0,GPR0(r1)
1195         lwz     r2,GPR2(r1)
1196         lwz     r1,GPR1(r1)
1197         SYNC
1198         rfci
1199
1200 #ifdef CONFIG_440
1201 mck_return:
1202         mfmsr   r28             /* Disable interrupts */
1203         li      r4,0
1204         ori     r4,r4,MSR_EE
1205         andc    r28,r28,r4
1206         SYNC                    /* Some chip revs need this... */
1207         mtmsr   r28
1208         SYNC
1209         lwz     r2,_CTR(r1)
1210         lwz     r0,_LINK(r1)
1211         mtctr   r2
1212         mtlr    r0
1213         lwz     r2,_XER(r1)
1214         lwz     r0,_CCR(r1)
1215         mtspr   XER,r2
1216         mtcrf   0xFF,r0
1217         REST_10GPRS(3, r1)
1218         REST_10GPRS(13, r1)
1219         REST_8GPRS(23, r1)
1220         REST_GPR(31, r1)
1221         lwz     r2,_NIP(r1)     /* Restore environment */
1222         lwz     r0,_MSR(r1)
1223         mtspr   SPRN_MCSRR0,r2
1224         mtspr   SPRN_MCSRR1,r0
1225         lwz     r0,GPR0(r1)
1226         lwz     r2,GPR2(r1)
1227         lwz     r1,GPR1(r1)
1228         SYNC
1229         rfmci
1230 #endif /* CONFIG_440 */
1231
1232
1233         .globl get_pvr
1234 get_pvr:
1235         mfspr   r3, PVR
1236         blr
1237
1238 /*------------------------------------------------------------------------------- */
1239 /* Function:     out16 */
1240 /* Description:  Output 16 bits */
1241 /*------------------------------------------------------------------------------- */
1242         .globl  out16
1243 out16:
1244         sth     r4,0x0000(r3)
1245         blr
1246
1247 /*------------------------------------------------------------------------------- */
1248 /* Function:     out16r */
1249 /* Description:  Byte reverse and output 16 bits */
1250 /*------------------------------------------------------------------------------- */
1251         .globl  out16r
1252 out16r:
1253         sthbrx  r4,r0,r3
1254         blr
1255
1256 /*------------------------------------------------------------------------------- */
1257 /* Function:     out32r */
1258 /* Description:  Byte reverse and output 32 bits */
1259 /*------------------------------------------------------------------------------- */
1260         .globl  out32r
1261 out32r:
1262         stwbrx  r4,r0,r3
1263         blr
1264
1265 /*------------------------------------------------------------------------------- */
1266 /* Function:     in16 */
1267 /* Description:  Input 16 bits */
1268 /*------------------------------------------------------------------------------- */
1269         .globl  in16
1270 in16:
1271         lhz     r3,0x0000(r3)
1272         blr
1273
1274 /*------------------------------------------------------------------------------- */
1275 /* Function:     in16r */
1276 /* Description:  Input 16 bits and byte reverse */
1277 /*------------------------------------------------------------------------------- */
1278         .globl  in16r
1279 in16r:
1280         lhbrx   r3,r0,r3
1281         blr
1282
1283 /*------------------------------------------------------------------------------- */
1284 /* Function:     in32r */
1285 /* Description:  Input 32 bits and byte reverse */
1286 /*------------------------------------------------------------------------------- */
1287         .globl  in32r
1288 in32r:
1289         lwbrx   r3,r0,r3
1290         blr
1291
1292 #if !defined(CONFIG_SPL_BUILD)
1293 /*
1294  * void relocate_code (addr_sp, gd, addr_moni)
1295  *
1296  * This "function" does not return, instead it continues in RAM
1297  * after relocating the monitor code.
1298  *
1299  * r3 = Relocated stack pointer
1300  * r4 = Relocated global data pointer
1301  * r5 = Relocated text pointer
1302  */
1303         .globl  relocate_code
1304 relocate_code:
1305 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1306         /*
1307          * We need to flush the initial global data (gd_t) and bd_info
1308          * before the dcache will be invalidated.
1309          */
1310
1311         /* Save registers */
1312         mr      r9, r3
1313         mr      r10, r4
1314         mr      r11, r5
1315
1316         /*
1317          * Flush complete dcache, this is faster than flushing the
1318          * ranges for global_data and bd_info instead.
1319          */
1320         bl      flush_dcache
1321
1322 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1323         /*
1324          * Undo the earlier data cache set-up for the primordial stack and
1325          * data area. First, invalidate the data cache and then disable data
1326          * cacheability for that area. Finally, restore the EBC values, if
1327          * any.
1328          */
1329
1330         /* Invalidate the primordial stack and data area in cache */
1331         lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
1332         ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1333
1334         lis     r4, CONFIG_SYS_INIT_RAM_SIZE@h
1335         ori     r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1336         add     r4, r4, r3
1337
1338         bl      invalidate_dcache_range
1339
1340         /* Disable cacheability for the region */
1341         mfdccr  r3
1342         lis     r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1343         ori     r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1344         and     r3, r3, r4
1345         mtdccr  r3
1346
1347         /* Restore the EBC parameters */
1348         li      r3, PBxAP
1349         mtdcr   EBC0_CFGADDR, r3
1350         lis     r3, PBxAP_VAL@h
1351         ori     r3, r3, PBxAP_VAL@l
1352         mtdcr   EBC0_CFGDATA, r3
1353
1354         li      r3, PBxCR
1355         mtdcr   EBC0_CFGADDR, r3
1356         lis     r3, PBxCR_VAL@h
1357         ori     r3, r3, PBxCR_VAL@l
1358         mtdcr   EBC0_CFGDATA, r3
1359 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1360
1361         /* Restore registers */
1362         mr      r3, r9
1363         mr      r4, r10
1364         mr      r5, r11
1365 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1366
1367 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1368         /*
1369          * Unlock the previously locked d-cache
1370          */
1371         msync
1372         isync
1373         /* set TFLOOR/NFLOOR to 0 again */
1374         lis     r6,0x0001
1375         ori     r6,r6,0xf800
1376         mtspr   SPRN_DVLIM,r6
1377         lis     r6,0x0000
1378         ori     r6,r6,0x0000
1379         mtspr   SPRN_DNV0,r6
1380         mtspr   SPRN_DNV1,r6
1381         mtspr   SPRN_DNV2,r6
1382         mtspr   SPRN_DNV3,r6
1383         mtspr   SPRN_DTV0,r6
1384         mtspr   SPRN_DTV1,r6
1385         mtspr   SPRN_DTV2,r6
1386         mtspr   SPRN_DTV3,r6
1387         msync
1388         isync
1389
1390         /* Invalidate data cache, now no longer our stack */
1391         dccci   0,0
1392         sync
1393         isync
1394 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1395
1396         /*
1397          * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1398          * to speed up the boot process. Now this cache needs to be disabled.
1399          */
1400 #if defined(CONFIG_440)
1401         /* Clear all potential pending exceptions */
1402         mfspr   r1,SPRN_MCSR
1403         mtspr   SPRN_MCSR,r1
1404         addi    r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH     /* Use defined TLB */
1405         tlbre   r0,r1,0x0002            /* Read contents */
1406         ori     r0,r0,0x0c00            /* Or in the inhibit, write through bit */
1407         tlbwe   r0,r1,0x0002            /* Save it out */
1408         sync
1409         isync
1410 #endif /* defined(CONFIG_440) */
1411         mr      r1,  r3         /* Set new stack pointer                */
1412         mr      r9,  r4         /* Save copy of Init Data pointer       */
1413         mr      r10, r5         /* Save copy of Destination Address     */
1414
1415         GET_GOT
1416         mr      r3,  r5                         /* Destination Address  */
1417         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
1418         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
1419         lwz     r5, GOT(__init_end)
1420         sub     r5, r5, r4
1421         li      r6, L1_CACHE_BYTES              /* Cache Line Size      */
1422
1423         /*
1424          * Fix GOT pointer:
1425          *
1426          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1427          *
1428          * Offset:
1429          */
1430         sub     r15, r10, r4
1431
1432         /* First our own GOT */
1433         add     r12, r12, r15
1434         /* then the one used by the C code */
1435         add     r30, r30, r15
1436
1437         /*
1438          * Now relocate code
1439          */
1440
1441         cmplw   cr1,r3,r4
1442         addi    r0,r5,3
1443         srwi.   r0,r0,2
1444         beq     cr1,4f          /* In place copy is not necessary       */
1445         beq     7f              /* Protect against 0 count              */
1446         mtctr   r0
1447         bge     cr1,2f
1448
1449         la      r8,-4(r4)
1450         la      r7,-4(r3)
1451 1:      lwzu    r0,4(r8)
1452         stwu    r0,4(r7)
1453         bdnz    1b
1454         b       4f
1455
1456 2:      slwi    r0,r0,2
1457         add     r8,r4,r0
1458         add     r7,r3,r0
1459 3:      lwzu    r0,-4(r8)
1460         stwu    r0,-4(r7)
1461         bdnz    3b
1462
1463 /*
1464  * Now flush the cache: note that we must start from a cache aligned
1465  * address. Otherwise we might miss one cache line.
1466  */
1467 4:      cmpwi   r6,0
1468         add     r5,r3,r5
1469         beq     7f              /* Always flush prefetch queue in any case */
1470         subi    r0,r6,1
1471         andc    r3,r3,r0
1472         mr      r4,r3
1473 5:      dcbst   0,r4
1474         add     r4,r4,r6
1475         cmplw   r4,r5
1476         blt     5b
1477         sync                    /* Wait for all dcbst to complete on bus */
1478         mr      r4,r3
1479 6:      icbi    0,r4
1480         add     r4,r4,r6
1481         cmplw   r4,r5
1482         blt     6b
1483 7:      sync                    /* Wait for all icbi to complete on bus */
1484         isync
1485
1486 /*
1487  * We are done. Do not return, instead branch to second part of board
1488  * initialization, now running from RAM.
1489  */
1490
1491         addi    r0, r10, in_ram - _start + _START_OFFSET
1492         mtlr    r0
1493         blr                             /* NEVER RETURNS! */
1494
1495 in_ram:
1496
1497         /*
1498          * Relocation Function, r12 point to got2+0x8000
1499          *
1500          * Adjust got2 pointers, no need to check for 0, this code
1501          * already puts a few entries in the table.
1502          */
1503         li      r0,__got2_entries@sectoff@l
1504         la      r3,GOT(_GOT2_TABLE_)
1505         lwz     r11,GOT(_GOT2_TABLE_)
1506         mtctr   r0
1507         sub     r11,r3,r11
1508         addi    r3,r3,-4
1509 1:      lwzu    r0,4(r3)
1510         cmpwi   r0,0
1511         beq-    2f
1512         add     r0,r0,r11
1513         stw     r0,0(r3)
1514 2:      bdnz    1b
1515
1516         /*
1517          * Now adjust the fixups and the pointers to the fixups
1518          * in case we need to move ourselves again.
1519          */
1520         li      r0,__fixup_entries@sectoff@l
1521         lwz     r3,GOT(_FIXUP_TABLE_)
1522         cmpwi   r0,0
1523         mtctr   r0
1524         addi    r3,r3,-4
1525         beq     4f
1526 3:      lwzu    r4,4(r3)
1527         lwzux   r0,r4,r11
1528         cmpwi   r0,0
1529         add     r0,r0,r11
1530         stw     r4,0(r3)
1531         beq-    5f
1532         stw     r0,0(r4)
1533 5:      bdnz    3b
1534 4:
1535 clear_bss:
1536         /*
1537          * Now clear BSS segment
1538          */
1539         lwz     r3,GOT(__bss_start)
1540         lwz     r4,GOT(__bss_end)
1541
1542         cmplw   0, r3, r4
1543         beq     7f
1544
1545         li      r0, 0
1546
1547         andi.   r5, r4, 3
1548         beq     6f
1549         sub     r4, r4, r5
1550         mtctr   r5
1551         mr      r5, r4
1552 5:      stb     r0, 0(r5)
1553         addi    r5, r5, 1
1554         bdnz    5b
1555 6:
1556         stw     r0, 0(r3)
1557         addi    r3, r3, 4
1558         cmplw   0, r3, r4
1559         bne     6b
1560
1561 7:
1562         mr      r3, r9          /* Init Data pointer            */
1563         mr      r4, r10         /* Destination Address          */
1564         bl      board_init_r
1565
1566         /*
1567          * Copy exception vector code to low memory
1568          *
1569          * r3: dest_addr
1570          * r7: source address, r8: end address, r9: target address
1571          */
1572         .globl  trap_init
1573 trap_init:
1574         mflr    r4                      /* save link register           */
1575         GET_GOT
1576         lwz     r7, GOT(_start_of_vectors)
1577         lwz     r8, GOT(_end_of_vectors)
1578
1579         li      r9, 0x100               /* reset vector always at 0x100 */
1580
1581         cmplw   0, r7, r8
1582         bgelr                           /* return if r7>=r8 - just in case */
1583 1:
1584         lwz     r0, 0(r7)
1585         stw     r0, 0(r9)
1586         addi    r7, r7, 4
1587         addi    r9, r9, 4
1588         cmplw   0, r7, r8
1589         bne     1b
1590
1591         /*
1592          * relocate `hdlr' and `int_return' entries
1593          */
1594         li      r7, .L_MachineCheck - _start + _START_OFFSET
1595         li      r8, Alignment - _start + _START_OFFSET
1596 2:
1597         bl      trap_reloc
1598         addi    r7, r7, 0x100           /* next exception vector */
1599         cmplw   0, r7, r8
1600         blt     2b
1601
1602         li      r7, .L_Alignment - _start + _START_OFFSET
1603         bl      trap_reloc
1604
1605         li      r7, .L_ProgramCheck - _start + _START_OFFSET
1606         bl      trap_reloc
1607
1608 #ifdef CONFIG_440
1609         li      r7, .L_FPUnavailable - _start + _START_OFFSET
1610         bl      trap_reloc
1611
1612         li      r7, .L_Decrementer - _start + _START_OFFSET
1613         bl      trap_reloc
1614
1615         li      r7, .L_APU - _start + _START_OFFSET
1616         bl      trap_reloc
1617
1618         li      r7, .L_InstructionTLBError - _start + _START_OFFSET
1619         bl      trap_reloc
1620
1621         li      r7, .L_DataTLBError - _start + _START_OFFSET
1622         bl      trap_reloc
1623 #else /* CONFIG_440 */
1624         li      r7, .L_PIT - _start + _START_OFFSET
1625         bl      trap_reloc
1626
1627         li      r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1628         bl      trap_reloc
1629
1630         li      r7, .L_DataTLBMiss - _start + _START_OFFSET
1631         bl      trap_reloc
1632 #endif /* CONFIG_440 */
1633
1634         li      r7, .L_DebugBreakpoint - _start + _START_OFFSET
1635         bl      trap_reloc
1636
1637 #if !defined(CONFIG_440)
1638         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1639         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1640         mtmsr   r7                      /* change MSR */
1641 #else
1642         bl      __440_msr_set
1643         b       __440_msr_continue
1644
1645 __440_msr_set:
1646         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1647         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1648         mtspr   SPRN_SRR1,r7
1649         mflr    r7
1650         mtspr   SPRN_SRR0,r7
1651         rfi
1652 __440_msr_continue:
1653 #endif
1654
1655         mtlr    r4                      /* restore link register        */
1656         blr
1657 #endif /* CONFIG_SPL_BUILD */
1658
1659 #if defined(CONFIG_440)
1660 /*----------------------------------------------------------------------------+
1661 | dcbz_area.
1662 +----------------------------------------------------------------------------*/
1663         function_prolog(dcbz_area)
1664         rlwinm. r5,r4,0,27,31
1665         rlwinm  r5,r4,27,5,31
1666         beq     ..d_ra2
1667         addi    r5,r5,0x0001
1668 ..d_ra2:mtctr   r5
1669 ..d_ag2:dcbz    r0,r3
1670         addi    r3,r3,32
1671         bdnz    ..d_ag2
1672         sync
1673         blr
1674         function_epilog(dcbz_area)
1675 #endif /* CONFIG_440 */
1676 #endif /* CONFIG_NAND_SPL */
1677
1678 /*------------------------------------------------------------------------------- */
1679 /* Function:     in8 */
1680 /* Description:  Input 8 bits */
1681 /*------------------------------------------------------------------------------- */
1682         .globl  in8
1683 in8:
1684         lbz     r3,0x0000(r3)
1685         blr
1686
1687 /*------------------------------------------------------------------------------- */
1688 /* Function:     out8 */
1689 /* Description:  Output 8 bits */
1690 /*------------------------------------------------------------------------------- */
1691         .globl  out8
1692 out8:
1693         stb     r4,0x0000(r3)
1694         blr
1695
1696 /*------------------------------------------------------------------------------- */
1697 /* Function:     out32 */
1698 /* Description:  Output 32 bits */
1699 /*------------------------------------------------------------------------------- */
1700         .globl  out32
1701 out32:
1702         stw     r4,0x0000(r3)
1703         blr
1704
1705 /*------------------------------------------------------------------------------- */
1706 /* Function:     in32 */
1707 /* Description:  Input 32 bits */
1708 /*------------------------------------------------------------------------------- */
1709         .globl  in32
1710 in32:
1711         lwz     3,0x0000(3)
1712         blr
1713
1714 /**************************************************************************/
1715 /* PPC405EP specific stuff                                                */
1716 /**************************************************************************/
1717 #ifdef CONFIG_405EP
1718 ppc405ep_init:
1719
1720 #ifdef CONFIG_BUBINGA
1721         /*
1722          * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1723          * function) to support FPGA and NVRAM accesses below.
1724          */
1725
1726         lis     r3,GPIO0_OSRH@h         /* config GPIO output select */
1727         ori     r3,r3,GPIO0_OSRH@l
1728         lis     r4,CONFIG_SYS_GPIO0_OSRH@h
1729         ori     r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1730         stw     r4,0(r3)
1731         lis     r3,GPIO0_OSRL@h
1732         ori     r3,r3,GPIO0_OSRL@l
1733         lis     r4,CONFIG_SYS_GPIO0_OSRL@h
1734         ori     r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1735         stw     r4,0(r3)
1736
1737         lis     r3,GPIO0_ISR1H@h        /* config GPIO input select */
1738         ori     r3,r3,GPIO0_ISR1H@l
1739         lis     r4,CONFIG_SYS_GPIO0_ISR1H@h
1740         ori     r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1741         stw     r4,0(r3)
1742         lis     r3,GPIO0_ISR1L@h
1743         ori     r3,r3,GPIO0_ISR1L@l
1744         lis     r4,CONFIG_SYS_GPIO0_ISR1L@h
1745         ori     r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1746         stw     r4,0(r3)
1747
1748         lis     r3,GPIO0_TSRH@h         /* config GPIO three-state select */
1749         ori     r3,r3,GPIO0_TSRH@l
1750         lis     r4,CONFIG_SYS_GPIO0_TSRH@h
1751         ori     r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1752         stw     r4,0(r3)
1753         lis     r3,GPIO0_TSRL@h
1754         ori     r3,r3,GPIO0_TSRL@l
1755         lis     r4,CONFIG_SYS_GPIO0_TSRL@h
1756         ori     r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1757         stw     r4,0(r3)
1758
1759         lis     r3,GPIO0_TCR@h          /* config GPIO driver output enables */
1760         ori     r3,r3,GPIO0_TCR@l
1761         lis     r4,CONFIG_SYS_GPIO0_TCR@h
1762         ori     r4,r4,CONFIG_SYS_GPIO0_TCR@l
1763         stw     r4,0(r3)
1764
1765         li      r3,PB1AP                /* program EBC bank 1 for RTC access */
1766         mtdcr   EBC0_CFGADDR,r3
1767         lis     r3,CONFIG_SYS_EBC_PB1AP@h
1768         ori     r3,r3,CONFIG_SYS_EBC_PB1AP@l
1769         mtdcr   EBC0_CFGDATA,r3
1770         li      r3,PB1CR
1771         mtdcr   EBC0_CFGADDR,r3
1772         lis     r3,CONFIG_SYS_EBC_PB1CR@h
1773         ori     r3,r3,CONFIG_SYS_EBC_PB1CR@l
1774         mtdcr   EBC0_CFGDATA,r3
1775
1776         li      r3,PB1AP                /* program EBC bank 1 for RTC access */
1777         mtdcr   EBC0_CFGADDR,r3
1778         lis     r3,CONFIG_SYS_EBC_PB1AP@h
1779         ori     r3,r3,CONFIG_SYS_EBC_PB1AP@l
1780         mtdcr   EBC0_CFGDATA,r3
1781         li      r3,PB1CR
1782         mtdcr   EBC0_CFGADDR,r3
1783         lis     r3,CONFIG_SYS_EBC_PB1CR@h
1784         ori     r3,r3,CONFIG_SYS_EBC_PB1CR@l
1785         mtdcr   EBC0_CFGDATA,r3
1786
1787         li      r3,PB4AP                /* program EBC bank 4 for FPGA access */
1788         mtdcr   EBC0_CFGADDR,r3
1789         lis     r3,CONFIG_SYS_EBC_PB4AP@h
1790         ori     r3,r3,CONFIG_SYS_EBC_PB4AP@l
1791         mtdcr   EBC0_CFGDATA,r3
1792         li      r3,PB4CR
1793         mtdcr   EBC0_CFGADDR,r3
1794         lis     r3,CONFIG_SYS_EBC_PB4CR@h
1795         ori     r3,r3,CONFIG_SYS_EBC_PB4CR@l
1796         mtdcr   EBC0_CFGDATA,r3
1797 #endif
1798
1799         /*
1800         !-----------------------------------------------------------------------
1801         ! Check to see if chip is in bypass mode.
1802         ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1803         ! CPU reset   Otherwise, skip this step and keep going.
1804         ! Note:  Running BIOS in bypass mode is not supported since PLB speed
1805         !        will not be fast enough for the SDRAM (min 66MHz)
1806         !-----------------------------------------------------------------------
1807         */
1808         mfdcr   r5, CPC0_PLLMR1
1809         rlwinm  r4,r5,1,0x1             /* get system clock source (SSCS) */
1810         cmpi    cr0,0,r4,0x1
1811
1812         beq    pll_done                 /* if SSCS =b'1' then PLL has */
1813                                         /* already been set */
1814                                         /* and CPU has been reset */
1815                                         /* so skip to next section */
1816
1817 #ifdef CONFIG_BUBINGA
1818         /*
1819         !-----------------------------------------------------------------------
1820         ! Read NVRAM to get value to write in PLLMR.
1821         ! If value has not been correctly saved, write default value
1822         ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1823         ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1824         !
1825         ! WARNING:  This code assumes the first three words in the nvram_t
1826         !           structure in openbios.h.  Changing the beginning of
1827         !           the structure will break this code.
1828         !
1829         !-----------------------------------------------------------------------
1830         */
1831         addis   r3,0,NVRAM_BASE@h
1832         addi    r3,r3,NVRAM_BASE@l
1833
1834         lwz     r4, 0(r3)
1835         addis   r5,0,NVRVFY1@h
1836         addi    r5,r5,NVRVFY1@l
1837         cmp     cr0,0,r4,r5             /* Compare 1st NVRAM Magic number*/
1838         bne     ..no_pllset
1839         addi    r3,r3,4
1840         lwz     r4, 0(r3)
1841         addis   r5,0,NVRVFY2@h
1842         addi    r5,r5,NVRVFY2@l
1843         cmp     cr0,0,r4,r5             /* Compare 2 NVRAM Magic number */
1844         bne     ..no_pllset
1845         addi    r3,r3,8                 /* Skip over conf_size */
1846         lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
1847         lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
1848         rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
1849         cmpi     cr0,0,r5,1             /* See if PLL is locked */
1850         beq     pll_write
1851 ..no_pllset:
1852 #endif /* CONFIG_BUBINGA */
1853
1854 #ifdef CONFIG_TAIHU
1855         mfdcr   r4, CPC0_BOOT
1856         andi.   r5, r4, CPC0_BOOT_SEP@l
1857         bne     strap_1                 /* serial eeprom present */
1858         addis   r5,0,CPLD_REG0_ADDR@h
1859         ori     r5,r5,CPLD_REG0_ADDR@l
1860         andi.   r5, r5, 0x10
1861         bne     _pci_66mhz
1862 #endif /* CONFIG_TAIHU */
1863
1864 #if defined(CONFIG_ZEUS)
1865         mfdcr   r4, CPC0_BOOT
1866         andi.   r5, r4, CPC0_BOOT_SEP@l
1867         bne     strap_1                 /* serial eeprom present */
1868         lis     r3,0x0000
1869         addi    r3,r3,0x3030
1870         lis     r4,0x8042
1871         addi    r4,r4,0x223e
1872         b       1f
1873 strap_1:
1874         mfdcr   r3, CPC0_PLLMR0
1875         mfdcr   r4, CPC0_PLLMR1
1876         b       1f
1877 #endif
1878
1879         addis   r3,0,PLLMR0_DEFAULT@h   /* PLLMR0 default value */
1880         ori     r3,r3,PLLMR0_DEFAULT@l  /* */
1881         addis   r4,0,PLLMR1_DEFAULT@h   /* PLLMR1 default value */
1882         ori     r4,r4,PLLMR1_DEFAULT@l  /* */
1883
1884 #ifdef CONFIG_TAIHU
1885         b       1f
1886 _pci_66mhz:
1887         addis   r3,0,PLLMR0_DEFAULT_PCI66@h
1888         ori     r3,r3,PLLMR0_DEFAULT_PCI66@l
1889         addis   r4,0,PLLMR1_DEFAULT_PCI66@h
1890         ori     r4,r4,PLLMR1_DEFAULT_PCI66@l
1891         b       1f
1892 strap_1:
1893         mfdcr   r3, CPC0_PLLMR0
1894         mfdcr   r4, CPC0_PLLMR1
1895 #endif /* CONFIG_TAIHU */
1896
1897 1:
1898         b       pll_write               /* Write the CPC0_PLLMR with new value */
1899
1900 pll_done:
1901         /*
1902         !-----------------------------------------------------------------------
1903         ! Clear Soft Reset Register
1904         ! This is needed to enable PCI if not booting from serial EPROM
1905         !-----------------------------------------------------------------------
1906                 */
1907         addi    r3, 0, 0x0
1908         mtdcr   CPC0_SRR, r3
1909
1910         addis    r3,0,0x0010
1911         mtctr   r3
1912 pci_wait:
1913         bdnz    pci_wait
1914
1915         blr                             /* return to main code */
1916
1917 /*
1918 !-----------------------------------------------------------------------------
1919 ! Function:     pll_write
1920 ! Description:  Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1921 !               That is:
1922 !                         1.  Pll is first disabled (de-activated by putting in bypass mode)
1923 !                         2.  PLL is reset
1924 !                         3.  Clock dividers are set while PLL is held in reset and bypassed
1925 !                         4.  PLL Reset is cleared
1926 !                         5.  Wait 100us for PLL to lock
1927 !                         6.  A core reset is performed
1928 ! Input: r3 = Value to write to CPC0_PLLMR0
1929 ! Input: r4 = Value to write to CPC0_PLLMR1
1930 ! Output r3 = none
1931 !-----------------------------------------------------------------------------
1932 */
1933         .globl  pll_write
1934 pll_write:
1935         mfdcr  r5, CPC0_UCR
1936         andis. r5,r5,0xFFFF
1937         ori    r5,r5,0x0101             /* Stop the UART clocks */
1938         mtdcr  CPC0_UCR,r5              /* Before changing PLL */
1939
1940         mfdcr  r5, CPC0_PLLMR1
1941         rlwinm r5,r5,0,0x7FFFFFFF       /* Disable PLL */
1942         mtdcr   CPC0_PLLMR1,r5
1943         oris   r5,r5,0x4000             /* Set PLL Reset */
1944         mtdcr   CPC0_PLLMR1,r5
1945
1946         mtdcr   CPC0_PLLMR0,r3          /* Set clock dividers */
1947         rlwinm r5,r4,0,0x3FFFFFFF       /* Reset & Bypass new PLL dividers */
1948         oris   r5,r5,0x4000             /* Set PLL Reset */
1949         mtdcr   CPC0_PLLMR1,r5          /* Set clock dividers */
1950         rlwinm r5,r5,0,0xBFFFFFFF       /* Clear PLL Reset */
1951         mtdcr   CPC0_PLLMR1,r5
1952
1953                 /*
1954         ! Wait min of 100us for PLL to lock.
1955         ! See CMOS 27E databook for more info.
1956         ! At 200MHz, that means waiting 20,000 instructions
1957                  */
1958         addi    r3,0,20000              /* 2000 = 0x4e20 */
1959         mtctr   r3
1960 pll_wait:
1961         bdnz    pll_wait
1962
1963         oris   r5,r5,0x8000             /* Enable PLL */
1964         mtdcr   CPC0_PLLMR1,r5          /* Engage */
1965
1966         /*
1967          * Reset CPU to guarantee timings are OK
1968          * Not sure if this is needed...
1969          */
1970         addis r3,0,0x1000
1971         mtspr SPRN_DBCR0,r3             /* This will cause a CPU core reset, and */
1972                                         /* execution will continue from the poweron */
1973                                         /* vector of 0xfffffffc */
1974 #endif /* CONFIG_405EP */
1975
1976 #if defined(CONFIG_440)
1977 /*----------------------------------------------------------------------------+
1978 | mttlb3.
1979 +----------------------------------------------------------------------------*/
1980         function_prolog(mttlb3)
1981         TLBWE(4,3,2)
1982         blr
1983         function_epilog(mttlb3)
1984
1985 /*----------------------------------------------------------------------------+
1986 | mftlb3.
1987 +----------------------------------------------------------------------------*/
1988         function_prolog(mftlb3)
1989         TLBRE(3,3,2)
1990         blr
1991         function_epilog(mftlb3)
1992
1993 /*----------------------------------------------------------------------------+
1994 | mttlb2.
1995 +----------------------------------------------------------------------------*/
1996         function_prolog(mttlb2)
1997         TLBWE(4,3,1)
1998         blr
1999         function_epilog(mttlb2)
2000
2001 /*----------------------------------------------------------------------------+
2002 | mftlb2.
2003 +----------------------------------------------------------------------------*/
2004         function_prolog(mftlb2)
2005         TLBRE(3,3,1)
2006         blr
2007         function_epilog(mftlb2)
2008
2009 /*----------------------------------------------------------------------------+
2010 | mttlb1.
2011 +----------------------------------------------------------------------------*/
2012         function_prolog(mttlb1)
2013         TLBWE(4,3,0)
2014         blr
2015         function_epilog(mttlb1)
2016
2017 /*----------------------------------------------------------------------------+
2018 | mftlb1.
2019 +----------------------------------------------------------------------------*/
2020         function_prolog(mftlb1)
2021         TLBRE(3,3,0)
2022         blr
2023         function_epilog(mftlb1)
2024 #endif /* CONFIG_440 */
2025
2026 #if defined(CONFIG_NAND_SPL)
2027 /*
2028  * void nand_boot_relocate(dst, src, bytes)
2029  *
2030  * r3 = Destination address to copy code to (in SDRAM)
2031  * r4 = Source address to copy code from
2032  * r5 = size to copy in bytes
2033  */
2034 nand_boot_relocate:
2035         mr      r6,r3
2036         mr      r7,r4
2037         mflr    r8
2038
2039         /*
2040          * Copy SPL from icache into SDRAM
2041          */
2042         subi    r3,r3,4
2043         subi    r4,r4,4
2044         srwi    r5,r5,2
2045         mtctr   r5
2046 ..spl_loop:
2047         lwzu    r0,4(r4)
2048         stwu    r0,4(r3)
2049         bdnz    ..spl_loop
2050
2051         /*
2052          * Calculate "corrected" link register, so that we "continue"
2053          * in execution in destination range
2054          */
2055         sub     r3,r7,r6        /* r3 = src - dst */
2056         sub     r8,r8,r3        /* r8 = link-reg - (src - dst) */
2057         mtlr    r8
2058         blr
2059
2060 nand_boot_common:
2061         /*
2062          * First initialize SDRAM. It has to be available *before* calling
2063          * nand_boot().
2064          */
2065         lis     r3,CONFIG_SYS_SDRAM_BASE@h
2066         ori     r3,r3,CONFIG_SYS_SDRAM_BASE@l
2067         bl      initdram
2068
2069         /*
2070          * Now copy the 4k SPL code into SDRAM and continue execution
2071          * from there.
2072          */
2073         lis     r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2074         ori     r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2075         lis     r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2076         ori     r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2077         lis     r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2078         ori     r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2079         bl      nand_boot_relocate
2080
2081         /*
2082          * We're running from SDRAM now!!!
2083          *
2084          * It is necessary for 4xx systems to relocate from running at
2085          * the original location (0xfffffxxx) to somewhere else (SDRAM
2086          * preferably). This is because CS0 needs to be reconfigured for
2087          * NAND access. And we can't reconfigure this CS when currently
2088          * "running" from it.
2089          */
2090
2091         /*
2092          * Finally call nand_boot() to load main NAND U-Boot image from
2093          * NAND and jump to it.
2094          */
2095         bl      nand_boot               /* will not return */
2096 #endif /* CONFIG_NAND_SPL */