arch/powerpc/cpu/ppc4xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *  Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
   6  *  Copyright (c) 2008 Nuovation System Designs, LLC
   7  *    Grant Erickson <gerickson@nuovations.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 /*------------------------------------------------------------------------------+
  28  *   This source code is dual-licensed.  You may use it under the terms of the
  29  *   GNU General Public License version 2, or under the license below.
  30  *
  31  *       This source code has been made available to you by IBM on an AS-IS
  32  *       basis.  Anyone receiving this source is licensed under IBM
  33  *       copyrights to use it in any way he or she deems fit, including
  34  *       copying it, modifying it, compiling it, and redistributing it either
  35  *       with or without modifications.  No license under IBM patents or
  36  *       patent applications is to be implied by the copyright license.
  37  *
  38  *       Any user of this software should understand that IBM cannot provide
  39  *       technical support for this software and will not be responsible for
  40  *       any consequences resulting from the use of this software.
  41  *
  42  *       Any person who transfers this source code or any derivative work
  43  *       must include the IBM copyright notice, this paragraph, and the
  44  *       preceding two paragraphs in the transferred software.
  45  *
  46  *       COPYRIGHT   I B M   CORPORATION 1995
  47  *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  48  *-------------------------------------------------------------------------------
  49  */
  50
  51 /*
  52  * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
  53  *
  54  * The following description only applies to the NOR flash style booting.
  55  * NAND booting is different. For more details about NAND booting on 4xx
  56  * take a look at doc/README.nand-boot-ppc440.
  57  *
  58  * The CPU starts at address 0xfffffffc (last word in the address space).
  59  * The U-Boot image therefore has to be located in the "upper" area of the
  60  * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
  61  * the boot chip-select (CS0) is quite big and covers this area. On the
  62  * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
  63  * reconfigure this CS0 (and other chip-selects as well when configured
  64  * this way) in the boot process to the "correct" values matching the
  65  * board layout.
  66  */
  67
  68 #include <asm-offsets.h>
  69 #include <config.h>
  70 #include <asm/ppc4xx.h>
  71 #include <version.h>
  72
  73 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  74
  75 #include <ppc_asm.tmpl>
  76 #include <ppc_defs.h>
  77
  78 #include <asm/cache.h>
  79 #include <asm/mmu.h>
  80 #include <asm/ppc4xx-isram.h>
  81
  82 #ifdef CONFIG_SYS_INIT_DCACHE_CS
  83 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
  84 #  define PBxAP PB1AP
  85 #  define PBxCR PB0CR
  86 #  if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
  87 #   define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
  88 #   define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
  89 #  endif
  90 # endif
  91 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
  92 #  define PBxAP PB1AP
  93 #  define PBxCR PB1CR
  94 #  if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
  95 #   define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
  96 #   define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
  97 #  endif
  98 # endif
  99 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
 100 #  define PBxAP PB2AP
 101 #  define PBxCR PB2CR
 102 #  if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
 103 #   define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
 104 #   define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
 105 #  endif
 106 # endif
 107 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
 108 #  define PBxAP PB3AP
 109 #  define PBxCR PB3CR
 110 #  if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
 111 #   define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
 112 #   define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
 113 #  endif
 114 # endif
 115 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
 116 #  define PBxAP PB4AP
 117 #  define PBxCR PB4CR
 118 #  if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
 119 #   define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
 120 #   define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
 121 #  endif
 122 # endif
 123 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
 124 #  define PBxAP PB5AP
 125 #  define PBxCR PB5CR
 126 #  if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
 127 #   define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
 128 #   define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
 129 #  endif
 130 # endif
 131 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
 132 #  define PBxAP PB6AP
 133 #  define PBxCR PB6CR
 134 #  if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
 135 #   define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
 136 #   define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
 137 #  endif
 138 # endif
 139 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
 140 #  define PBxAP PB7AP
 141 #  define PBxCR PB7CR
 142 #  if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
 143 #   define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
 144 #   define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
 145 #  endif
 146 # endif
 147 # ifndef PBxAP_VAL
 148 #  define PBxAP_VAL     0
 149 # endif
 150 # ifndef PBxCR_VAL
 151 #  define PBxCR_VAL     0
 152 # endif
 153 /*
 154  * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
 155  * used as temporary stack pointer for the primordial stack
 156  */
 157 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
 158 #  define CONFIG_SYS_INIT_DCACHE_PBxAR  (EBC_BXAP_BME_DISABLED                  | \
 159                                  EBC_BXAP_TWT_ENCODE(7)                 | \
 160                                  EBC_BXAP_BCE_DISABLE                   | \
 161                                  EBC_BXAP_BCT_2TRANS                    | \
 162                                  EBC_BXAP_CSN_ENCODE(0)                 | \
 163                                  EBC_BXAP_OEN_ENCODE(0)                 | \
 164                                  EBC_BXAP_WBN_ENCODE(0)                 | \
 165                                  EBC_BXAP_WBF_ENCODE(0)                 | \
 166                                  EBC_BXAP_TH_ENCODE(2)                  | \
 167                                  EBC_BXAP_RE_DISABLED                   | \
 168                                  EBC_BXAP_SOR_NONDELAYED                | \
 169                                  EBC_BXAP_BEM_WRITEONLY                 | \
 170                                  EBC_BXAP_PEN_DISABLED)
 171 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
 172 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
 173 #  define CONFIG_SYS_INIT_DCACHE_PBxCR  (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR)  | \
 174                                  EBC_BXCR_BS_64MB                       | \
 175                                  EBC_BXCR_BU_RW                         | \
 176                                  EBC_BXCR_BW_16BIT)
 177 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
 178 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
 179 #  define CONFIG_SYS_INIT_RAM_PATTERN   0xDEADDEAD
 180 # endif
 181 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
 182
 183 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
 184 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
 185 #endif
 186
 187 /*
 188  * Unless otherwise overriden, enable two 128MB cachable instruction regions
 189  * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
 190  * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
 191  */
 192 #if !defined(CONFIG_SYS_FLASH_BASE)
 193 /* If not already defined, set it to the "last" 128MByte region */
 194 # define CONFIG_SYS_FLASH_BASE          0xf8000000
 195 #endif
 196 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
 197 # define CONFIG_SYS_ICACHE_SACR_VALUE           \
 198                 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (  0 << 20)) | \
 199                  PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
 200                  PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
 201 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
 202
 203 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
 204 # define CONFIG_SYS_DCACHE_SACR_VALUE           \
 205                 (0x00000000)
 206 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
 207
 208 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
 209 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0       /* use TLB 0 as default */
 210 #endif
 211
 212 #define function_prolog(func_name)      .text; \
 213                                         .align 2; \
 214                                         .globl func_name; \
 215                                         func_name:
 216 #define function_epilog(func_name)      .type func_name,@function; \
 217                                         .size func_name,.-func_name
 218
 219 /* We don't want the  MMU yet.
 220 */
 221 #undef  MSR_KERNEL
 222 #define MSR_KERNEL ( MSR_ME  )  /* Machine Check */
 223
 224
 225         .extern ext_bus_cntlr_init
 226 #ifdef CONFIG_NAND_U_BOOT
 227         .extern reconfig_tlb0
 228 #endif
 229
 230 /*
 231  * Set up GOT: Global Offset Table
 232  *
 233  * Use r12 to access the GOT
 234  */
 235 #if !defined(CONFIG_NAND_SPL)
 236         START_GOT
 237         GOT_ENTRY(_GOT2_TABLE_)
 238         GOT_ENTRY(_FIXUP_TABLE_)
 239
 240         GOT_ENTRY(_start)
 241         GOT_ENTRY(_start_of_vectors)
 242         GOT_ENTRY(_end_of_vectors)
 243         GOT_ENTRY(transfer_to_handler)
 244
 245         GOT_ENTRY(__init_end)
 246         GOT_ENTRY(__bss_end__)
 247         GOT_ENTRY(__bss_start)
 248         END_GOT
 249 #endif /* CONFIG_NAND_SPL */
 250
 251 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 252         /*
 253          * NAND U-Boot image is started from offset 0
 254          */
 255         .text
 256 #if defined(CONFIG_440)
 257         bl      reconfig_tlb0
 258 #endif
 259         GET_GOT
 260         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 261         bl      board_init_f
 262         /* NOTREACHED - board_init_f() does not return */
 263 #endif
 264
 265 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
 266         /*
 267          * 4xx RAM-booting U-Boot image is started from offset 0
 268          */
 269         .text
 270         bl      _start_440
 271 #endif
 272
 273 /*
 274  * 440 Startup -- on reset only the top 4k of the effective
 275  * address space is mapped in by an entry in the instruction
 276  * and data shadow TLB. The .bootpg section is located in the
 277  * top 4k & does only what's necessary to map in the the rest
 278  * of the boot rom. Once the boot rom is mapped in we can
 279  * proceed with normal startup.
 280  *
 281  * NOTE: CS0 only covers the top 2MB of the effective address
 282  * space after reset.
 283  */
 284
 285 #if defined(CONFIG_440)
 286 #if !defined(CONFIG_NAND_SPL)
 287     .section .bootpg,"ax"
 288 #endif
 289     .globl _start_440
 290
 291 /**************************************************************************/
 292 _start_440:
 293         /*--------------------------------------------------------------------+
 294         | 440EPX BUP Change - Hardware team request
 295         +--------------------------------------------------------------------*/
 296 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 297         sync
 298         nop
 299         nop
 300 #endif
 301         /*----------------------------------------------------------------+
 302         | Core bug fix.  Clear the esr
 303         +-----------------------------------------------------------------*/
 304         li      r0,0
 305         mtspr   SPRN_ESR,r0
 306         /*----------------------------------------------------------------*/
 307         /* Clear and set up some registers. */
 308         /*----------------------------------------------------------------*/
 309         iccci   r0,r0           /* NOTE: operands not used for 440 */
 310         dccci   r0,r0           /* NOTE: operands not used for 440 */
 311         sync
 312         li      r0,0
 313         mtspr   SPRN_SRR0,r0
 314         mtspr   SPRN_SRR1,r0
 315         mtspr   SPRN_CSRR0,r0
 316         mtspr   SPRN_CSRR1,r0
 317         /* NOTE: 440GX adds machine check status regs */
 318 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
 319         mtspr   SPRN_MCSRR0,r0
 320         mtspr   SPRN_MCSRR1,r0
 321         mfspr   r1,SPRN_MCSR
 322         mtspr   SPRN_MCSR,r1
 323 #endif
 324
 325         /*----------------------------------------------------------------*/
 326         /* CCR0 init */
 327         /*----------------------------------------------------------------*/
 328         /* Disable store gathering & broadcast, guarantee inst/data
 329         * cache block touch, force load/store alignment
 330         * (see errata 1.12: 440_33)
 331         */
 332         lis     r1,0x0030       /* store gathering & broadcast disable */
 333         ori     r1,r1,0x6000    /* cache touch */
 334         mtspr   SPRN_CCR0,r1
 335
 336         /*----------------------------------------------------------------*/
 337         /* Initialize debug */
 338         /*----------------------------------------------------------------*/
 339         mfspr   r1,SPRN_DBCR0
 340         andis.  r1, r1, 0x8000  /* test DBCR0[EDM] bit                  */
 341         bne     skip_debug_init /* if set, don't clear debug register   */
 342         mfspr   r1,SPRN_CCR0
 343         ori     r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
 344         mtspr   SPRN_CCR0,r1
 345         mtspr   SPRN_DBCR0,r0
 346         mtspr   SPRN_DBCR1,r0
 347         mtspr   SPRN_DBCR2,r0
 348         mtspr   SPRN_IAC1,r0
 349         mtspr   SPRN_IAC2,r0
 350         mtspr   SPRN_IAC3,r0
 351         mtspr   SPRN_DAC1,r0
 352         mtspr   SPRN_DAC2,r0
 353         mtspr   SPRN_DVC1,r0
 354         mtspr   SPRN_DVC2,r0
 355
 356         mfspr   r1,SPRN_DBSR
 357         mtspr   SPRN_DBSR,r1    /* Clear all valid bits */
 358 skip_debug_init:
 359
 360 #if defined (CONFIG_440SPE)
 361         /*----------------------------------------------------------------+
 362         | Initialize Core Configuration Reg1.
 363         | a. ICDPEI: Record even parity. Normal operation.
 364         | b. ICTPEI: Record even parity. Normal operation.
 365         | c. DCTPEI: Record even parity. Normal operation.
 366         | d. DCDPEI: Record even parity. Normal operation.
 367         | e. DCUPEI: Record even parity. Normal operation.
 368         | f. DCMPEI: Record even parity. Normal operation.
 369         | g. FCOM:   Normal operation
 370         | h. MMUPEI: Record even parity. Normal operation.
 371         | i. FFF:    Flush only as much data as necessary.
 372         | j. TCS:    Timebase increments from CPU clock.
 373         +-----------------------------------------------------------------*/
 374         li      r0,0
 375         mtspr   SPRN_CCR1, r0
 376
 377         /*----------------------------------------------------------------+
 378         | Reset the timebase.
 379         | The previous write to CCR1 sets the timebase source.
 380         +-----------------------------------------------------------------*/
 381         mtspr   SPRN_TBWL, r0
 382         mtspr   SPRN_TBWU, r0
 383 #endif
 384
 385         /*----------------------------------------------------------------*/
 386         /* Setup interrupt vectors */
 387         /*----------------------------------------------------------------*/
 388         mtspr   SPRN_IVPR,r0            /* Vectors start at 0x0000_0000 */
 389         li      r1,0x0100
 390         mtspr   SPRN_IVOR0,r1   /* Critical input */
 391         li      r1,0x0200
 392         mtspr   SPRN_IVOR1,r1   /* Machine check */
 393         li      r1,0x0300
 394         mtspr   SPRN_IVOR2,r1   /* Data storage */
 395         li      r1,0x0400
 396         mtspr   SPRN_IVOR3,r1   /* Instruction storage */
 397         li      r1,0x0500
 398         mtspr   SPRN_IVOR4,r1   /* External interrupt */
 399         li      r1,0x0600
 400         mtspr   SPRN_IVOR5,r1   /* Alignment */
 401         li      r1,0x0700
 402         mtspr   SPRN_IVOR6,r1   /* Program check */
 403         li      r1,0x0800
 404         mtspr   SPRN_IVOR7,r1   /* Floating point unavailable */
 405         li      r1,0x0c00
 406         mtspr   SPRN_IVOR8,r1   /* System call */
 407         li      r1,0x0a00
 408         mtspr   SPRN_IVOR9,r1   /* Auxiliary Processor unavailable */
 409         li      r1,0x0900
 410         mtspr   SPRN_IVOR10,r1  /* Decrementer */
 411         li      r1,0x1300
 412         mtspr   SPRN_IVOR13,r1  /* Data TLB error */
 413         li      r1,0x1400
 414         mtspr   SPRN_IVOR14,r1  /* Instr TLB error */
 415         li      r1,0x2000
 416         mtspr   SPRN_IVOR15,r1  /* Debug */
 417
 418         /*----------------------------------------------------------------*/
 419         /* Configure cache regions  */
 420         /*----------------------------------------------------------------*/
 421         mtspr   SPRN_INV0,r0
 422         mtspr   SPRN_INV1,r0
 423         mtspr   SPRN_INV2,r0
 424         mtspr   SPRN_INV3,r0
 425         mtspr   SPRN_DNV0,r0
 426         mtspr   SPRN_DNV1,r0
 427         mtspr   SPRN_DNV2,r0
 428         mtspr   SPRN_DNV3,r0
 429         mtspr   SPRN_ITV0,r0
 430         mtspr   SPRN_ITV1,r0
 431         mtspr   SPRN_ITV2,r0
 432         mtspr   SPRN_ITV3,r0
 433         mtspr   SPRN_DTV0,r0
 434         mtspr   SPRN_DTV1,r0
 435         mtspr   SPRN_DTV2,r0
 436         mtspr   SPRN_DTV3,r0
 437
 438         /*----------------------------------------------------------------*/
 439         /* Cache victim limits */
 440         /*----------------------------------------------------------------*/
 441         /* floors 0, ceiling max to use the entire cache -- nothing locked
 442         */
 443         lis     r1,0x0001
 444         ori     r1,r1,0xf800
 445         mtspr   SPRN_IVLIM,r1
 446         mtspr   SPRN_DVLIM,r1
 447
 448         /*----------------------------------------------------------------+
 449         |Initialize MMUCR[STID] = 0.
 450         +-----------------------------------------------------------------*/
 451         mfspr   r0,SPRN_MMUCR
 452         addis   r1,0,0xFFFF
 453         ori     r1,r1,0xFF00
 454         and     r0,r0,r1
 455         mtspr   SPRN_MMUCR,r0
 456
 457         /*----------------------------------------------------------------*/
 458         /* Clear all TLB entries -- TID = 0, TS = 0 */
 459         /*----------------------------------------------------------------*/
 460         addis   r0,0,0x0000
 461 #ifdef CONFIG_SYS_RAMBOOT
 462         li      r4,0            /* Start with TLB #0 */
 463 #else
 464         li      r4,1            /* Start with TLB #1 */
 465 #endif
 466         li      r1,64           /* 64 TLB entries */
 467         sub     r1,r1,r4        /* calculate last TLB # */
 468         mtctr   r1
 469 rsttlb:
 470 #ifdef CONFIG_SYS_RAMBOOT
 471         tlbre   r3,r4,0         /* Read contents from TLB word #0 to get EPN */
 472         rlwinm. r3,r3,0,0xfffffc00      /* Mask EPN */
 473         beq     tlbnxt          /* Skip EPN=0 TLB, this is the SDRAM TLB */
 474 #endif
 475         tlbwe   r0,r4,0         /* Invalidate all entries (V=0)*/
 476         tlbwe   r0,r4,1
 477         tlbwe   r0,r4,2
 478 tlbnxt: addi    r4,r4,1         /* Next TLB */
 479         bdnz    rsttlb
 480
 481         /*----------------------------------------------------------------*/
 482         /* TLB entry setup -- step thru tlbtab */
 483         /*----------------------------------------------------------------*/
 484 #if defined(CONFIG_440SPE_REVA)
 485         /*----------------------------------------------------------------*/
 486         /* We have different TLB tables for revA and rev B of 440SPe */
 487         /*----------------------------------------------------------------*/
 488         mfspr   r1, PVR
 489         lis     r0,0x5342
 490         ori     r0,r0,0x1891
 491         cmpw    r7,r1,r0
 492         bne     r7,..revA
 493         bl      tlbtabB
 494         b       ..goon
 495 ..revA:
 496         bl      tlbtabA
 497 ..goon:
 498 #else
 499         bl      tlbtab          /* Get tlbtab pointer */
 500 #endif
 501         mr      r5,r0
 502         li      r1,0x003f       /* 64 TLB entries max */
 503         mtctr   r1
 504         li      r4,0            /* TLB # */
 505
 506         addi    r5,r5,-4
 507 1:
 508 #ifdef CONFIG_SYS_RAMBOOT
 509         tlbre   r3,r4,0         /* Read contents from TLB word #0 */
 510         rlwinm. r3,r3,0,0x00000200      /* Mask V (valid) bit */
 511         bne     tlbnx2          /* Skip V=1 TLB, this is the SDRAM TLB */
 512 #endif
 513         lwzu    r0,4(r5)
 514         cmpwi   r0,0
 515         beq     2f              /* 0 marks end */
 516         lwzu    r1,4(r5)
 517         lwzu    r2,4(r5)
 518         tlbwe   r0,r4,0         /* TLB Word 0 */
 519         tlbwe   r1,r4,1         /* TLB Word 1 */
 520         tlbwe   r2,r4,2         /* TLB Word 2 */
 521 tlbnx2: addi    r4,r4,1         /* Next TLB */
 522         bdnz    1b
 523
 524         /*----------------------------------------------------------------*/
 525         /* Continue from 'normal' start */
 526         /*----------------------------------------------------------------*/
 527 2:
 528         bl      3f
 529         b       _start
 530
 531 3:      li      r0,0
 532         mtspr   SPRN_SRR1,r0            /* Keep things disabled for now */
 533         mflr    r1
 534         mtspr   SPRN_SRR0,r1
 535         rfi
 536 #endif /* CONFIG_440 */
 537
 538 /*
 539  * r3 - 1st arg to board_init(): IMMP pointer
 540  * r4 - 2nd arg to board_init(): boot flag
 541  */
 542 #ifndef CONFIG_NAND_SPL
 543         .text
 544         .long   0x27051956              /* U-Boot Magic Number                  */
 545         .globl  version_string
 546 version_string:
 547         .ascii U_BOOT_VERSION_STRING, "\0"
 548
 549         . = EXC_OFF_SYS_RESET
 550         .globl  _start_of_vectors
 551 _start_of_vectors:
 552
 553 /* Critical input. */
 554         CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
 555
 556 #ifdef CONFIG_440
 557 /* Machine check */
 558         MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 559 #else
 560         CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 561 #endif /* CONFIG_440 */
 562
 563 /* Data Storage exception. */
 564         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 565
 566 /* Instruction Storage exception. */
 567         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 568
 569 /* External Interrupt exception. */
 570         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 571
 572 /* Alignment exception. */
 573         . = 0x600
 574 Alignment:
 575         EXCEPTION_PROLOG(SRR0, SRR1)
 576         mfspr   r4,DAR
 577         stw     r4,_DAR(r21)
 578         mfspr   r5,DSISR
 579         stw     r5,_DSISR(r21)
 580         addi    r3,r1,STACK_FRAME_OVERHEAD
 581         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 582
 583 /* Program check exception */
 584         . = 0x700
 585 ProgramCheck:
 586         EXCEPTION_PROLOG(SRR0, SRR1)
 587         addi    r3,r1,STACK_FRAME_OVERHEAD
 588         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 589                 MSR_KERNEL, COPY_EE)
 590
 591 #ifdef CONFIG_440
 592         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 593         STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
 594         STD_EXCEPTION(0xa00, APU, UnknownException)
 595 #endif
 596         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 597
 598 #ifdef CONFIG_440
 599         STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
 600         STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
 601 #else
 602         STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
 603         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 604         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 605 #endif
 606         CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
 607
 608         .globl  _end_of_vectors
 609 _end_of_vectors:
 610         . = _START_OFFSET
 611 #endif
 612         .globl  _start
 613 _start:
 614
 615 /*****************************************************************************/
 616 #if defined(CONFIG_440)
 617
 618         /*----------------------------------------------------------------*/
 619         /* Clear and set up some registers. */
 620         /*----------------------------------------------------------------*/
 621         li      r0,0x0000
 622         lis     r1,0xffff
 623         mtspr   SPRN_DEC,r0                     /* prevent dec exceptions */
 624         mtspr   SPRN_TBWL,r0                    /* prevent fit & wdt exceptions */
 625         mtspr   SPRN_TBWU,r0
 626         mtspr   SPRN_TSR,r1                     /* clear all timer exception status */
 627         mtspr   SPRN_TCR,r0                     /* disable all */
 628         mtspr   SPRN_ESR,r0                     /* clear exception syndrome register */
 629         mtxer   r0                      /* clear integer exception register */
 630
 631         /*----------------------------------------------------------------*/
 632         /* Debug setup -- some (not very good) ice's need an event*/
 633         /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
 634         /* value you need in this case 0x8cff 0000 should do the trick */
 635         /*----------------------------------------------------------------*/
 636 #if defined(CONFIG_SYS_INIT_DBCR)
 637         lis     r1,0xffff
 638         ori     r1,r1,0xffff
 639         mtspr   SPRN_DBSR,r1                    /* Clear all status bits */
 640         lis     r0,CONFIG_SYS_INIT_DBCR@h
 641         ori     r0,r0,CONFIG_SYS_INIT_DBCR@l
 642         mtspr   SPRN_DBCR0,r0
 643         isync
 644 #endif
 645
 646         /*----------------------------------------------------------------*/
 647         /* Setup the internal SRAM */
 648         /*----------------------------------------------------------------*/
 649         li      r0,0
 650
 651 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
 652         /* Clear Dcache to use as RAM */
 653         addis   r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
 654         ori     r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
 655         addis   r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
 656         ori     r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
 657         rlwinm. r5,r4,0,27,31
 658         rlwinm  r5,r4,27,5,31
 659         beq     ..d_ran
 660         addi    r5,r5,0x0001
 661 ..d_ran:
 662         mtctr   r5
 663 ..d_ag:
 664         dcbz    r0,r3
 665         addi    r3,r3,32
 666         bdnz    ..d_ag
 667
 668         /*
 669          * Lock the init-ram/stack in d-cache, so that other regions
 670          * may use d-cache as well
 671          * Note, that this current implementation locks exactly 4k
 672          * of d-cache, so please make sure that you don't define a
 673          * bigger init-ram area. Take a look at the lwmon5 440EPx
 674          * implementation as a reference.
 675          */
 676         msync
 677         isync
 678         /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
 679         lis     r1,0x0201
 680         ori     r1,r1,0xf808
 681         mtspr   SPRN_DVLIM,r1
 682         lis     r1,0x0808
 683         ori     r1,r1,0x0808
 684         mtspr   SPRN_DNV0,r1
 685         mtspr   SPRN_DNV1,r1
 686         mtspr   SPRN_DNV2,r1
 687         mtspr   SPRN_DNV3,r1
 688         mtspr   SPRN_DTV0,r1
 689         mtspr   SPRN_DTV1,r1
 690         mtspr   SPRN_DTV2,r1
 691         mtspr   SPRN_DTV3,r1
 692         msync
 693         isync
 694 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 695
 696         /* 440EP & 440GR are only 440er PPC's without internal SRAM */
 697 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
 698         /* not all PPC's have internal SRAM usable as L2-cache */
 699 #if defined(CONFIG_440GX) || \
 700     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 701     defined(CONFIG_460SX)
 702         mtdcr   L2_CACHE_CFG,r0         /* Ensure L2 Cache is off */
 703 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 704       defined(CONFIG_APM821XX)
 705         lis     r1, 0x0000
 706         ori     r1,r1,0x0008            /* Set L2_CACHE_CFG[RDBW]=1 */
 707         mtdcr   L2_CACHE_CFG,r1
 708 #endif
 709
 710         lis     r2,0x7fff
 711         ori     r2,r2,0xffff
 712         mfdcr   r1,ISRAM0_DPC
 713         and     r1,r1,r2                /* Disable parity check */
 714         mtdcr   ISRAM0_DPC,r1
 715         mfdcr   r1,ISRAM0_PMEG
 716         and     r1,r1,r2                /* Disable pwr mgmt */
 717         mtdcr   ISRAM0_PMEG,r1
 718
 719         lis     r1,0x8000               /* BAS = 8000_0000 */
 720 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 721         ori     r1,r1,0x0980            /* first 64k */
 722         mtdcr   ISRAM0_SB0CR,r1
 723         lis     r1,0x8001
 724         ori     r1,r1,0x0980            /* second 64k */
 725         mtdcr   ISRAM0_SB1CR,r1
 726         lis     r1, 0x8002
 727         ori     r1,r1, 0x0980           /* third 64k */
 728         mtdcr   ISRAM0_SB2CR,r1
 729         lis     r1, 0x8003
 730         ori     r1,r1, 0x0980           /* fourth 64k */
 731         mtdcr   ISRAM0_SB3CR,r1
 732 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
 733       defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
 734         lis     r1,0x0000               /* BAS = X_0000_0000 */
 735         ori     r1,r1,0x0984            /* first 64k */
 736         mtdcr   ISRAM0_SB0CR,r1
 737         lis     r1,0x0001
 738         ori     r1,r1,0x0984            /* second 64k */
 739         mtdcr   ISRAM0_SB1CR,r1
 740         lis     r1, 0x0002
 741         ori     r1,r1, 0x0984           /* third 64k */
 742         mtdcr   ISRAM0_SB2CR,r1
 743         lis     r1, 0x0003
 744         ori     r1,r1, 0x0984           /* fourth 64k */
 745         mtdcr   ISRAM0_SB3CR,r1
 746 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 747     defined(CONFIG_APM821XX)
 748         lis     r2,0x7fff
 749         ori     r2,r2,0xffff
 750         mfdcr   r1,ISRAM1_DPC
 751         and     r1,r1,r2                /* Disable parity check */
 752         mtdcr   ISRAM1_DPC,r1
 753         mfdcr   r1,ISRAM1_PMEG
 754         and     r1,r1,r2                /* Disable pwr mgmt */
 755         mtdcr   ISRAM1_PMEG,r1
 756
 757         lis     r1,0x0004               /* BAS = 4_0004_0000 */
 758         ori     r1,r1,ISRAM1_SIZE       /* ocm size */
 759         mtdcr   ISRAM1_SB0CR,r1
 760 #endif
 761 #elif defined(CONFIG_460SX)
 762         lis     r1,0x0000               /* BAS = 0000_0000 */
 763         ori     r1,r1,0x0B84            /* first 128k */
 764         mtdcr   ISRAM0_SB0CR,r1
 765         lis     r1,0x0001
 766         ori     r1,r1,0x0B84            /* second 128k */
 767         mtdcr   ISRAM0_SB1CR,r1
 768         lis     r1, 0x0002
 769         ori     r1,r1, 0x0B84           /* third 128k */
 770         mtdcr   ISRAM0_SB2CR,r1
 771         lis     r1, 0x0003
 772         ori     r1,r1, 0x0B84           /* fourth 128k */
 773         mtdcr   ISRAM0_SB3CR,r1
 774 #elif defined(CONFIG_440GP)
 775         ori     r1,r1,0x0380            /* 8k rw */
 776         mtdcr   ISRAM0_SB0CR,r1
 777         mtdcr   ISRAM0_SB1CR,r0         /* Disable bank 1 */
 778 #endif
 779 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 780
 781         /*----------------------------------------------------------------*/
 782         /* Setup the stack in internal SRAM */
 783         /*----------------------------------------------------------------*/
 784         lis     r1,CONFIG_SYS_INIT_RAM_ADDR@h
 785         ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
 786         li      r0,0
 787         stwu    r0,-4(r1)
 788         stwu    r0,-4(r1)               /* Terminate call chain */
 789
 790         stwu    r1,-8(r1)               /* Save back chain and move SP */
 791         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 792         ori     r0,r0, RESET_VECTOR@l
 793         stwu    r1,-8(r1)               /* Save back chain and move SP */
 794         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 795
 796 #ifdef CONFIG_NAND_SPL
 797         bl      nand_boot_common        /* will not return */
 798 #else
 799         GET_GOT
 800
 801         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 802         bl      board_init_f
 803         /* NOTREACHED - board_init_f() does not return */
 804 #endif
 805
 806 #endif /* CONFIG_440 */
 807
 808 /*****************************************************************************/
 809 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
 810     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 811     defined(CONFIG_405EX) || defined(CONFIG_405)
 812         /*----------------------------------------------------------------------- */
 813         /* Clear and set up some registers. */
 814         /*----------------------------------------------------------------------- */
 815         addi    r4,r0,0x0000
 816 #if !defined(CONFIG_405EX)
 817         mtspr   SPRN_SGR,r4
 818 #else
 819         /*
 820          * On 405EX, completely clearing the SGR leads to PPC hangup
 821          * upon PCIe configuration access. The PCIe memory regions
 822          * need to be guarded!
 823          */
 824         lis     r3,0x0000
 825         ori     r3,r3,0x7FFC
 826         mtspr   SPRN_SGR,r3
 827 #endif
 828         mtspr   SPRN_DCWR,r4
 829         mtesr   r4                      /* clear Exception Syndrome Reg */
 830         mttcr   r4                      /* clear Timer Control Reg */
 831         mtxer   r4                      /* clear Fixed-Point Exception Reg */
 832         mtevpr  r4                      /* clear Exception Vector Prefix Reg */
 833         addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF (status in the */
 834                                         /* dbsr is cleared by setting bits to 1) */
 835         mtdbsr  r4                      /* clear/reset the dbsr */
 836
 837         /* Invalidate the i- and d-caches. */
 838         bl      invalidate_icache
 839         bl      invalidate_dcache
 840
 841         /* Set-up icache cacheability. */
 842         lis     r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
 843         ori     r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
 844         mticcr  r4
 845         isync
 846
 847         /* Set-up dcache cacheability. */
 848         lis     r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
 849         ori     r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
 850         mtdccr  r4
 851
 852 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
 853                                 && !defined (CONFIG_XILINX_405)
 854         /*----------------------------------------------------------------------- */
 855         /* Tune the speed and size for flash CS0  */
 856         /*----------------------------------------------------------------------- */
 857         bl      ext_bus_cntlr_init
 858 #endif
 859
 860 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
 861         /*
 862          * For boards that don't have OCM and can't use the data cache
 863          * for their primordial stack, setup stack here directly after the
 864          * SDRAM is initialized in ext_bus_cntlr_init.
 865          */
 866         lis     r1, CONFIG_SYS_INIT_RAM_ADDR@h
 867         ori     r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
 868
 869         li      r0, 0                   /* Make room for stack frame header and */
 870         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 871         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 872         /*
 873          * Set up a dummy frame to store reset vector as return address.
 874          * this causes stack underflow to reset board.
 875          */
 876         stwu    r1, -8(r1)              /* Save back chain and move SP */
 877         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
 878         ori     r0, r0, RESET_VECTOR@l
 879         stwu    r1, -8(r1)              /* Save back chain and move SP */
 880         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
 881 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS   || !CONFIG_SYS_TEM_STACK_OCM) */
 882
 883 #if defined(CONFIG_405EP)
 884         /*----------------------------------------------------------------------- */
 885         /* DMA Status, clear to come up clean */
 886         /*----------------------------------------------------------------------- */
 887         addis   r3,r0, 0xFFFF           /* Clear all existing DMA status */
 888         ori     r3,r3, 0xFFFF
 889         mtdcr   DMASR, r3
 890
 891         bl      ppc405ep_init           /* do ppc405ep specific init */
 892 #endif /* CONFIG_405EP */
 893
 894 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
 895 #if defined(CONFIG_405EZ)
 896         /********************************************************************
 897          * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
 898          *******************************************************************/
 899         /*
 900          * We can map the OCM on the PLB3, so map it at
 901          * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
 902          */
 903         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 904         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 905         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 906         mtdcr   OCM0_PLBCR1,r3          /* Set PLB Access */
 907         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 908         mtdcr   OCM0_PLBCR2,r3          /* Set PLB Access */
 909         isync
 910
 911         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 912         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 913         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 914         mtdcr   OCM0_DSRC1, r3          /* Set Data Side */
 915         mtdcr   OCM0_ISRC1, r3          /* Set Instruction Side */
 916         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 917         mtdcr   OCM0_DSRC2, r3          /* Set Data Side */
 918         mtdcr   OCM0_ISRC2, r3          /* Set Instruction Side */
 919         addis   r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
 920         mtdcr   OCM0_DISDPC,r3
 921
 922         isync
 923 #else /* CONFIG_405EZ */
 924         /********************************************************************
 925          * Setup OCM - On Chip Memory
 926          *******************************************************************/
 927         /* Setup OCM */
 928         lis     r0, 0x7FFF
 929         ori     r0, r0, 0xFFFF
 930         mfdcr   r3, OCM0_ISCNTL         /* get instr-side IRAM config */
 931         mfdcr   r4, OCM0_DSCNTL         /* get data-side IRAM config */
 932         and     r3, r3, r0              /* disable data-side IRAM */
 933         and     r4, r4, r0              /* disable data-side IRAM */
 934         mtdcr   OCM0_ISCNTL, r3         /* set instr-side IRAM config */
 935         mtdcr   OCM0_DSCNTL, r4         /* set data-side IRAM config */
 936         isync
 937
 938         lis     r3,CONFIG_SYS_OCM_DATA_ADDR@h   /* OCM location */
 939         ori     r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 940         mtdcr   OCM0_DSARC, r3
 941         addis   r4, 0, 0xC000           /* OCM data area enabled */
 942         mtdcr   OCM0_DSCNTL, r4
 943         isync
 944 #endif /* CONFIG_405EZ */
 945 #endif
 946
 947         /*----------------------------------------------------------------------- */
 948         /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 949         /*----------------------------------------------------------------------- */
 950 #ifdef CONFIG_SYS_INIT_DCACHE_CS
 951         li      r4, PBxAP
 952         mtdcr   EBC0_CFGADDR, r4
 953         lis     r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
 954         ori     r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
 955         mtdcr   EBC0_CFGDATA, r4
 956
 957         addi    r4, 0, PBxCR
 958         mtdcr   EBC0_CFGADDR, r4
 959         lis     r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
 960         ori     r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
 961         mtdcr   EBC0_CFGDATA, r4
 962
 963         /*
 964          * Enable the data cache for the 128MB storage access control region
 965          * at CONFIG_SYS_INIT_RAM_ADDR.
 966          */
 967         mfdccr  r4
 968         oris    r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
 969         ori     r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
 970         mtdccr  r4
 971
 972         /*
 973          * Preallocate data cache lines to be used to avoid a subsequent
 974          * cache miss and an ensuing machine check exception when exceptions
 975          * are enabled.
 976          */
 977         li      r0, 0
 978
 979         lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
 980         ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 981
 982         lis     r4, CONFIG_SYS_INIT_RAM_SIZE@h
 983         ori     r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
 984
 985         /*
 986          * Convert the size, in bytes, to the number of cache lines/blocks
 987          * to preallocate.
 988          */
 989         clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
 990         srwi    r5, r4, L1_CACHE_SHIFT
 991         beq     ..load_counter
 992         addi    r5, r5, 0x0001
 993 ..load_counter:
 994         mtctr   r5
 995
 996         /* Preallocate the computed number of cache blocks. */
 997 ..alloc_dcache_block:
 998         dcba    r0, r3
 999         addi    r3, r3, L1_CACHE_BYTES
1000         bdnz    ..alloc_dcache_block
1001         sync
1002
1003         /*
1004          * Load the initial stack pointer and data area and convert the size,
1005          * in bytes, to the number of words to initialize to a known value.
1006          */
1007         lis     r1, CONFIG_SYS_INIT_RAM_ADDR@h
1008         ori     r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1009
1010         lis     r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
1011         ori     r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1012         mtctr   r4
1013
1014         lis     r2, CONFIG_SYS_INIT_RAM_ADDR@h
1015         ori     r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1016
1017         lis     r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1018         ori     r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1019
1020 ..stackloop:
1021         stwu    r4, -4(r2)
1022         bdnz    ..stackloop
1023
1024         /*
1025          * Make room for stack frame header and clear final stack frame so
1026          * that stack backtraces terminate cleanly.
1027          */
1028         stwu    r0, -4(r1)
1029         stwu    r0, -4(r1)
1030
1031         /*
1032          * Set up a dummy frame to store reset vector as return address.
1033          * this causes stack underflow to reset board.
1034          */
1035         stwu    r1, -8(r1)              /* Save back chain and move SP */
1036         addis   r0, 0, RESET_VECTOR@h   /* Address of reset vector */
1037         ori     r0, r0, RESET_VECTOR@l
1038         stwu    r1, -8(r1)              /* Save back chain and move SP */
1039         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1040
1041 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1042         (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1043         /*
1044          * Stack in OCM.
1045          */
1046
1047         /* Set up Stack at top of OCM */
1048         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1049         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1050
1051         /* Set up a zeroized stack frame so that backtrace works right */
1052         li      r0, 0
1053         stwu    r0, -4(r1)
1054         stwu    r0, -4(r1)
1055
1056         /*
1057          * Set up a dummy frame to store reset vector as return address.
1058          * this causes stack underflow to reset board.
1059          */
1060         stwu    r1, -8(r1)              /* Save back chain and move SP */
1061         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
1062         ori     r0, r0, RESET_VECTOR@l
1063         stwu    r1, -8(r1)              /* Save back chain and move SP */
1064         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1065 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1066
1067 #ifdef CONFIG_NAND_SPL
1068         bl      nand_boot_common        /* will not return */
1069 #else
1070         GET_GOT                 /* initialize GOT access                        */
1071
1072         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
1073
1074         bl      board_init_f    /* run first part of init code (from Flash)     */
1075         /* NOTREACHED - board_init_f() does not return */
1076
1077 #endif /* CONFIG_NAND_SPL */
1078
1079 #endif  /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1080         /*----------------------------------------------------------------------- */
1081
1082
1083 #ifndef CONFIG_NAND_SPL
1084 /*
1085  * This code finishes saving the registers to the exception frame
1086  * and jumps to the appropriate handler for the exception.
1087  * Register r21 is pointer into trap frame, r1 has new stack pointer.
1088  */
1089         .globl  transfer_to_handler
1090 transfer_to_handler:
1091         stw     r22,_NIP(r21)
1092         lis     r22,MSR_POW@h
1093         andc    r23,r23,r22
1094         stw     r23,_MSR(r21)
1095         SAVE_GPR(7, r21)
1096         SAVE_4GPRS(8, r21)
1097         SAVE_8GPRS(12, r21)
1098         SAVE_8GPRS(24, r21)
1099         mflr    r23
1100         andi.   r24,r23,0x3f00          /* get vector offset */
1101         stw     r24,TRAP(r21)
1102         li      r22,0
1103         stw     r22,RESULT(r21)
1104         mtspr   SPRG2,r22               /* r1 is now kernel sp */
1105         lwz     r24,0(r23)              /* virtual address of handler */
1106         lwz     r23,4(r23)              /* where to go when done */
1107         mtspr   SRR0,r24
1108         mtspr   SRR1,r20
1109         mtlr    r23
1110         SYNC
1111         rfi                             /* jump to handler, enable MMU */
1112
1113 int_return:
1114         mfmsr   r28             /* Disable interrupts */
1115         li      r4,0
1116         ori     r4,r4,MSR_EE
1117         andc    r28,r28,r4
1118         SYNC                    /* Some chip revs need this... */
1119         mtmsr   r28
1120         SYNC
1121         lwz     r2,_CTR(r1)
1122         lwz     r0,_LINK(r1)
1123         mtctr   r2
1124         mtlr    r0
1125         lwz     r2,_XER(r1)
1126         lwz     r0,_CCR(r1)
1127         mtspr   XER,r2
1128         mtcrf   0xFF,r0
1129         REST_10GPRS(3, r1)
1130         REST_10GPRS(13, r1)
1131         REST_8GPRS(23, r1)
1132         REST_GPR(31, r1)
1133         lwz     r2,_NIP(r1)     /* Restore environment */
1134         lwz     r0,_MSR(r1)
1135         mtspr   SRR0,r2
1136         mtspr   SRR1,r0
1137         lwz     r0,GPR0(r1)
1138         lwz     r2,GPR2(r1)
1139         lwz     r1,GPR1(r1)
1140         SYNC
1141         rfi
1142
1143 crit_return:
1144         mfmsr   r28             /* Disable interrupts */
1145         li      r4,0
1146         ori     r4,r4,MSR_EE
1147         andc    r28,r28,r4
1148         SYNC                    /* Some chip revs need this... */
1149         mtmsr   r28
1150         SYNC
1151         lwz     r2,_CTR(r1)
1152         lwz     r0,_LINK(r1)
1153         mtctr   r2
1154         mtlr    r0
1155         lwz     r2,_XER(r1)
1156         lwz     r0,_CCR(r1)
1157         mtspr   XER,r2
1158         mtcrf   0xFF,r0
1159         REST_10GPRS(3, r1)
1160         REST_10GPRS(13, r1)
1161         REST_8GPRS(23, r1)
1162         REST_GPR(31, r1)
1163         lwz     r2,_NIP(r1)     /* Restore environment */
1164         lwz     r0,_MSR(r1)
1165         mtspr   SPRN_CSRR0,r2
1166         mtspr   SPRN_CSRR1,r0
1167         lwz     r0,GPR0(r1)
1168         lwz     r2,GPR2(r1)
1169         lwz     r1,GPR1(r1)
1170         SYNC
1171         rfci
1172
1173 #ifdef CONFIG_440
1174 mck_return:
1175         mfmsr   r28             /* Disable interrupts */
1176         li      r4,0
1177         ori     r4,r4,MSR_EE
1178         andc    r28,r28,r4
1179         SYNC                    /* Some chip revs need this... */
1180         mtmsr   r28
1181         SYNC
1182         lwz     r2,_CTR(r1)
1183         lwz     r0,_LINK(r1)
1184         mtctr   r2
1185         mtlr    r0
1186         lwz     r2,_XER(r1)
1187         lwz     r0,_CCR(r1)
1188         mtspr   XER,r2
1189         mtcrf   0xFF,r0
1190         REST_10GPRS(3, r1)
1191         REST_10GPRS(13, r1)
1192         REST_8GPRS(23, r1)
1193         REST_GPR(31, r1)
1194         lwz     r2,_NIP(r1)     /* Restore environment */
1195         lwz     r0,_MSR(r1)
1196         mtspr   SPRN_MCSRR0,r2
1197         mtspr   SPRN_MCSRR1,r0
1198         lwz     r0,GPR0(r1)
1199         lwz     r2,GPR2(r1)
1200         lwz     r1,GPR1(r1)
1201         SYNC
1202         rfmci
1203 #endif /* CONFIG_440 */
1204
1205
1206         .globl get_pvr
1207 get_pvr:
1208         mfspr   r3, PVR
1209         blr
1210
1211 /*------------------------------------------------------------------------------- */
1212 /* Function:     out16 */
1213 /* Description:  Output 16 bits */
1214 /*------------------------------------------------------------------------------- */
1215         .globl  out16
1216 out16:
1217         sth     r4,0x0000(r3)
1218         blr
1219
1220 /*------------------------------------------------------------------------------- */
1221 /* Function:     out16r */
1222 /* Description:  Byte reverse and output 16 bits */
1223 /*------------------------------------------------------------------------------- */
1224         .globl  out16r
1225 out16r:
1226         sthbrx  r4,r0,r3
1227         blr
1228
1229 /*------------------------------------------------------------------------------- */
1230 /* Function:     out32r */
1231 /* Description:  Byte reverse and output 32 bits */
1232 /*------------------------------------------------------------------------------- */
1233         .globl  out32r
1234 out32r:
1235         stwbrx  r4,r0,r3
1236         blr
1237
1238 /*------------------------------------------------------------------------------- */
1239 /* Function:     in16 */
1240 /* Description:  Input 16 bits */
1241 /*------------------------------------------------------------------------------- */
1242         .globl  in16
1243 in16:
1244         lhz     r3,0x0000(r3)
1245         blr
1246
1247 /*------------------------------------------------------------------------------- */
1248 /* Function:     in16r */
1249 /* Description:  Input 16 bits and byte reverse */
1250 /*------------------------------------------------------------------------------- */
1251         .globl  in16r
1252 in16r:
1253         lhbrx   r3,r0,r3
1254         blr
1255
1256 /*------------------------------------------------------------------------------- */
1257 /* Function:     in32r */
1258 /* Description:  Input 32 bits and byte reverse */
1259 /*------------------------------------------------------------------------------- */
1260         .globl  in32r
1261 in32r:
1262         lwbrx   r3,r0,r3
1263         blr
1264
1265 /*
1266  * void relocate_code (addr_sp, gd, addr_moni)
1267  *
1268  * This "function" does not return, instead it continues in RAM
1269  * after relocating the monitor code.
1270  *
1271  * r3 = Relocated stack pointer
1272  * r4 = Relocated global data pointer
1273  * r5 = Relocated text pointer
1274  */
1275         .globl  relocate_code
1276 relocate_code:
1277 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1278         /*
1279          * We need to flush the initial global data (gd_t) and bd_info
1280          * before the dcache will be invalidated.
1281          */
1282
1283         /* Save registers */
1284         mr      r9, r3
1285         mr      r10, r4
1286         mr      r11, r5
1287
1288         /*
1289          * Flush complete dcache, this is faster than flushing the
1290          * ranges for global_data and bd_info instead.
1291          */
1292         bl      flush_dcache
1293
1294 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1295         /*
1296          * Undo the earlier data cache set-up for the primordial stack and
1297          * data area. First, invalidate the data cache and then disable data
1298          * cacheability for that area. Finally, restore the EBC values, if
1299          * any.
1300          */
1301
1302         /* Invalidate the primordial stack and data area in cache */
1303         lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
1304         ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1305
1306         lis     r4, CONFIG_SYS_INIT_RAM_SIZE@h
1307         ori     r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1308         add     r4, r4, r3
1309
1310         bl      invalidate_dcache_range
1311
1312         /* Disable cacheability for the region */
1313         mfdccr  r3
1314         lis     r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1315         ori     r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1316         and     r3, r3, r4
1317         mtdccr  r3
1318
1319         /* Restore the EBC parameters */
1320         li      r3, PBxAP
1321         mtdcr   EBC0_CFGADDR, r3
1322         lis     r3, PBxAP_VAL@h
1323         ori     r3, r3, PBxAP_VAL@l
1324         mtdcr   EBC0_CFGDATA, r3
1325
1326         li      r3, PBxCR
1327         mtdcr   EBC0_CFGADDR, r3
1328         lis     r3, PBxCR_VAL@h
1329         ori     r3, r3, PBxCR_VAL@l
1330         mtdcr   EBC0_CFGDATA, r3
1331 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1332
1333         /* Restore registers */
1334         mr      r3, r9
1335         mr      r4, r10
1336         mr      r5, r11
1337 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1338
1339 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1340         /*
1341          * Unlock the previously locked d-cache
1342          */
1343         msync
1344         isync
1345         /* set TFLOOR/NFLOOR to 0 again */
1346         lis     r6,0x0001
1347         ori     r6,r6,0xf800
1348         mtspr   SPRN_DVLIM,r6
1349         lis     r6,0x0000
1350         ori     r6,r6,0x0000
1351         mtspr   SPRN_DNV0,r6
1352         mtspr   SPRN_DNV1,r6
1353         mtspr   SPRN_DNV2,r6
1354         mtspr   SPRN_DNV3,r6
1355         mtspr   SPRN_DTV0,r6
1356         mtspr   SPRN_DTV1,r6
1357         mtspr   SPRN_DTV2,r6
1358         mtspr   SPRN_DTV3,r6
1359         msync
1360         isync
1361
1362         /* Invalidate data cache, now no longer our stack */
1363         dccci   0,0
1364         sync
1365         isync
1366 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1367
1368         /*
1369          * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1370          * to speed up the boot process. Now this cache needs to be disabled.
1371          */
1372 #if defined(CONFIG_440)
1373         /* Clear all potential pending exceptions */
1374         mfspr   r1,SPRN_MCSR
1375         mtspr   SPRN_MCSR,r1
1376         addi    r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH     /* Use defined TLB */
1377         tlbre   r0,r1,0x0002            /* Read contents */
1378         ori     r0,r0,0x0c00            /* Or in the inhibit, write through bit */
1379         tlbwe   r0,r1,0x0002            /* Save it out */
1380         sync
1381         isync
1382 #endif /* defined(CONFIG_440) */
1383         mr      r1,  r3         /* Set new stack pointer                */
1384         mr      r9,  r4         /* Save copy of Init Data pointer       */
1385         mr      r10, r5         /* Save copy of Destination Address     */
1386
1387         GET_GOT
1388         mr      r3,  r5                         /* Destination Address  */
1389         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
1390         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
1391         lwz     r5, GOT(__init_end)
1392         sub     r5, r5, r4
1393         li      r6, L1_CACHE_BYTES              /* Cache Line Size      */
1394
1395         /*
1396          * Fix GOT pointer:
1397          *
1398          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1399          *
1400          * Offset:
1401          */
1402         sub     r15, r10, r4
1403
1404         /* First our own GOT */
1405         add     r12, r12, r15
1406         /* then the one used by the C code */
1407         add     r30, r30, r15
1408
1409         /*
1410          * Now relocate code
1411          */
1412
1413         cmplw   cr1,r3,r4
1414         addi    r0,r5,3
1415         srwi.   r0,r0,2
1416         beq     cr1,4f          /* In place copy is not necessary       */
1417         beq     7f              /* Protect against 0 count              */
1418         mtctr   r0
1419         bge     cr1,2f
1420
1421         la      r8,-4(r4)
1422         la      r7,-4(r3)
1423 1:      lwzu    r0,4(r8)
1424         stwu    r0,4(r7)
1425         bdnz    1b
1426         b       4f
1427
1428 2:      slwi    r0,r0,2
1429         add     r8,r4,r0
1430         add     r7,r3,r0
1431 3:      lwzu    r0,-4(r8)
1432         stwu    r0,-4(r7)
1433         bdnz    3b
1434
1435 /*
1436  * Now flush the cache: note that we must start from a cache aligned
1437  * address. Otherwise we might miss one cache line.
1438  */
1439 4:      cmpwi   r6,0
1440         add     r5,r3,r5
1441         beq     7f              /* Always flush prefetch queue in any case */
1442         subi    r0,r6,1
1443         andc    r3,r3,r0
1444         mr      r4,r3
1445 5:      dcbst   0,r4
1446         add     r4,r4,r6
1447         cmplw   r4,r5
1448         blt     5b
1449         sync                    /* Wait for all dcbst to complete on bus */
1450         mr      r4,r3
1451 6:      icbi    0,r4
1452         add     r4,r4,r6
1453         cmplw   r4,r5
1454         blt     6b
1455 7:      sync                    /* Wait for all icbi to complete on bus */
1456         isync
1457
1458 /*
1459  * We are done. Do not return, instead branch to second part of board
1460  * initialization, now running from RAM.
1461  */
1462
1463         addi    r0, r10, in_ram - _start + _START_OFFSET
1464         mtlr    r0
1465         blr                             /* NEVER RETURNS! */
1466
1467 in_ram:
1468
1469         /*
1470          * Relocation Function, r12 point to got2+0x8000
1471          *
1472          * Adjust got2 pointers, no need to check for 0, this code
1473          * already puts a few entries in the table.
1474          */
1475         li      r0,__got2_entries@sectoff@l
1476         la      r3,GOT(_GOT2_TABLE_)
1477         lwz     r11,GOT(_GOT2_TABLE_)
1478         mtctr   r0
1479         sub     r11,r3,r11
1480         addi    r3,r3,-4
1481 1:      lwzu    r0,4(r3)
1482         cmpwi   r0,0
1483         beq-    2f
1484         add     r0,r0,r11
1485         stw     r0,0(r3)
1486 2:      bdnz    1b
1487
1488         /*
1489          * Now adjust the fixups and the pointers to the fixups
1490          * in case we need to move ourselves again.
1491          */
1492         li      r0,__fixup_entries@sectoff@l
1493         lwz     r3,GOT(_FIXUP_TABLE_)
1494         cmpwi   r0,0
1495         mtctr   r0
1496         addi    r3,r3,-4
1497         beq     4f
1498 3:      lwzu    r4,4(r3)
1499         lwzux   r0,r4,r11
1500         cmpwi   r0,0
1501         add     r0,r0,r11
1502         stw     r4,0(r3)
1503         beq-    5f
1504         stw     r0,0(r4)
1505 5:      bdnz    3b
1506 4:
1507 clear_bss:
1508         /*
1509          * Now clear BSS segment
1510          */
1511         lwz     r3,GOT(__bss_start)
1512         lwz     r4,GOT(__bss_end__)
1513
1514         cmplw   0, r3, r4
1515         beq     7f
1516
1517         li      r0, 0
1518
1519         andi.   r5, r4, 3
1520         beq     6f
1521         sub     r4, r4, r5
1522         mtctr   r5
1523         mr      r5, r4
1524 5:      stb     r0, 0(r5)
1525         addi    r5, r5, 1
1526         bdnz    5b
1527 6:
1528         stw     r0, 0(r3)
1529         addi    r3, r3, 4
1530         cmplw   0, r3, r4
1531         bne     6b
1532
1533 7:
1534         mr      r3, r9          /* Init Data pointer            */
1535         mr      r4, r10         /* Destination Address          */
1536         bl      board_init_r
1537
1538         /*
1539          * Copy exception vector code to low memory
1540          *
1541          * r3: dest_addr
1542          * r7: source address, r8: end address, r9: target address
1543          */
1544         .globl  trap_init
1545 trap_init:
1546         mflr    r4                      /* save link register           */
1547         GET_GOT
1548         lwz     r7, GOT(_start_of_vectors)
1549         lwz     r8, GOT(_end_of_vectors)
1550
1551         li      r9, 0x100               /* reset vector always at 0x100 */
1552
1553         cmplw   0, r7, r8
1554         bgelr                           /* return if r7>=r8 - just in case */
1555 1:
1556         lwz     r0, 0(r7)
1557         stw     r0, 0(r9)
1558         addi    r7, r7, 4
1559         addi    r9, r9, 4
1560         cmplw   0, r7, r8
1561         bne     1b
1562
1563         /*
1564          * relocate `hdlr' and `int_return' entries
1565          */
1566         li      r7, .L_MachineCheck - _start + _START_OFFSET
1567         li      r8, Alignment - _start + _START_OFFSET
1568 2:
1569         bl      trap_reloc
1570         addi    r7, r7, 0x100           /* next exception vector */
1571         cmplw   0, r7, r8
1572         blt     2b
1573
1574         li      r7, .L_Alignment - _start + _START_OFFSET
1575         bl      trap_reloc
1576
1577         li      r7, .L_ProgramCheck - _start + _START_OFFSET
1578         bl      trap_reloc
1579
1580 #ifdef CONFIG_440
1581         li      r7, .L_FPUnavailable - _start + _START_OFFSET
1582         bl      trap_reloc
1583
1584         li      r7, .L_Decrementer - _start + _START_OFFSET
1585         bl      trap_reloc
1586
1587         li      r7, .L_APU - _start + _START_OFFSET
1588         bl      trap_reloc
1589
1590         li      r7, .L_InstructionTLBError - _start + _START_OFFSET
1591         bl      trap_reloc
1592
1593         li      r7, .L_DataTLBError - _start + _START_OFFSET
1594         bl      trap_reloc
1595 #else /* CONFIG_440 */
1596         li      r7, .L_PIT - _start + _START_OFFSET
1597         bl      trap_reloc
1598
1599         li      r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1600         bl      trap_reloc
1601
1602         li      r7, .L_DataTLBMiss - _start + _START_OFFSET
1603         bl      trap_reloc
1604 #endif /* CONFIG_440 */
1605
1606         li      r7, .L_DebugBreakpoint - _start + _START_OFFSET
1607         bl      trap_reloc
1608
1609 #if !defined(CONFIG_440)
1610         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1611         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1612         mtmsr   r7                      /* change MSR */
1613 #else
1614         bl      __440_msr_set
1615         b       __440_msr_continue
1616
1617 __440_msr_set:
1618         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1619         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1620         mtspr   SPRN_SRR1,r7
1621         mflr    r7
1622         mtspr   SPRN_SRR0,r7
1623         rfi
1624 __440_msr_continue:
1625 #endif
1626
1627         mtlr    r4                      /* restore link register        */
1628         blr
1629
1630 #if defined(CONFIG_440)
1631 /*----------------------------------------------------------------------------+
1632 | dcbz_area.
1633 +----------------------------------------------------------------------------*/
1634         function_prolog(dcbz_area)
1635         rlwinm. r5,r4,0,27,31
1636         rlwinm  r5,r4,27,5,31
1637         beq     ..d_ra2
1638         addi    r5,r5,0x0001
1639 ..d_ra2:mtctr   r5
1640 ..d_ag2:dcbz    r0,r3
1641         addi    r3,r3,32
1642         bdnz    ..d_ag2
1643         sync
1644         blr
1645         function_epilog(dcbz_area)
1646 #endif /* CONFIG_440 */
1647 #endif /* CONFIG_NAND_SPL */
1648
1649 /*------------------------------------------------------------------------------- */
1650 /* Function:     in8 */
1651 /* Description:  Input 8 bits */
1652 /*------------------------------------------------------------------------------- */
1653         .globl  in8
1654 in8:
1655         lbz     r3,0x0000(r3)
1656         blr
1657
1658 /*------------------------------------------------------------------------------- */
1659 /* Function:     out8 */
1660 /* Description:  Output 8 bits */
1661 /*------------------------------------------------------------------------------- */
1662         .globl  out8
1663 out8:
1664         stb     r4,0x0000(r3)
1665         blr
1666
1667 /*------------------------------------------------------------------------------- */
1668 /* Function:     out32 */
1669 /* Description:  Output 32 bits */
1670 /*------------------------------------------------------------------------------- */
1671         .globl  out32
1672 out32:
1673         stw     r4,0x0000(r3)
1674         blr
1675
1676 /*------------------------------------------------------------------------------- */
1677 /* Function:     in32 */
1678 /* Description:  Input 32 bits */
1679 /*------------------------------------------------------------------------------- */
1680         .globl  in32
1681 in32:
1682         lwz     3,0x0000(3)
1683         blr
1684
1685 /**************************************************************************/
1686 /* PPC405EP specific stuff                                                */
1687 /**************************************************************************/
1688 #ifdef CONFIG_405EP
1689 ppc405ep_init:
1690
1691 #ifdef CONFIG_BUBINGA
1692         /*
1693          * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1694          * function) to support FPGA and NVRAM accesses below.
1695          */
1696
1697         lis     r3,GPIO0_OSRH@h         /* config GPIO output select */
1698         ori     r3,r3,GPIO0_OSRH@l
1699         lis     r4,CONFIG_SYS_GPIO0_OSRH@h
1700         ori     r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1701         stw     r4,0(r3)
1702         lis     r3,GPIO0_OSRL@h
1703         ori     r3,r3,GPIO0_OSRL@l
1704         lis     r4,CONFIG_SYS_GPIO0_OSRL@h
1705         ori     r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1706         stw     r4,0(r3)
1707
1708         lis     r3,GPIO0_ISR1H@h        /* config GPIO input select */
1709         ori     r3,r3,GPIO0_ISR1H@l
1710         lis     r4,CONFIG_SYS_GPIO0_ISR1H@h
1711         ori     r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1712         stw     r4,0(r3)
1713         lis     r3,GPIO0_ISR1L@h
1714         ori     r3,r3,GPIO0_ISR1L@l
1715         lis     r4,CONFIG_SYS_GPIO0_ISR1L@h
1716         ori     r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1717         stw     r4,0(r3)
1718
1719         lis     r3,GPIO0_TSRH@h         /* config GPIO three-state select */
1720         ori     r3,r3,GPIO0_TSRH@l
1721         lis     r4,CONFIG_SYS_GPIO0_TSRH@h
1722         ori     r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1723         stw     r4,0(r3)
1724         lis     r3,GPIO0_TSRL@h
1725         ori     r3,r3,GPIO0_TSRL@l
1726         lis     r4,CONFIG_SYS_GPIO0_TSRL@h
1727         ori     r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1728         stw     r4,0(r3)
1729
1730         lis     r3,GPIO0_TCR@h          /* config GPIO driver output enables */
1731         ori     r3,r3,GPIO0_TCR@l
1732         lis     r4,CONFIG_SYS_GPIO0_TCR@h
1733         ori     r4,r4,CONFIG_SYS_GPIO0_TCR@l
1734         stw     r4,0(r3)
1735
1736         li      r3,PB1AP                /* program EBC bank 1 for RTC access */
1737         mtdcr   EBC0_CFGADDR,r3
1738         lis     r3,CONFIG_SYS_EBC_PB1AP@h
1739         ori     r3,r3,CONFIG_SYS_EBC_PB1AP@l
1740         mtdcr   EBC0_CFGDATA,r3
1741         li      r3,PB1CR
1742         mtdcr   EBC0_CFGADDR,r3
1743         lis     r3,CONFIG_SYS_EBC_PB1CR@h
1744         ori     r3,r3,CONFIG_SYS_EBC_PB1CR@l
1745         mtdcr   EBC0_CFGDATA,r3
1746
1747         li      r3,PB1AP                /* program EBC bank 1 for RTC access */
1748         mtdcr   EBC0_CFGADDR,r3
1749         lis     r3,CONFIG_SYS_EBC_PB1AP@h
1750         ori     r3,r3,CONFIG_SYS_EBC_PB1AP@l
1751         mtdcr   EBC0_CFGDATA,r3
1752         li      r3,PB1CR
1753         mtdcr   EBC0_CFGADDR,r3
1754         lis     r3,CONFIG_SYS_EBC_PB1CR@h
1755         ori     r3,r3,CONFIG_SYS_EBC_PB1CR@l
1756         mtdcr   EBC0_CFGDATA,r3
1757
1758         li      r3,PB4AP                /* program EBC bank 4 for FPGA access */
1759         mtdcr   EBC0_CFGADDR,r3
1760         lis     r3,CONFIG_SYS_EBC_PB4AP@h
1761         ori     r3,r3,CONFIG_SYS_EBC_PB4AP@l
1762         mtdcr   EBC0_CFGDATA,r3
1763         li      r3,PB4CR
1764         mtdcr   EBC0_CFGADDR,r3
1765         lis     r3,CONFIG_SYS_EBC_PB4CR@h
1766         ori     r3,r3,CONFIG_SYS_EBC_PB4CR@l
1767         mtdcr   EBC0_CFGDATA,r3
1768 #endif
1769
1770         /*
1771         !-----------------------------------------------------------------------
1772         ! Check to see if chip is in bypass mode.
1773         ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1774         ! CPU reset   Otherwise, skip this step and keep going.
1775         ! Note:  Running BIOS in bypass mode is not supported since PLB speed
1776         !        will not be fast enough for the SDRAM (min 66MHz)
1777         !-----------------------------------------------------------------------
1778         */
1779         mfdcr   r5, CPC0_PLLMR1
1780         rlwinm  r4,r5,1,0x1             /* get system clock source (SSCS) */
1781         cmpi    cr0,0,r4,0x1
1782
1783         beq    pll_done                 /* if SSCS =b'1' then PLL has */
1784                                         /* already been set */
1785                                         /* and CPU has been reset */
1786                                         /* so skip to next section */
1787
1788 #ifdef CONFIG_BUBINGA
1789         /*
1790         !-----------------------------------------------------------------------
1791         ! Read NVRAM to get value to write in PLLMR.
1792         ! If value has not been correctly saved, write default value
1793         ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1794         ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1795         !
1796         ! WARNING:  This code assumes the first three words in the nvram_t
1797         !           structure in openbios.h.  Changing the beginning of
1798         !           the structure will break this code.
1799         !
1800         !-----------------------------------------------------------------------
1801         */
1802         addis   r3,0,NVRAM_BASE@h
1803         addi    r3,r3,NVRAM_BASE@l
1804
1805         lwz     r4, 0(r3)
1806         addis   r5,0,NVRVFY1@h
1807         addi    r5,r5,NVRVFY1@l
1808         cmp     cr0,0,r4,r5             /* Compare 1st NVRAM Magic number*/
1809         bne     ..no_pllset
1810         addi    r3,r3,4
1811         lwz     r4, 0(r3)
1812         addis   r5,0,NVRVFY2@h
1813         addi    r5,r5,NVRVFY2@l
1814         cmp     cr0,0,r4,r5             /* Compare 2 NVRAM Magic number */
1815         bne     ..no_pllset
1816         addi    r3,r3,8                 /* Skip over conf_size */
1817         lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
1818         lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
1819         rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
1820         cmpi     cr0,0,r5,1             /* See if PLL is locked */
1821         beq     pll_write
1822 ..no_pllset:
1823 #endif /* CONFIG_BUBINGA */
1824
1825 #ifdef CONFIG_TAIHU
1826         mfdcr   r4, CPC0_BOOT
1827         andi.   r5, r4, CPC0_BOOT_SEP@l
1828         bne     strap_1                 /* serial eeprom present */
1829         addis   r5,0,CPLD_REG0_ADDR@h
1830         ori     r5,r5,CPLD_REG0_ADDR@l
1831         andi.   r5, r5, 0x10
1832         bne     _pci_66mhz
1833 #endif /* CONFIG_TAIHU */
1834
1835 #if defined(CONFIG_ZEUS)
1836         mfdcr   r4, CPC0_BOOT
1837         andi.   r5, r4, CPC0_BOOT_SEP@l
1838         bne     strap_1                 /* serial eeprom present */
1839         lis     r3,0x0000
1840         addi    r3,r3,0x3030
1841         lis     r4,0x8042
1842         addi    r4,r4,0x223e
1843         b       1f
1844 strap_1:
1845         mfdcr   r3, CPC0_PLLMR0
1846         mfdcr   r4, CPC0_PLLMR1
1847         b       1f
1848 #endif
1849
1850         addis   r3,0,PLLMR0_DEFAULT@h   /* PLLMR0 default value */
1851         ori     r3,r3,PLLMR0_DEFAULT@l  /* */
1852         addis   r4,0,PLLMR1_DEFAULT@h   /* PLLMR1 default value */
1853         ori     r4,r4,PLLMR1_DEFAULT@l  /* */
1854
1855 #ifdef CONFIG_TAIHU
1856         b       1f
1857 _pci_66mhz:
1858         addis   r3,0,PLLMR0_DEFAULT_PCI66@h
1859         ori     r3,r3,PLLMR0_DEFAULT_PCI66@l
1860         addis   r4,0,PLLMR1_DEFAULT_PCI66@h
1861         ori     r4,r4,PLLMR1_DEFAULT_PCI66@l
1862         b       1f
1863 strap_1:
1864         mfdcr   r3, CPC0_PLLMR0
1865         mfdcr   r4, CPC0_PLLMR1
1866 #endif /* CONFIG_TAIHU */
1867
1868 1:
1869         b       pll_write               /* Write the CPC0_PLLMR with new value */
1870
1871 pll_done:
1872         /*
1873         !-----------------------------------------------------------------------
1874         ! Clear Soft Reset Register
1875         ! This is needed to enable PCI if not booting from serial EPROM
1876         !-----------------------------------------------------------------------
1877                 */
1878         addi    r3, 0, 0x0
1879         mtdcr   CPC0_SRR, r3
1880
1881         addis    r3,0,0x0010
1882         mtctr   r3
1883 pci_wait:
1884         bdnz    pci_wait
1885
1886         blr                             /* return to main code */
1887
1888 /*
1889 !-----------------------------------------------------------------------------
1890 ! Function:     pll_write
1891 ! Description:  Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1892 !               That is:
1893 !                         1.  Pll is first disabled (de-activated by putting in bypass mode)
1894 !                         2.  PLL is reset
1895 !                         3.  Clock dividers are set while PLL is held in reset and bypassed
1896 !                         4.  PLL Reset is cleared
1897 !                         5.  Wait 100us for PLL to lock
1898 !                         6.  A core reset is performed
1899 ! Input: r3 = Value to write to CPC0_PLLMR0
1900 ! Input: r4 = Value to write to CPC0_PLLMR1
1901 ! Output r3 = none
1902 !-----------------------------------------------------------------------------
1903 */
1904         .globl  pll_write
1905 pll_write:
1906         mfdcr  r5, CPC0_UCR
1907         andis. r5,r5,0xFFFF
1908         ori    r5,r5,0x0101             /* Stop the UART clocks */
1909         mtdcr  CPC0_UCR,r5              /* Before changing PLL */
1910
1911         mfdcr  r5, CPC0_PLLMR1
1912         rlwinm r5,r5,0,0x7FFFFFFF       /* Disable PLL */
1913         mtdcr   CPC0_PLLMR1,r5
1914         oris   r5,r5,0x4000             /* Set PLL Reset */
1915         mtdcr   CPC0_PLLMR1,r5
1916
1917         mtdcr   CPC0_PLLMR0,r3          /* Set clock dividers */
1918         rlwinm r5,r4,0,0x3FFFFFFF       /* Reset & Bypass new PLL dividers */
1919         oris   r5,r5,0x4000             /* Set PLL Reset */
1920         mtdcr   CPC0_PLLMR1,r5          /* Set clock dividers */
1921         rlwinm r5,r5,0,0xBFFFFFFF       /* Clear PLL Reset */
1922         mtdcr   CPC0_PLLMR1,r5
1923
1924                 /*
1925         ! Wait min of 100us for PLL to lock.
1926         ! See CMOS 27E databook for more info.
1927         ! At 200MHz, that means waiting 20,000 instructions
1928                  */
1929         addi    r3,0,20000              /* 2000 = 0x4e20 */
1930         mtctr   r3
1931 pll_wait:
1932         bdnz    pll_wait
1933
1934         oris   r5,r5,0x8000             /* Enable PLL */
1935         mtdcr   CPC0_PLLMR1,r5          /* Engage */
1936
1937         /*
1938          * Reset CPU to guarantee timings are OK
1939          * Not sure if this is needed...
1940          */
1941         addis r3,0,0x1000
1942         mtspr SPRN_DBCR0,r3             /* This will cause a CPU core reset, and */
1943                                         /* execution will continue from the poweron */
1944                                         /* vector of 0xfffffffc */
1945 #endif /* CONFIG_405EP */
1946
1947 #if defined(CONFIG_440)
1948 /*----------------------------------------------------------------------------+
1949 | mttlb3.
1950 +----------------------------------------------------------------------------*/
1951         function_prolog(mttlb3)
1952         TLBWE(4,3,2)
1953         blr
1954         function_epilog(mttlb3)
1955
1956 /*----------------------------------------------------------------------------+
1957 | mftlb3.
1958 +----------------------------------------------------------------------------*/
1959         function_prolog(mftlb3)
1960         TLBRE(3,3,2)
1961         blr
1962         function_epilog(mftlb3)
1963
1964 /*----------------------------------------------------------------------------+
1965 | mttlb2.
1966 +----------------------------------------------------------------------------*/
1967         function_prolog(mttlb2)
1968         TLBWE(4,3,1)
1969         blr
1970         function_epilog(mttlb2)
1971
1972 /*----------------------------------------------------------------------------+
1973 | mftlb2.
1974 +----------------------------------------------------------------------------*/
1975         function_prolog(mftlb2)
1976         TLBRE(3,3,1)
1977         blr
1978         function_epilog(mftlb2)
1979
1980 /*----------------------------------------------------------------------------+
1981 | mttlb1.
1982 +----------------------------------------------------------------------------*/
1983         function_prolog(mttlb1)
1984         TLBWE(4,3,0)
1985         blr
1986         function_epilog(mttlb1)
1987
1988 /*----------------------------------------------------------------------------+
1989 | mftlb1.
1990 +----------------------------------------------------------------------------*/
1991         function_prolog(mftlb1)
1992         TLBRE(3,3,0)
1993         blr
1994         function_epilog(mftlb1)
1995 #endif /* CONFIG_440 */
1996
1997 #if defined(CONFIG_NAND_SPL)
1998 /*
1999  * void nand_boot_relocate(dst, src, bytes)
2000  *
2001  * r3 = Destination address to copy code to (in SDRAM)
2002  * r4 = Source address to copy code from
2003  * r5 = size to copy in bytes
2004  */
2005 nand_boot_relocate:
2006         mr      r6,r3
2007         mr      r7,r4
2008         mflr    r8
2009
2010         /*
2011          * Copy SPL from icache into SDRAM
2012          */
2013         subi    r3,r3,4
2014         subi    r4,r4,4
2015         srwi    r5,r5,2
2016         mtctr   r5
2017 ..spl_loop:
2018         lwzu    r0,4(r4)
2019         stwu    r0,4(r3)
2020         bdnz    ..spl_loop
2021
2022         /*
2023          * Calculate "corrected" link register, so that we "continue"
2024          * in execution in destination range
2025          */
2026         sub     r3,r7,r6        /* r3 = src - dst */
2027         sub     r8,r8,r3        /* r8 = link-reg - (src - dst) */
2028         mtlr    r8
2029         blr
2030
2031 nand_boot_common:
2032         /*
2033          * First initialize SDRAM. It has to be available *before* calling
2034          * nand_boot().
2035          */
2036         lis     r3,CONFIG_SYS_SDRAM_BASE@h
2037         ori     r3,r3,CONFIG_SYS_SDRAM_BASE@l
2038         bl      initdram
2039
2040         /*
2041          * Now copy the 4k SPL code into SDRAM and continue execution
2042          * from there.
2043          */
2044         lis     r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2045         ori     r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2046         lis     r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2047         ori     r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2048         lis     r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2049         ori     r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2050         bl      nand_boot_relocate
2051
2052         /*
2053          * We're running from SDRAM now!!!
2054          *
2055          * It is necessary for 4xx systems to relocate from running at
2056          * the original location (0xfffffxxx) to somewhere else (SDRAM
2057          * preferably). This is because CS0 needs to be reconfigured for
2058          * NAND access. And we can't reconfigure this CS when currently
2059          * "running" from it.
2060          */
2061
2062         /*
2063          * Finally call nand_boot() to load main NAND U-Boot image from
2064          * NAND and jump to it.
2065          */
2066         bl      nand_boot               /* will not return */
2067 #endif /* CONFIG_NAND_SPL */