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Merge branch 'master' of git://git.denx.de/u-boot-i2c
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / start.S
1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27 /*------------------------------------------------------------------------------+
28 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
30 *
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
37 *
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
41 *
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
45 *
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
49 */
50
51 /*
52 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
53 *
54 * The following description only applies to the NOR flash style booting.
55 * NAND booting is different. For more details about NAND booting on 4xx
56 * take a look at doc/README.nand-boot-ppc440.
57 *
58 * The CPU starts at address 0xfffffffc (last word in the address space).
59 * The U-Boot image therefore has to be located in the "upper" area of the
60 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
61 * the boot chip-select (CS0) is quite big and covers this area. On the
62 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
63 * reconfigure this CS0 (and other chip-selects as well when configured
64 * this way) in the boot process to the "correct" values matching the
65 * board layout.
66 */
67
68 #include <asm-offsets.h>
69 #include <config.h>
70 #include <asm/ppc4xx.h>
71 #include <timestamp.h>
72 #include <version.h>
73
74 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
75
76 #include <ppc_asm.tmpl>
77 #include <ppc_defs.h>
78
79 #include <asm/cache.h>
80 #include <asm/mmu.h>
81 #include <asm/ppc4xx-isram.h>
82
83 #ifndef CONFIG_IDENT_STRING
84 #define CONFIG_IDENT_STRING ""
85 #endif
86
87 #ifdef CONFIG_SYS_INIT_DCACHE_CS
88 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
89 # define PBxAP PB1AP
90 # define PBxCR PB0CR
91 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
92 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
93 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
94 # endif
95 # endif
96 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
97 # define PBxAP PB1AP
98 # define PBxCR PB1CR
99 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
100 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
101 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
102 # endif
103 # endif
104 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
105 # define PBxAP PB2AP
106 # define PBxCR PB2CR
107 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
108 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
109 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
110 # endif
111 # endif
112 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
113 # define PBxAP PB3AP
114 # define PBxCR PB3CR
115 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
116 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
117 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
118 # endif
119 # endif
120 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
121 # define PBxAP PB4AP
122 # define PBxCR PB4CR
123 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
124 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
125 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
126 # endif
127 # endif
128 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
129 # define PBxAP PB5AP
130 # define PBxCR PB5CR
131 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
132 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
133 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
134 # endif
135 # endif
136 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
137 # define PBxAP PB6AP
138 # define PBxCR PB6CR
139 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
140 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
141 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
142 # endif
143 # endif
144 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
145 # define PBxAP PB7AP
146 # define PBxCR PB7CR
147 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
148 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
149 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
150 # endif
151 # endif
152 # ifndef PBxAP_VAL
153 # define PBxAP_VAL 0
154 # endif
155 # ifndef PBxCR_VAL
156 # define PBxCR_VAL 0
157 # endif
158 /*
159 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
160 * used as temporary stack pointer for the primordial stack
161 */
162 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
163 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
164 EBC_BXAP_TWT_ENCODE(7) | \
165 EBC_BXAP_BCE_DISABLE | \
166 EBC_BXAP_BCT_2TRANS | \
167 EBC_BXAP_CSN_ENCODE(0) | \
168 EBC_BXAP_OEN_ENCODE(0) | \
169 EBC_BXAP_WBN_ENCODE(0) | \
170 EBC_BXAP_WBF_ENCODE(0) | \
171 EBC_BXAP_TH_ENCODE(2) | \
172 EBC_BXAP_RE_DISABLED | \
173 EBC_BXAP_SOR_NONDELAYED | \
174 EBC_BXAP_BEM_WRITEONLY | \
175 EBC_BXAP_PEN_DISABLED)
176 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
177 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
178 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
179 EBC_BXCR_BS_64MB | \
180 EBC_BXCR_BU_RW | \
181 EBC_BXCR_BW_16BIT)
182 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
183 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
184 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
185 # endif
186 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
187
188 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
189 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
190 #endif
191
192 /*
193 * Unless otherwise overriden, enable two 128MB cachable instruction regions
194 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
195 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
196 */
197 #if !defined(CONFIG_SYS_FLASH_BASE)
198 /* If not already defined, set it to the "last" 128MByte region */
199 # define CONFIG_SYS_FLASH_BASE 0xf8000000
200 #endif
201 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
202 # define CONFIG_SYS_ICACHE_SACR_VALUE \
203 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
204 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
205 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
206 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
207
208 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
209 # define CONFIG_SYS_DCACHE_SACR_VALUE \
210 (0x00000000)
211 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
212
213 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
214 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
215 #endif
216
217 #define function_prolog(func_name) .text; \
218 .align 2; \
219 .globl func_name; \
220 func_name:
221 #define function_epilog(func_name) .type func_name,@function; \
222 .size func_name,.-func_name
223
224 /* We don't want the MMU yet.
225 */
226 #undef MSR_KERNEL
227 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
228
229
230 .extern ext_bus_cntlr_init
231 #ifdef CONFIG_NAND_U_BOOT
232 .extern reconfig_tlb0
233 #endif
234
235 /*
236 * Set up GOT: Global Offset Table
237 *
238 * Use r12 to access the GOT
239 */
240 #if !defined(CONFIG_NAND_SPL)
241 START_GOT
242 GOT_ENTRY(_GOT2_TABLE_)
243 GOT_ENTRY(_FIXUP_TABLE_)
244
245 GOT_ENTRY(_start)
246 GOT_ENTRY(_start_of_vectors)
247 GOT_ENTRY(_end_of_vectors)
248 GOT_ENTRY(transfer_to_handler)
249
250 GOT_ENTRY(__init_end)
251 GOT_ENTRY(__bss_end__)
252 GOT_ENTRY(__bss_start)
253 END_GOT
254 #endif /* CONFIG_NAND_SPL */
255
256 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
257 /*
258 * NAND U-Boot image is started from offset 0
259 */
260 .text
261 #if defined(CONFIG_440)
262 bl reconfig_tlb0
263 #endif
264 GET_GOT
265 bl cpu_init_f /* run low-level CPU init code (from Flash) */
266 bl board_init_f
267 /* NOTREACHED - board_init_f() does not return */
268 #endif
269
270 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
271 /*
272 * 4xx RAM-booting U-Boot image is started from offset 0
273 */
274 .text
275 bl _start_440
276 #endif
277
278 /*
279 * 440 Startup -- on reset only the top 4k of the effective
280 * address space is mapped in by an entry in the instruction
281 * and data shadow TLB. The .bootpg section is located in the
282 * top 4k & does only what's necessary to map in the the rest
283 * of the boot rom. Once the boot rom is mapped in we can
284 * proceed with normal startup.
285 *
286 * NOTE: CS0 only covers the top 2MB of the effective address
287 * space after reset.
288 */
289
290 #if defined(CONFIG_440)
291 #if !defined(CONFIG_NAND_SPL)
292 .section .bootpg,"ax"
293 #endif
294 .globl _start_440
295
296 /**************************************************************************/
297 _start_440:
298 /*--------------------------------------------------------------------+
299 | 440EPX BUP Change - Hardware team request
300 +--------------------------------------------------------------------*/
301 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
302 sync
303 nop
304 nop
305 #endif
306 /*----------------------------------------------------------------+
307 | Core bug fix. Clear the esr
308 +-----------------------------------------------------------------*/
309 li r0,0
310 mtspr SPRN_ESR,r0
311 /*----------------------------------------------------------------*/
312 /* Clear and set up some registers. */
313 /*----------------------------------------------------------------*/
314 iccci r0,r0 /* NOTE: operands not used for 440 */
315 dccci r0,r0 /* NOTE: operands not used for 440 */
316 sync
317 li r0,0
318 mtspr SPRN_SRR0,r0
319 mtspr SPRN_SRR1,r0
320 mtspr SPRN_CSRR0,r0
321 mtspr SPRN_CSRR1,r0
322 /* NOTE: 440GX adds machine check status regs */
323 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
324 mtspr SPRN_MCSRR0,r0
325 mtspr SPRN_MCSRR1,r0
326 mfspr r1,SPRN_MCSR
327 mtspr SPRN_MCSR,r1
328 #endif
329
330 /*----------------------------------------------------------------*/
331 /* CCR0 init */
332 /*----------------------------------------------------------------*/
333 /* Disable store gathering & broadcast, guarantee inst/data
334 * cache block touch, force load/store alignment
335 * (see errata 1.12: 440_33)
336 */
337 lis r1,0x0030 /* store gathering & broadcast disable */
338 ori r1,r1,0x6000 /* cache touch */
339 mtspr SPRN_CCR0,r1
340
341 /*----------------------------------------------------------------*/
342 /* Initialize debug */
343 /*----------------------------------------------------------------*/
344 mfspr r1,SPRN_DBCR0
345 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
346 bne skip_debug_init /* if set, don't clear debug register */
347 mfspr r1,SPRN_CCR0
348 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
349 mtspr SPRN_CCR0,r1
350 mtspr SPRN_DBCR0,r0
351 mtspr SPRN_DBCR1,r0
352 mtspr SPRN_DBCR2,r0
353 mtspr SPRN_IAC1,r0
354 mtspr SPRN_IAC2,r0
355 mtspr SPRN_IAC3,r0
356 mtspr SPRN_DAC1,r0
357 mtspr SPRN_DAC2,r0
358 mtspr SPRN_DVC1,r0
359 mtspr SPRN_DVC2,r0
360
361 mfspr r1,SPRN_DBSR
362 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
363 skip_debug_init:
364
365 #if defined (CONFIG_440SPE)
366 /*----------------------------------------------------------------+
367 | Initialize Core Configuration Reg1.
368 | a. ICDPEI: Record even parity. Normal operation.
369 | b. ICTPEI: Record even parity. Normal operation.
370 | c. DCTPEI: Record even parity. Normal operation.
371 | d. DCDPEI: Record even parity. Normal operation.
372 | e. DCUPEI: Record even parity. Normal operation.
373 | f. DCMPEI: Record even parity. Normal operation.
374 | g. FCOM: Normal operation
375 | h. MMUPEI: Record even parity. Normal operation.
376 | i. FFF: Flush only as much data as necessary.
377 | j. TCS: Timebase increments from CPU clock.
378 +-----------------------------------------------------------------*/
379 li r0,0
380 mtspr SPRN_CCR1, r0
381
382 /*----------------------------------------------------------------+
383 | Reset the timebase.
384 | The previous write to CCR1 sets the timebase source.
385 +-----------------------------------------------------------------*/
386 mtspr SPRN_TBWL, r0
387 mtspr SPRN_TBWU, r0
388 #endif
389
390 /*----------------------------------------------------------------*/
391 /* Setup interrupt vectors */
392 /*----------------------------------------------------------------*/
393 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
394 li r1,0x0100
395 mtspr SPRN_IVOR0,r1 /* Critical input */
396 li r1,0x0200
397 mtspr SPRN_IVOR1,r1 /* Machine check */
398 li r1,0x0300
399 mtspr SPRN_IVOR2,r1 /* Data storage */
400 li r1,0x0400
401 mtspr SPRN_IVOR3,r1 /* Instruction storage */
402 li r1,0x0500
403 mtspr SPRN_IVOR4,r1 /* External interrupt */
404 li r1,0x0600
405 mtspr SPRN_IVOR5,r1 /* Alignment */
406 li r1,0x0700
407 mtspr SPRN_IVOR6,r1 /* Program check */
408 li r1,0x0800
409 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
410 li r1,0x0c00
411 mtspr SPRN_IVOR8,r1 /* System call */
412 li r1,0x0a00
413 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
414 li r1,0x0900
415 mtspr SPRN_IVOR10,r1 /* Decrementer */
416 li r1,0x1300
417 mtspr SPRN_IVOR13,r1 /* Data TLB error */
418 li r1,0x1400
419 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
420 li r1,0x2000
421 mtspr SPRN_IVOR15,r1 /* Debug */
422
423 /*----------------------------------------------------------------*/
424 /* Configure cache regions */
425 /*----------------------------------------------------------------*/
426 mtspr SPRN_INV0,r0
427 mtspr SPRN_INV1,r0
428 mtspr SPRN_INV2,r0
429 mtspr SPRN_INV3,r0
430 mtspr SPRN_DNV0,r0
431 mtspr SPRN_DNV1,r0
432 mtspr SPRN_DNV2,r0
433 mtspr SPRN_DNV3,r0
434 mtspr SPRN_ITV0,r0
435 mtspr SPRN_ITV1,r0
436 mtspr SPRN_ITV2,r0
437 mtspr SPRN_ITV3,r0
438 mtspr SPRN_DTV0,r0
439 mtspr SPRN_DTV1,r0
440 mtspr SPRN_DTV2,r0
441 mtspr SPRN_DTV3,r0
442
443 /*----------------------------------------------------------------*/
444 /* Cache victim limits */
445 /*----------------------------------------------------------------*/
446 /* floors 0, ceiling max to use the entire cache -- nothing locked
447 */
448 lis r1,0x0001
449 ori r1,r1,0xf800
450 mtspr SPRN_IVLIM,r1
451 mtspr SPRN_DVLIM,r1
452
453 /*----------------------------------------------------------------+
454 |Initialize MMUCR[STID] = 0.
455 +-----------------------------------------------------------------*/
456 mfspr r0,SPRN_MMUCR
457 addis r1,0,0xFFFF
458 ori r1,r1,0xFF00
459 and r0,r0,r1
460 mtspr SPRN_MMUCR,r0
461
462 /*----------------------------------------------------------------*/
463 /* Clear all TLB entries -- TID = 0, TS = 0 */
464 /*----------------------------------------------------------------*/
465 addis r0,0,0x0000
466 #ifdef CONFIG_SYS_RAMBOOT
467 li r4,0 /* Start with TLB #0 */
468 #else
469 li r4,1 /* Start with TLB #1 */
470 #endif
471 li r1,64 /* 64 TLB entries */
472 sub r1,r1,r4 /* calculate last TLB # */
473 mtctr r1
474 rsttlb:
475 #ifdef CONFIG_SYS_RAMBOOT
476 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
477 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
478 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
479 #endif
480 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
481 tlbwe r0,r4,1
482 tlbwe r0,r4,2
483 tlbnxt: addi r4,r4,1 /* Next TLB */
484 bdnz rsttlb
485
486 /*----------------------------------------------------------------*/
487 /* TLB entry setup -- step thru tlbtab */
488 /*----------------------------------------------------------------*/
489 #if defined(CONFIG_440SPE_REVA)
490 /*----------------------------------------------------------------*/
491 /* We have different TLB tables for revA and rev B of 440SPe */
492 /*----------------------------------------------------------------*/
493 mfspr r1, PVR
494 lis r0,0x5342
495 ori r0,r0,0x1891
496 cmpw r7,r1,r0
497 bne r7,..revA
498 bl tlbtabB
499 b ..goon
500 ..revA:
501 bl tlbtabA
502 ..goon:
503 #else
504 bl tlbtab /* Get tlbtab pointer */
505 #endif
506 mr r5,r0
507 li r1,0x003f /* 64 TLB entries max */
508 mtctr r1
509 li r4,0 /* TLB # */
510
511 addi r5,r5,-4
512 1:
513 #ifdef CONFIG_SYS_RAMBOOT
514 tlbre r3,r4,0 /* Read contents from TLB word #0 */
515 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
516 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
517 #endif
518 lwzu r0,4(r5)
519 cmpwi r0,0
520 beq 2f /* 0 marks end */
521 lwzu r1,4(r5)
522 lwzu r2,4(r5)
523 tlbwe r0,r4,0 /* TLB Word 0 */
524 tlbwe r1,r4,1 /* TLB Word 1 */
525 tlbwe r2,r4,2 /* TLB Word 2 */
526 tlbnx2: addi r4,r4,1 /* Next TLB */
527 bdnz 1b
528
529 /*----------------------------------------------------------------*/
530 /* Continue from 'normal' start */
531 /*----------------------------------------------------------------*/
532 2:
533 bl 3f
534 b _start
535
536 3: li r0,0
537 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
538 mflr r1
539 mtspr SPRN_SRR0,r1
540 rfi
541 #endif /* CONFIG_440 */
542
543 /*
544 * r3 - 1st arg to board_init(): IMMP pointer
545 * r4 - 2nd arg to board_init(): boot flag
546 */
547 #ifndef CONFIG_NAND_SPL
548 .text
549 .long 0x27051956 /* U-Boot Magic Number */
550 .globl version_string
551 version_string:
552 .ascii U_BOOT_VERSION
553 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
554 .ascii CONFIG_IDENT_STRING, "\0"
555
556 . = EXC_OFF_SYS_RESET
557 .globl _start_of_vectors
558 _start_of_vectors:
559
560 /* Critical input. */
561 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
562
563 #ifdef CONFIG_440
564 /* Machine check */
565 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
566 #else
567 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
568 #endif /* CONFIG_440 */
569
570 /* Data Storage exception. */
571 STD_EXCEPTION(0x300, DataStorage, UnknownException)
572
573 /* Instruction Storage exception. */
574 STD_EXCEPTION(0x400, InstStorage, UnknownException)
575
576 /* External Interrupt exception. */
577 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
578
579 /* Alignment exception. */
580 . = 0x600
581 Alignment:
582 EXCEPTION_PROLOG(SRR0, SRR1)
583 mfspr r4,DAR
584 stw r4,_DAR(r21)
585 mfspr r5,DSISR
586 stw r5,_DSISR(r21)
587 addi r3,r1,STACK_FRAME_OVERHEAD
588 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
589
590 /* Program check exception */
591 . = 0x700
592 ProgramCheck:
593 EXCEPTION_PROLOG(SRR0, SRR1)
594 addi r3,r1,STACK_FRAME_OVERHEAD
595 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
596 MSR_KERNEL, COPY_EE)
597
598 #ifdef CONFIG_440
599 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
600 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
601 STD_EXCEPTION(0xa00, APU, UnknownException)
602 #endif
603 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
604
605 #ifdef CONFIG_440
606 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
607 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
608 #else
609 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
610 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
611 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
612 #endif
613 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
614
615 .globl _end_of_vectors
616 _end_of_vectors:
617 . = _START_OFFSET
618 #endif
619 .globl _start
620 _start:
621
622 /*****************************************************************************/
623 #if defined(CONFIG_440)
624
625 /*----------------------------------------------------------------*/
626 /* Clear and set up some registers. */
627 /*----------------------------------------------------------------*/
628 li r0,0x0000
629 lis r1,0xffff
630 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
631 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
632 mtspr SPRN_TBWU,r0
633 mtspr SPRN_TSR,r1 /* clear all timer exception status */
634 mtspr SPRN_TCR,r0 /* disable all */
635 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
636 mtxer r0 /* clear integer exception register */
637
638 /*----------------------------------------------------------------*/
639 /* Debug setup -- some (not very good) ice's need an event*/
640 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
641 /* value you need in this case 0x8cff 0000 should do the trick */
642 /*----------------------------------------------------------------*/
643 #if defined(CONFIG_SYS_INIT_DBCR)
644 lis r1,0xffff
645 ori r1,r1,0xffff
646 mtspr SPRN_DBSR,r1 /* Clear all status bits */
647 lis r0,CONFIG_SYS_INIT_DBCR@h
648 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
649 mtspr SPRN_DBCR0,r0
650 isync
651 #endif
652
653 /*----------------------------------------------------------------*/
654 /* Setup the internal SRAM */
655 /*----------------------------------------------------------------*/
656 li r0,0
657
658 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
659 /* Clear Dcache to use as RAM */
660 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
661 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
662 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
663 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
664 rlwinm. r5,r4,0,27,31
665 rlwinm r5,r4,27,5,31
666 beq ..d_ran
667 addi r5,r5,0x0001
668 ..d_ran:
669 mtctr r5
670 ..d_ag:
671 dcbz r0,r3
672 addi r3,r3,32
673 bdnz ..d_ag
674
675 /*
676 * Lock the init-ram/stack in d-cache, so that other regions
677 * may use d-cache as well
678 * Note, that this current implementation locks exactly 4k
679 * of d-cache, so please make sure that you don't define a
680 * bigger init-ram area. Take a look at the lwmon5 440EPx
681 * implementation as a reference.
682 */
683 msync
684 isync
685 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
686 lis r1,0x0201
687 ori r1,r1,0xf808
688 mtspr SPRN_DVLIM,r1
689 lis r1,0x0808
690 ori r1,r1,0x0808
691 mtspr SPRN_DNV0,r1
692 mtspr SPRN_DNV1,r1
693 mtspr SPRN_DNV2,r1
694 mtspr SPRN_DNV3,r1
695 mtspr SPRN_DTV0,r1
696 mtspr SPRN_DTV1,r1
697 mtspr SPRN_DTV2,r1
698 mtspr SPRN_DTV3,r1
699 msync
700 isync
701 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
702
703 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
704 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
705 /* not all PPC's have internal SRAM usable as L2-cache */
706 #if defined(CONFIG_440GX) || \
707 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
708 defined(CONFIG_460SX)
709 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
710 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
711 defined(CONFIG_APM821XX)
712 lis r1, 0x0000
713 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
714 mtdcr L2_CACHE_CFG,r1
715 #endif
716
717 lis r2,0x7fff
718 ori r2,r2,0xffff
719 mfdcr r1,ISRAM0_DPC
720 and r1,r1,r2 /* Disable parity check */
721 mtdcr ISRAM0_DPC,r1
722 mfdcr r1,ISRAM0_PMEG
723 and r1,r1,r2 /* Disable pwr mgmt */
724 mtdcr ISRAM0_PMEG,r1
725
726 lis r1,0x8000 /* BAS = 8000_0000 */
727 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
728 ori r1,r1,0x0980 /* first 64k */
729 mtdcr ISRAM0_SB0CR,r1
730 lis r1,0x8001
731 ori r1,r1,0x0980 /* second 64k */
732 mtdcr ISRAM0_SB1CR,r1
733 lis r1, 0x8002
734 ori r1,r1, 0x0980 /* third 64k */
735 mtdcr ISRAM0_SB2CR,r1
736 lis r1, 0x8003
737 ori r1,r1, 0x0980 /* fourth 64k */
738 mtdcr ISRAM0_SB3CR,r1
739 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
740 defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
741 lis r1,0x0000 /* BAS = X_0000_0000 */
742 ori r1,r1,0x0984 /* first 64k */
743 mtdcr ISRAM0_SB0CR,r1
744 lis r1,0x0001
745 ori r1,r1,0x0984 /* second 64k */
746 mtdcr ISRAM0_SB1CR,r1
747 lis r1, 0x0002
748 ori r1,r1, 0x0984 /* third 64k */
749 mtdcr ISRAM0_SB2CR,r1
750 lis r1, 0x0003
751 ori r1,r1, 0x0984 /* fourth 64k */
752 mtdcr ISRAM0_SB3CR,r1
753 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
754 defined(CONFIG_APM821XX)
755 lis r2,0x7fff
756 ori r2,r2,0xffff
757 mfdcr r1,ISRAM1_DPC
758 and r1,r1,r2 /* Disable parity check */
759 mtdcr ISRAM1_DPC,r1
760 mfdcr r1,ISRAM1_PMEG
761 and r1,r1,r2 /* Disable pwr mgmt */
762 mtdcr ISRAM1_PMEG,r1
763
764 lis r1,0x0004 /* BAS = 4_0004_0000 */
765 ori r1,r1,ISRAM1_SIZE /* ocm size */
766 mtdcr ISRAM1_SB0CR,r1
767 #endif
768 #elif defined(CONFIG_460SX)
769 lis r1,0x0000 /* BAS = 0000_0000 */
770 ori r1,r1,0x0B84 /* first 128k */
771 mtdcr ISRAM0_SB0CR,r1
772 lis r1,0x0001
773 ori r1,r1,0x0B84 /* second 128k */
774 mtdcr ISRAM0_SB1CR,r1
775 lis r1, 0x0002
776 ori r1,r1, 0x0B84 /* third 128k */
777 mtdcr ISRAM0_SB2CR,r1
778 lis r1, 0x0003
779 ori r1,r1, 0x0B84 /* fourth 128k */
780 mtdcr ISRAM0_SB3CR,r1
781 #elif defined(CONFIG_440GP)
782 ori r1,r1,0x0380 /* 8k rw */
783 mtdcr ISRAM0_SB0CR,r1
784 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
785 #endif
786 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
787
788 /*----------------------------------------------------------------*/
789 /* Setup the stack in internal SRAM */
790 /*----------------------------------------------------------------*/
791 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
792 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
793 li r0,0
794 stwu r0,-4(r1)
795 stwu r0,-4(r1) /* Terminate call chain */
796
797 stwu r1,-8(r1) /* Save back chain and move SP */
798 lis r0,RESET_VECTOR@h /* Address of reset vector */
799 ori r0,r0, RESET_VECTOR@l
800 stwu r1,-8(r1) /* Save back chain and move SP */
801 stw r0,+12(r1) /* Save return addr (underflow vect) */
802
803 #ifdef CONFIG_NAND_SPL
804 bl nand_boot_common /* will not return */
805 #else
806 GET_GOT
807
808 bl cpu_init_f /* run low-level CPU init code (from Flash) */
809 bl board_init_f
810 /* NOTREACHED - board_init_f() does not return */
811 #endif
812
813 #endif /* CONFIG_440 */
814
815 /*****************************************************************************/
816 #ifdef CONFIG_IOP480
817 /*----------------------------------------------------------------------- */
818 /* Set up some machine state registers. */
819 /*----------------------------------------------------------------------- */
820 addi r0,r0,0x0000 /* initialize r0 to zero */
821 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
822 mttcr r0 /* timer control register */
823 mtexier r0 /* disable all interrupts */
824 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
825 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
826 mtdbsr r4 /* clear/reset the dbsr */
827 mtexisr r4 /* clear all pending interrupts */
828 addis r4,r0,0x8000
829 mtexier r4 /* enable critical exceptions */
830 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
831 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
832 mtiocr r4 /* since bit not used) & DRC to latch */
833 /* data bus on rising edge of CAS */
834 /*----------------------------------------------------------------------- */
835 /* Clear XER. */
836 /*----------------------------------------------------------------------- */
837 mtxer r0
838 /*----------------------------------------------------------------------- */
839 /* Invalidate i-cache and d-cache TAG arrays. */
840 /*----------------------------------------------------------------------- */
841 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
842 addi r4,0,1024 /* 1/4 of I-cache */
843 ..cloop:
844 iccci 0,r3
845 iccci r4,r3
846 dccci 0,r3
847 addic. r3,r3,-16 /* move back one cache line */
848 bne ..cloop /* loop back to do rest until r3 = 0 */
849
850 /* */
851 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
852 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
853 /* */
854
855 /* first copy IOP480 register base address into r3 */
856 addis r3,0,0x5000 /* IOP480 register base address hi */
857 /* ori r3,r3,0x0000 / IOP480 register base address lo */
858
859 #ifdef CONFIG_ADCIOP
860 /* use r4 as the working variable */
861 /* turn on CS3 (LOCCTL.7) */
862 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
863 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
864 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
865 #endif
866
867 #ifdef CONFIG_DASA_SIM
868 /* use r4 as the working variable */
869 /* turn on MA17 (LOCCTL.7) */
870 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
871 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
872 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
873 #endif
874
875 /* turn on MA16..13 (LCS0BRD.12 = 0) */
876 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
877 andi. r4,r4,0xefff /* make bit 12 = 0 */
878 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
879
880 /* make sure above stores all comlete before going on */
881 sync
882
883 /* last thing, set local init status done bit (DEVINIT.31) */
884 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
885 oris r4,r4,0x8000 /* make bit 31 = 1 */
886 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
887
888 /* clear all pending interrupts and disable all interrupts */
889 li r4,-1 /* set p1 to 0xffffffff */
890 stw r4,0x1b0(r3) /* clear all pending interrupts */
891 stw r4,0x1b8(r3) /* clear all pending interrupts */
892 li r4,0 /* set r4 to 0 */
893 stw r4,0x1b4(r3) /* disable all interrupts */
894 stw r4,0x1bc(r3) /* disable all interrupts */
895
896 /* make sure above stores all comlete before going on */
897 sync
898
899 /* Set-up icache cacheability. */
900 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
901 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
902 mticcr r1
903 isync
904
905 /* Set-up dcache cacheability. */
906 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
907 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
908 mtdccr r1
909
910 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
911 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
912 li r0, 0 /* Make room for stack frame header and */
913 stwu r0, -4(r1) /* clear final stack frame so that */
914 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
915
916 GET_GOT /* initialize GOT access */
917
918 bl board_init_f /* run first part of init code (from Flash) */
919 /* NOTREACHED - board_init_f() does not return */
920
921 #endif /* CONFIG_IOP480 */
922
923 /*****************************************************************************/
924 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
925 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
926 defined(CONFIG_405EX) || defined(CONFIG_405)
927 /*----------------------------------------------------------------------- */
928 /* Clear and set up some registers. */
929 /*----------------------------------------------------------------------- */
930 addi r4,r0,0x0000
931 #if !defined(CONFIG_405EX)
932 mtspr SPRN_SGR,r4
933 #else
934 /*
935 * On 405EX, completely clearing the SGR leads to PPC hangup
936 * upon PCIe configuration access. The PCIe memory regions
937 * need to be guarded!
938 */
939 lis r3,0x0000
940 ori r3,r3,0x7FFC
941 mtspr SPRN_SGR,r3
942 #endif
943 mtspr SPRN_DCWR,r4
944 mtesr r4 /* clear Exception Syndrome Reg */
945 mttcr r4 /* clear Timer Control Reg */
946 mtxer r4 /* clear Fixed-Point Exception Reg */
947 mtevpr r4 /* clear Exception Vector Prefix Reg */
948 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
949 /* dbsr is cleared by setting bits to 1) */
950 mtdbsr r4 /* clear/reset the dbsr */
951
952 /* Invalidate the i- and d-caches. */
953 bl invalidate_icache
954 bl invalidate_dcache
955
956 /* Set-up icache cacheability. */
957 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
958 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
959 mticcr r4
960 isync
961
962 /* Set-up dcache cacheability. */
963 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
964 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
965 mtdccr r4
966
967 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
968 && !defined (CONFIG_XILINX_405)
969 /*----------------------------------------------------------------------- */
970 /* Tune the speed and size for flash CS0 */
971 /*----------------------------------------------------------------------- */
972 bl ext_bus_cntlr_init
973 #endif
974
975 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
976 /*
977 * For boards that don't have OCM and can't use the data cache
978 * for their primordial stack, setup stack here directly after the
979 * SDRAM is initialized in ext_bus_cntlr_init.
980 */
981 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
982 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
983
984 li r0, 0 /* Make room for stack frame header and */
985 stwu r0, -4(r1) /* clear final stack frame so that */
986 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
987 /*
988 * Set up a dummy frame to store reset vector as return address.
989 * this causes stack underflow to reset board.
990 */
991 stwu r1, -8(r1) /* Save back chain and move SP */
992 lis r0, RESET_VECTOR@h /* Address of reset vector */
993 ori r0, r0, RESET_VECTOR@l
994 stwu r1, -8(r1) /* Save back chain and move SP */
995 stw r0, +12(r1) /* Save return addr (underflow vect) */
996 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
997
998 #if defined(CONFIG_405EP)
999 /*----------------------------------------------------------------------- */
1000 /* DMA Status, clear to come up clean */
1001 /*----------------------------------------------------------------------- */
1002 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
1003 ori r3,r3, 0xFFFF
1004 mtdcr DMASR, r3
1005
1006 bl ppc405ep_init /* do ppc405ep specific init */
1007 #endif /* CONFIG_405EP */
1008
1009 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
1010 #if defined(CONFIG_405EZ)
1011 /********************************************************************
1012 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1013 *******************************************************************/
1014 /*
1015 * We can map the OCM on the PLB3, so map it at
1016 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1017 */
1018 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1019 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1020 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1021 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
1022 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1023 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
1024 isync
1025
1026 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1027 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1028 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1029 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1030 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
1031 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1032 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1033 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
1034 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1035 mtdcr OCM0_DISDPC,r3
1036
1037 isync
1038 #else /* CONFIG_405EZ */
1039 /********************************************************************
1040 * Setup OCM - On Chip Memory
1041 *******************************************************************/
1042 /* Setup OCM */
1043 lis r0, 0x7FFF
1044 ori r0, r0, 0xFFFF
1045 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1046 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
1047 and r3, r3, r0 /* disable data-side IRAM */
1048 and r4, r4, r0 /* disable data-side IRAM */
1049 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1050 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
1051 isync
1052
1053 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1054 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1055 mtdcr OCM0_DSARC, r3
1056 addis r4, 0, 0xC000 /* OCM data area enabled */
1057 mtdcr OCM0_DSCNTL, r4
1058 isync
1059 #endif /* CONFIG_405EZ */
1060 #endif
1061
1062 /*----------------------------------------------------------------------- */
1063 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1064 /*----------------------------------------------------------------------- */
1065 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1066 li r4, PBxAP
1067 mtdcr EBC0_CFGADDR, r4
1068 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1069 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1070 mtdcr EBC0_CFGDATA, r4
1071
1072 addi r4, 0, PBxCR
1073 mtdcr EBC0_CFGADDR, r4
1074 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1075 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1076 mtdcr EBC0_CFGDATA, r4
1077
1078 /*
1079 * Enable the data cache for the 128MB storage access control region
1080 * at CONFIG_SYS_INIT_RAM_ADDR.
1081 */
1082 mfdccr r4
1083 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1084 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1085 mtdccr r4
1086
1087 /*
1088 * Preallocate data cache lines to be used to avoid a subsequent
1089 * cache miss and an ensuing machine check exception when exceptions
1090 * are enabled.
1091 */
1092 li r0, 0
1093
1094 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1095 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1096
1097 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1098 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1099
1100 /*
1101 * Convert the size, in bytes, to the number of cache lines/blocks
1102 * to preallocate.
1103 */
1104 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1105 srwi r5, r4, L1_CACHE_SHIFT
1106 beq ..load_counter
1107 addi r5, r5, 0x0001
1108 ..load_counter:
1109 mtctr r5
1110
1111 /* Preallocate the computed number of cache blocks. */
1112 ..alloc_dcache_block:
1113 dcba r0, r3
1114 addi r3, r3, L1_CACHE_BYTES
1115 bdnz ..alloc_dcache_block
1116 sync
1117
1118 /*
1119 * Load the initial stack pointer and data area and convert the size,
1120 * in bytes, to the number of words to initialize to a known value.
1121 */
1122 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1123 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1124
1125 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
1126 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1127 mtctr r4
1128
1129 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1130 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1131
1132 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1133 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1134
1135 ..stackloop:
1136 stwu r4, -4(r2)
1137 bdnz ..stackloop
1138
1139 /*
1140 * Make room for stack frame header and clear final stack frame so
1141 * that stack backtraces terminate cleanly.
1142 */
1143 stwu r0, -4(r1)
1144 stwu r0, -4(r1)
1145
1146 /*
1147 * Set up a dummy frame to store reset vector as return address.
1148 * this causes stack underflow to reset board.
1149 */
1150 stwu r1, -8(r1) /* Save back chain and move SP */
1151 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1152 ori r0, r0, RESET_VECTOR@l
1153 stwu r1, -8(r1) /* Save back chain and move SP */
1154 stw r0, +12(r1) /* Save return addr (underflow vect) */
1155
1156 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1157 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1158 /*
1159 * Stack in OCM.
1160 */
1161
1162 /* Set up Stack at top of OCM */
1163 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1164 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1165
1166 /* Set up a zeroized stack frame so that backtrace works right */
1167 li r0, 0
1168 stwu r0, -4(r1)
1169 stwu r0, -4(r1)
1170
1171 /*
1172 * Set up a dummy frame to store reset vector as return address.
1173 * this causes stack underflow to reset board.
1174 */
1175 stwu r1, -8(r1) /* Save back chain and move SP */
1176 lis r0, RESET_VECTOR@h /* Address of reset vector */
1177 ori r0, r0, RESET_VECTOR@l
1178 stwu r1, -8(r1) /* Save back chain and move SP */
1179 stw r0, +12(r1) /* Save return addr (underflow vect) */
1180 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1181
1182 #ifdef CONFIG_NAND_SPL
1183 bl nand_boot_common /* will not return */
1184 #else
1185 GET_GOT /* initialize GOT access */
1186
1187 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1188
1189 bl board_init_f /* run first part of init code (from Flash) */
1190 /* NOTREACHED - board_init_f() does not return */
1191
1192 #endif /* CONFIG_NAND_SPL */
1193
1194 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1195 /*----------------------------------------------------------------------- */
1196
1197
1198 #ifndef CONFIG_NAND_SPL
1199 /*
1200 * This code finishes saving the registers to the exception frame
1201 * and jumps to the appropriate handler for the exception.
1202 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1203 */
1204 .globl transfer_to_handler
1205 transfer_to_handler:
1206 stw r22,_NIP(r21)
1207 lis r22,MSR_POW@h
1208 andc r23,r23,r22
1209 stw r23,_MSR(r21)
1210 SAVE_GPR(7, r21)
1211 SAVE_4GPRS(8, r21)
1212 SAVE_8GPRS(12, r21)
1213 SAVE_8GPRS(24, r21)
1214 mflr r23
1215 andi. r24,r23,0x3f00 /* get vector offset */
1216 stw r24,TRAP(r21)
1217 li r22,0
1218 stw r22,RESULT(r21)
1219 mtspr SPRG2,r22 /* r1 is now kernel sp */
1220 lwz r24,0(r23) /* virtual address of handler */
1221 lwz r23,4(r23) /* where to go when done */
1222 mtspr SRR0,r24
1223 mtspr SRR1,r20
1224 mtlr r23
1225 SYNC
1226 rfi /* jump to handler, enable MMU */
1227
1228 int_return:
1229 mfmsr r28 /* Disable interrupts */
1230 li r4,0
1231 ori r4,r4,MSR_EE
1232 andc r28,r28,r4
1233 SYNC /* Some chip revs need this... */
1234 mtmsr r28
1235 SYNC
1236 lwz r2,_CTR(r1)
1237 lwz r0,_LINK(r1)
1238 mtctr r2
1239 mtlr r0
1240 lwz r2,_XER(r1)
1241 lwz r0,_CCR(r1)
1242 mtspr XER,r2
1243 mtcrf 0xFF,r0
1244 REST_10GPRS(3, r1)
1245 REST_10GPRS(13, r1)
1246 REST_8GPRS(23, r1)
1247 REST_GPR(31, r1)
1248 lwz r2,_NIP(r1) /* Restore environment */
1249 lwz r0,_MSR(r1)
1250 mtspr SRR0,r2
1251 mtspr SRR1,r0
1252 lwz r0,GPR0(r1)
1253 lwz r2,GPR2(r1)
1254 lwz r1,GPR1(r1)
1255 SYNC
1256 rfi
1257
1258 crit_return:
1259 mfmsr r28 /* Disable interrupts */
1260 li r4,0
1261 ori r4,r4,MSR_EE
1262 andc r28,r28,r4
1263 SYNC /* Some chip revs need this... */
1264 mtmsr r28
1265 SYNC
1266 lwz r2,_CTR(r1)
1267 lwz r0,_LINK(r1)
1268 mtctr r2
1269 mtlr r0
1270 lwz r2,_XER(r1)
1271 lwz r0,_CCR(r1)
1272 mtspr XER,r2
1273 mtcrf 0xFF,r0
1274 REST_10GPRS(3, r1)
1275 REST_10GPRS(13, r1)
1276 REST_8GPRS(23, r1)
1277 REST_GPR(31, r1)
1278 lwz r2,_NIP(r1) /* Restore environment */
1279 lwz r0,_MSR(r1)
1280 mtspr SPRN_CSRR0,r2
1281 mtspr SPRN_CSRR1,r0
1282 lwz r0,GPR0(r1)
1283 lwz r2,GPR2(r1)
1284 lwz r1,GPR1(r1)
1285 SYNC
1286 rfci
1287
1288 #ifdef CONFIG_440
1289 mck_return:
1290 mfmsr r28 /* Disable interrupts */
1291 li r4,0
1292 ori r4,r4,MSR_EE
1293 andc r28,r28,r4
1294 SYNC /* Some chip revs need this... */
1295 mtmsr r28
1296 SYNC
1297 lwz r2,_CTR(r1)
1298 lwz r0,_LINK(r1)
1299 mtctr r2
1300 mtlr r0
1301 lwz r2,_XER(r1)
1302 lwz r0,_CCR(r1)
1303 mtspr XER,r2
1304 mtcrf 0xFF,r0
1305 REST_10GPRS(3, r1)
1306 REST_10GPRS(13, r1)
1307 REST_8GPRS(23, r1)
1308 REST_GPR(31, r1)
1309 lwz r2,_NIP(r1) /* Restore environment */
1310 lwz r0,_MSR(r1)
1311 mtspr SPRN_MCSRR0,r2
1312 mtspr SPRN_MCSRR1,r0
1313 lwz r0,GPR0(r1)
1314 lwz r2,GPR2(r1)
1315 lwz r1,GPR1(r1)
1316 SYNC
1317 rfmci
1318 #endif /* CONFIG_440 */
1319
1320
1321 .globl get_pvr
1322 get_pvr:
1323 mfspr r3, PVR
1324 blr
1325
1326 /*------------------------------------------------------------------------------- */
1327 /* Function: out16 */
1328 /* Description: Output 16 bits */
1329 /*------------------------------------------------------------------------------- */
1330 .globl out16
1331 out16:
1332 sth r4,0x0000(r3)
1333 blr
1334
1335 /*------------------------------------------------------------------------------- */
1336 /* Function: out16r */
1337 /* Description: Byte reverse and output 16 bits */
1338 /*------------------------------------------------------------------------------- */
1339 .globl out16r
1340 out16r:
1341 sthbrx r4,r0,r3
1342 blr
1343
1344 /*------------------------------------------------------------------------------- */
1345 /* Function: out32r */
1346 /* Description: Byte reverse and output 32 bits */
1347 /*------------------------------------------------------------------------------- */
1348 .globl out32r
1349 out32r:
1350 stwbrx r4,r0,r3
1351 blr
1352
1353 /*------------------------------------------------------------------------------- */
1354 /* Function: in16 */
1355 /* Description: Input 16 bits */
1356 /*------------------------------------------------------------------------------- */
1357 .globl in16
1358 in16:
1359 lhz r3,0x0000(r3)
1360 blr
1361
1362 /*------------------------------------------------------------------------------- */
1363 /* Function: in16r */
1364 /* Description: Input 16 bits and byte reverse */
1365 /*------------------------------------------------------------------------------- */
1366 .globl in16r
1367 in16r:
1368 lhbrx r3,r0,r3
1369 blr
1370
1371 /*------------------------------------------------------------------------------- */
1372 /* Function: in32r */
1373 /* Description: Input 32 bits and byte reverse */
1374 /*------------------------------------------------------------------------------- */
1375 .globl in32r
1376 in32r:
1377 lwbrx r3,r0,r3
1378 blr
1379
1380 /*
1381 * void relocate_code (addr_sp, gd, addr_moni)
1382 *
1383 * This "function" does not return, instead it continues in RAM
1384 * after relocating the monitor code.
1385 *
1386 * r3 = Relocated stack pointer
1387 * r4 = Relocated global data pointer
1388 * r5 = Relocated text pointer
1389 */
1390 .globl relocate_code
1391 relocate_code:
1392 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1393 /*
1394 * We need to flush the initial global data (gd_t) and bd_info
1395 * before the dcache will be invalidated.
1396 */
1397
1398 /* Save registers */
1399 mr r9, r3
1400 mr r10, r4
1401 mr r11, r5
1402
1403 /*
1404 * Flush complete dcache, this is faster than flushing the
1405 * ranges for global_data and bd_info instead.
1406 */
1407 bl flush_dcache
1408
1409 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1410 /*
1411 * Undo the earlier data cache set-up for the primordial stack and
1412 * data area. First, invalidate the data cache and then disable data
1413 * cacheability for that area. Finally, restore the EBC values, if
1414 * any.
1415 */
1416
1417 /* Invalidate the primordial stack and data area in cache */
1418 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1419 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1420
1421 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1422 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1423 add r4, r4, r3
1424
1425 bl invalidate_dcache_range
1426
1427 /* Disable cacheability for the region */
1428 mfdccr r3
1429 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1430 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1431 and r3, r3, r4
1432 mtdccr r3
1433
1434 /* Restore the EBC parameters */
1435 li r3, PBxAP
1436 mtdcr EBC0_CFGADDR, r3
1437 lis r3, PBxAP_VAL@h
1438 ori r3, r3, PBxAP_VAL@l
1439 mtdcr EBC0_CFGDATA, r3
1440
1441 li r3, PBxCR
1442 mtdcr EBC0_CFGADDR, r3
1443 lis r3, PBxCR_VAL@h
1444 ori r3, r3, PBxCR_VAL@l
1445 mtdcr EBC0_CFGDATA, r3
1446 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1447
1448 /* Restore registers */
1449 mr r3, r9
1450 mr r4, r10
1451 mr r5, r11
1452 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1453
1454 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1455 /*
1456 * Unlock the previously locked d-cache
1457 */
1458 msync
1459 isync
1460 /* set TFLOOR/NFLOOR to 0 again */
1461 lis r6,0x0001
1462 ori r6,r6,0xf800
1463 mtspr SPRN_DVLIM,r6
1464 lis r6,0x0000
1465 ori r6,r6,0x0000
1466 mtspr SPRN_DNV0,r6
1467 mtspr SPRN_DNV1,r6
1468 mtspr SPRN_DNV2,r6
1469 mtspr SPRN_DNV3,r6
1470 mtspr SPRN_DTV0,r6
1471 mtspr SPRN_DTV1,r6
1472 mtspr SPRN_DTV2,r6
1473 mtspr SPRN_DTV3,r6
1474 msync
1475 isync
1476
1477 /* Invalidate data cache, now no longer our stack */
1478 dccci 0,0
1479 sync
1480 isync
1481 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1482
1483 /*
1484 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1485 * to speed up the boot process. Now this cache needs to be disabled.
1486 */
1487 #if defined(CONFIG_440)
1488 /* Clear all potential pending exceptions */
1489 mfspr r1,SPRN_MCSR
1490 mtspr SPRN_MCSR,r1
1491 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1492 tlbre r0,r1,0x0002 /* Read contents */
1493 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1494 tlbwe r0,r1,0x0002 /* Save it out */
1495 sync
1496 isync
1497 #endif /* defined(CONFIG_440) */
1498 mr r1, r3 /* Set new stack pointer */
1499 mr r9, r4 /* Save copy of Init Data pointer */
1500 mr r10, r5 /* Save copy of Destination Address */
1501
1502 GET_GOT
1503 mr r3, r5 /* Destination Address */
1504 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1505 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1506 lwz r5, GOT(__init_end)
1507 sub r5, r5, r4
1508 li r6, L1_CACHE_BYTES /* Cache Line Size */
1509
1510 /*
1511 * Fix GOT pointer:
1512 *
1513 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1514 *
1515 * Offset:
1516 */
1517 sub r15, r10, r4
1518
1519 /* First our own GOT */
1520 add r12, r12, r15
1521 /* then the one used by the C code */
1522 add r30, r30, r15
1523
1524 /*
1525 * Now relocate code
1526 */
1527
1528 cmplw cr1,r3,r4
1529 addi r0,r5,3
1530 srwi. r0,r0,2
1531 beq cr1,4f /* In place copy is not necessary */
1532 beq 7f /* Protect against 0 count */
1533 mtctr r0
1534 bge cr1,2f
1535
1536 la r8,-4(r4)
1537 la r7,-4(r3)
1538 1: lwzu r0,4(r8)
1539 stwu r0,4(r7)
1540 bdnz 1b
1541 b 4f
1542
1543 2: slwi r0,r0,2
1544 add r8,r4,r0
1545 add r7,r3,r0
1546 3: lwzu r0,-4(r8)
1547 stwu r0,-4(r7)
1548 bdnz 3b
1549
1550 /*
1551 * Now flush the cache: note that we must start from a cache aligned
1552 * address. Otherwise we might miss one cache line.
1553 */
1554 4: cmpwi r6,0
1555 add r5,r3,r5
1556 beq 7f /* Always flush prefetch queue in any case */
1557 subi r0,r6,1
1558 andc r3,r3,r0
1559 mr r4,r3
1560 5: dcbst 0,r4
1561 add r4,r4,r6
1562 cmplw r4,r5
1563 blt 5b
1564 sync /* Wait for all dcbst to complete on bus */
1565 mr r4,r3
1566 6: icbi 0,r4
1567 add r4,r4,r6
1568 cmplw r4,r5
1569 blt 6b
1570 7: sync /* Wait for all icbi to complete on bus */
1571 isync
1572
1573 /*
1574 * We are done. Do not return, instead branch to second part of board
1575 * initialization, now running from RAM.
1576 */
1577
1578 addi r0, r10, in_ram - _start + _START_OFFSET
1579 mtlr r0
1580 blr /* NEVER RETURNS! */
1581
1582 in_ram:
1583
1584 /*
1585 * Relocation Function, r12 point to got2+0x8000
1586 *
1587 * Adjust got2 pointers, no need to check for 0, this code
1588 * already puts a few entries in the table.
1589 */
1590 li r0,__got2_entries@sectoff@l
1591 la r3,GOT(_GOT2_TABLE_)
1592 lwz r11,GOT(_GOT2_TABLE_)
1593 mtctr r0
1594 sub r11,r3,r11
1595 addi r3,r3,-4
1596 1: lwzu r0,4(r3)
1597 cmpwi r0,0
1598 beq- 2f
1599 add r0,r0,r11
1600 stw r0,0(r3)
1601 2: bdnz 1b
1602
1603 /*
1604 * Now adjust the fixups and the pointers to the fixups
1605 * in case we need to move ourselves again.
1606 */
1607 li r0,__fixup_entries@sectoff@l
1608 lwz r3,GOT(_FIXUP_TABLE_)
1609 cmpwi r0,0
1610 mtctr r0
1611 addi r3,r3,-4
1612 beq 4f
1613 3: lwzu r4,4(r3)
1614 lwzux r0,r4,r11
1615 cmpwi r0,0
1616 add r0,r0,r11
1617 stw r4,0(r3)
1618 beq- 5f
1619 stw r0,0(r4)
1620 5: bdnz 3b
1621 4:
1622 clear_bss:
1623 /*
1624 * Now clear BSS segment
1625 */
1626 lwz r3,GOT(__bss_start)
1627 lwz r4,GOT(__bss_end__)
1628
1629 cmplw 0, r3, r4
1630 beq 7f
1631
1632 li r0, 0
1633
1634 andi. r5, r4, 3
1635 beq 6f
1636 sub r4, r4, r5
1637 mtctr r5
1638 mr r5, r4
1639 5: stb r0, 0(r5)
1640 addi r5, r5, 1
1641 bdnz 5b
1642 6:
1643 stw r0, 0(r3)
1644 addi r3, r3, 4
1645 cmplw 0, r3, r4
1646 bne 6b
1647
1648 7:
1649 mr r3, r9 /* Init Data pointer */
1650 mr r4, r10 /* Destination Address */
1651 bl board_init_r
1652
1653 /*
1654 * Copy exception vector code to low memory
1655 *
1656 * r3: dest_addr
1657 * r7: source address, r8: end address, r9: target address
1658 */
1659 .globl trap_init
1660 trap_init:
1661 mflr r4 /* save link register */
1662 GET_GOT
1663 lwz r7, GOT(_start_of_vectors)
1664 lwz r8, GOT(_end_of_vectors)
1665
1666 li r9, 0x100 /* reset vector always at 0x100 */
1667
1668 cmplw 0, r7, r8
1669 bgelr /* return if r7>=r8 - just in case */
1670 1:
1671 lwz r0, 0(r7)
1672 stw r0, 0(r9)
1673 addi r7, r7, 4
1674 addi r9, r9, 4
1675 cmplw 0, r7, r8
1676 bne 1b
1677
1678 /*
1679 * relocate `hdlr' and `int_return' entries
1680 */
1681 li r7, .L_MachineCheck - _start + _START_OFFSET
1682 li r8, Alignment - _start + _START_OFFSET
1683 2:
1684 bl trap_reloc
1685 addi r7, r7, 0x100 /* next exception vector */
1686 cmplw 0, r7, r8
1687 blt 2b
1688
1689 li r7, .L_Alignment - _start + _START_OFFSET
1690 bl trap_reloc
1691
1692 li r7, .L_ProgramCheck - _start + _START_OFFSET
1693 bl trap_reloc
1694
1695 #ifdef CONFIG_440
1696 li r7, .L_FPUnavailable - _start + _START_OFFSET
1697 bl trap_reloc
1698
1699 li r7, .L_Decrementer - _start + _START_OFFSET
1700 bl trap_reloc
1701
1702 li r7, .L_APU - _start + _START_OFFSET
1703 bl trap_reloc
1704
1705 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1706 bl trap_reloc
1707
1708 li r7, .L_DataTLBError - _start + _START_OFFSET
1709 bl trap_reloc
1710 #else /* CONFIG_440 */
1711 li r7, .L_PIT - _start + _START_OFFSET
1712 bl trap_reloc
1713
1714 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1715 bl trap_reloc
1716
1717 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1718 bl trap_reloc
1719 #endif /* CONFIG_440 */
1720
1721 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1722 bl trap_reloc
1723
1724 #if !defined(CONFIG_440)
1725 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1726 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1727 mtmsr r7 /* change MSR */
1728 #else
1729 bl __440_msr_set
1730 b __440_msr_continue
1731
1732 __440_msr_set:
1733 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1734 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1735 mtspr SPRN_SRR1,r7
1736 mflr r7
1737 mtspr SPRN_SRR0,r7
1738 rfi
1739 __440_msr_continue:
1740 #endif
1741
1742 mtlr r4 /* restore link register */
1743 blr
1744
1745 #if defined(CONFIG_440)
1746 /*----------------------------------------------------------------------------+
1747 | dcbz_area.
1748 +----------------------------------------------------------------------------*/
1749 function_prolog(dcbz_area)
1750 rlwinm. r5,r4,0,27,31
1751 rlwinm r5,r4,27,5,31
1752 beq ..d_ra2
1753 addi r5,r5,0x0001
1754 ..d_ra2:mtctr r5
1755 ..d_ag2:dcbz r0,r3
1756 addi r3,r3,32
1757 bdnz ..d_ag2
1758 sync
1759 blr
1760 function_epilog(dcbz_area)
1761 #endif /* CONFIG_440 */
1762 #endif /* CONFIG_NAND_SPL */
1763
1764 /*------------------------------------------------------------------------------- */
1765 /* Function: in8 */
1766 /* Description: Input 8 bits */
1767 /*------------------------------------------------------------------------------- */
1768 .globl in8
1769 in8:
1770 lbz r3,0x0000(r3)
1771 blr
1772
1773 /*------------------------------------------------------------------------------- */
1774 /* Function: out8 */
1775 /* Description: Output 8 bits */
1776 /*------------------------------------------------------------------------------- */
1777 .globl out8
1778 out8:
1779 stb r4,0x0000(r3)
1780 blr
1781
1782 /*------------------------------------------------------------------------------- */
1783 /* Function: out32 */
1784 /* Description: Output 32 bits */
1785 /*------------------------------------------------------------------------------- */
1786 .globl out32
1787 out32:
1788 stw r4,0x0000(r3)
1789 blr
1790
1791 /*------------------------------------------------------------------------------- */
1792 /* Function: in32 */
1793 /* Description: Input 32 bits */
1794 /*------------------------------------------------------------------------------- */
1795 .globl in32
1796 in32:
1797 lwz 3,0x0000(3)
1798 blr
1799
1800 /**************************************************************************/
1801 /* PPC405EP specific stuff */
1802 /**************************************************************************/
1803 #ifdef CONFIG_405EP
1804 ppc405ep_init:
1805
1806 #ifdef CONFIG_BUBINGA
1807 /*
1808 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1809 * function) to support FPGA and NVRAM accesses below.
1810 */
1811
1812 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1813 ori r3,r3,GPIO0_OSRH@l
1814 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1815 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1816 stw r4,0(r3)
1817 lis r3,GPIO0_OSRL@h
1818 ori r3,r3,GPIO0_OSRL@l
1819 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1820 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1821 stw r4,0(r3)
1822
1823 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1824 ori r3,r3,GPIO0_ISR1H@l
1825 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1826 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1827 stw r4,0(r3)
1828 lis r3,GPIO0_ISR1L@h
1829 ori r3,r3,GPIO0_ISR1L@l
1830 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1831 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1832 stw r4,0(r3)
1833
1834 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1835 ori r3,r3,GPIO0_TSRH@l
1836 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1837 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1838 stw r4,0(r3)
1839 lis r3,GPIO0_TSRL@h
1840 ori r3,r3,GPIO0_TSRL@l
1841 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1842 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1843 stw r4,0(r3)
1844
1845 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1846 ori r3,r3,GPIO0_TCR@l
1847 lis r4,CONFIG_SYS_GPIO0_TCR@h
1848 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1849 stw r4,0(r3)
1850
1851 li r3,PB1AP /* program EBC bank 1 for RTC access */
1852 mtdcr EBC0_CFGADDR,r3
1853 lis r3,CONFIG_SYS_EBC_PB1AP@h
1854 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1855 mtdcr EBC0_CFGDATA,r3
1856 li r3,PB1CR
1857 mtdcr EBC0_CFGADDR,r3
1858 lis r3,CONFIG_SYS_EBC_PB1CR@h
1859 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1860 mtdcr EBC0_CFGDATA,r3
1861
1862 li r3,PB1AP /* program EBC bank 1 for RTC access */
1863 mtdcr EBC0_CFGADDR,r3
1864 lis r3,CONFIG_SYS_EBC_PB1AP@h
1865 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1866 mtdcr EBC0_CFGDATA,r3
1867 li r3,PB1CR
1868 mtdcr EBC0_CFGADDR,r3
1869 lis r3,CONFIG_SYS_EBC_PB1CR@h
1870 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1871 mtdcr EBC0_CFGDATA,r3
1872
1873 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1874 mtdcr EBC0_CFGADDR,r3
1875 lis r3,CONFIG_SYS_EBC_PB4AP@h
1876 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1877 mtdcr EBC0_CFGDATA,r3
1878 li r3,PB4CR
1879 mtdcr EBC0_CFGADDR,r3
1880 lis r3,CONFIG_SYS_EBC_PB4CR@h
1881 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1882 mtdcr EBC0_CFGDATA,r3
1883 #endif
1884
1885 /*
1886 !-----------------------------------------------------------------------
1887 ! Check to see if chip is in bypass mode.
1888 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1889 ! CPU reset Otherwise, skip this step and keep going.
1890 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1891 ! will not be fast enough for the SDRAM (min 66MHz)
1892 !-----------------------------------------------------------------------
1893 */
1894 mfdcr r5, CPC0_PLLMR1
1895 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1896 cmpi cr0,0,r4,0x1
1897
1898 beq pll_done /* if SSCS =b'1' then PLL has */
1899 /* already been set */
1900 /* and CPU has been reset */
1901 /* so skip to next section */
1902
1903 #ifdef CONFIG_BUBINGA
1904 /*
1905 !-----------------------------------------------------------------------
1906 ! Read NVRAM to get value to write in PLLMR.
1907 ! If value has not been correctly saved, write default value
1908 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1909 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1910 !
1911 ! WARNING: This code assumes the first three words in the nvram_t
1912 ! structure in openbios.h. Changing the beginning of
1913 ! the structure will break this code.
1914 !
1915 !-----------------------------------------------------------------------
1916 */
1917 addis r3,0,NVRAM_BASE@h
1918 addi r3,r3,NVRAM_BASE@l
1919
1920 lwz r4, 0(r3)
1921 addis r5,0,NVRVFY1@h
1922 addi r5,r5,NVRVFY1@l
1923 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1924 bne ..no_pllset
1925 addi r3,r3,4
1926 lwz r4, 0(r3)
1927 addis r5,0,NVRVFY2@h
1928 addi r5,r5,NVRVFY2@l
1929 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1930 bne ..no_pllset
1931 addi r3,r3,8 /* Skip over conf_size */
1932 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1933 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1934 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1935 cmpi cr0,0,r5,1 /* See if PLL is locked */
1936 beq pll_write
1937 ..no_pllset:
1938 #endif /* CONFIG_BUBINGA */
1939
1940 #ifdef CONFIG_TAIHU
1941 mfdcr r4, CPC0_BOOT
1942 andi. r5, r4, CPC0_BOOT_SEP@l
1943 bne strap_1 /* serial eeprom present */
1944 addis r5,0,CPLD_REG0_ADDR@h
1945 ori r5,r5,CPLD_REG0_ADDR@l
1946 andi. r5, r5, 0x10
1947 bne _pci_66mhz
1948 #endif /* CONFIG_TAIHU */
1949
1950 #if defined(CONFIG_ZEUS)
1951 mfdcr r4, CPC0_BOOT
1952 andi. r5, r4, CPC0_BOOT_SEP@l
1953 bne strap_1 /* serial eeprom present */
1954 lis r3,0x0000
1955 addi r3,r3,0x3030
1956 lis r4,0x8042
1957 addi r4,r4,0x223e
1958 b 1f
1959 strap_1:
1960 mfdcr r3, CPC0_PLLMR0
1961 mfdcr r4, CPC0_PLLMR1
1962 b 1f
1963 #endif
1964
1965 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1966 ori r3,r3,PLLMR0_DEFAULT@l /* */
1967 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1968 ori r4,r4,PLLMR1_DEFAULT@l /* */
1969
1970 #ifdef CONFIG_TAIHU
1971 b 1f
1972 _pci_66mhz:
1973 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1974 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1975 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1976 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1977 b 1f
1978 strap_1:
1979 mfdcr r3, CPC0_PLLMR0
1980 mfdcr r4, CPC0_PLLMR1
1981 #endif /* CONFIG_TAIHU */
1982
1983 1:
1984 b pll_write /* Write the CPC0_PLLMR with new value */
1985
1986 pll_done:
1987 /*
1988 !-----------------------------------------------------------------------
1989 ! Clear Soft Reset Register
1990 ! This is needed to enable PCI if not booting from serial EPROM
1991 !-----------------------------------------------------------------------
1992 */
1993 addi r3, 0, 0x0
1994 mtdcr CPC0_SRR, r3
1995
1996 addis r3,0,0x0010
1997 mtctr r3
1998 pci_wait:
1999 bdnz pci_wait
2000
2001 blr /* return to main code */
2002
2003 /*
2004 !-----------------------------------------------------------------------------
2005 ! Function: pll_write
2006 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
2007 ! That is:
2008 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
2009 ! 2. PLL is reset
2010 ! 3. Clock dividers are set while PLL is held in reset and bypassed
2011 ! 4. PLL Reset is cleared
2012 ! 5. Wait 100us for PLL to lock
2013 ! 6. A core reset is performed
2014 ! Input: r3 = Value to write to CPC0_PLLMR0
2015 ! Input: r4 = Value to write to CPC0_PLLMR1
2016 ! Output r3 = none
2017 !-----------------------------------------------------------------------------
2018 */
2019 .globl pll_write
2020 pll_write:
2021 mfdcr r5, CPC0_UCR
2022 andis. r5,r5,0xFFFF
2023 ori r5,r5,0x0101 /* Stop the UART clocks */
2024 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2025
2026 mfdcr r5, CPC0_PLLMR1
2027 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2028 mtdcr CPC0_PLLMR1,r5
2029 oris r5,r5,0x4000 /* Set PLL Reset */
2030 mtdcr CPC0_PLLMR1,r5
2031
2032 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2033 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2034 oris r5,r5,0x4000 /* Set PLL Reset */
2035 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2036 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2037 mtdcr CPC0_PLLMR1,r5
2038
2039 /*
2040 ! Wait min of 100us for PLL to lock.
2041 ! See CMOS 27E databook for more info.
2042 ! At 200MHz, that means waiting 20,000 instructions
2043 */
2044 addi r3,0,20000 /* 2000 = 0x4e20 */
2045 mtctr r3
2046 pll_wait:
2047 bdnz pll_wait
2048
2049 oris r5,r5,0x8000 /* Enable PLL */
2050 mtdcr CPC0_PLLMR1,r5 /* Engage */
2051
2052 /*
2053 * Reset CPU to guarantee timings are OK
2054 * Not sure if this is needed...
2055 */
2056 addis r3,0,0x1000
2057 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
2058 /* execution will continue from the poweron */
2059 /* vector of 0xfffffffc */
2060 #endif /* CONFIG_405EP */
2061
2062 #if defined(CONFIG_440)
2063 /*----------------------------------------------------------------------------+
2064 | mttlb3.
2065 +----------------------------------------------------------------------------*/
2066 function_prolog(mttlb3)
2067 TLBWE(4,3,2)
2068 blr
2069 function_epilog(mttlb3)
2070
2071 /*----------------------------------------------------------------------------+
2072 | mftlb3.
2073 +----------------------------------------------------------------------------*/
2074 function_prolog(mftlb3)
2075 TLBRE(3,3,2)
2076 blr
2077 function_epilog(mftlb3)
2078
2079 /*----------------------------------------------------------------------------+
2080 | mttlb2.
2081 +----------------------------------------------------------------------------*/
2082 function_prolog(mttlb2)
2083 TLBWE(4,3,1)
2084 blr
2085 function_epilog(mttlb2)
2086
2087 /*----------------------------------------------------------------------------+
2088 | mftlb2.
2089 +----------------------------------------------------------------------------*/
2090 function_prolog(mftlb2)
2091 TLBRE(3,3,1)
2092 blr
2093 function_epilog(mftlb2)
2094
2095 /*----------------------------------------------------------------------------+
2096 | mttlb1.
2097 +----------------------------------------------------------------------------*/
2098 function_prolog(mttlb1)
2099 TLBWE(4,3,0)
2100 blr
2101 function_epilog(mttlb1)
2102
2103 /*----------------------------------------------------------------------------+
2104 | mftlb1.
2105 +----------------------------------------------------------------------------*/
2106 function_prolog(mftlb1)
2107 TLBRE(3,3,0)
2108 blr
2109 function_epilog(mftlb1)
2110 #endif /* CONFIG_440 */
2111
2112 #if defined(CONFIG_NAND_SPL)
2113 /*
2114 * void nand_boot_relocate(dst, src, bytes)
2115 *
2116 * r3 = Destination address to copy code to (in SDRAM)
2117 * r4 = Source address to copy code from
2118 * r5 = size to copy in bytes
2119 */
2120 nand_boot_relocate:
2121 mr r6,r3
2122 mr r7,r4
2123 mflr r8
2124
2125 /*
2126 * Copy SPL from icache into SDRAM
2127 */
2128 subi r3,r3,4
2129 subi r4,r4,4
2130 srwi r5,r5,2
2131 mtctr r5
2132 ..spl_loop:
2133 lwzu r0,4(r4)
2134 stwu r0,4(r3)
2135 bdnz ..spl_loop
2136
2137 /*
2138 * Calculate "corrected" link register, so that we "continue"
2139 * in execution in destination range
2140 */
2141 sub r3,r7,r6 /* r3 = src - dst */
2142 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2143 mtlr r8
2144 blr
2145
2146 nand_boot_common:
2147 /*
2148 * First initialize SDRAM. It has to be available *before* calling
2149 * nand_boot().
2150 */
2151 lis r3,CONFIG_SYS_SDRAM_BASE@h
2152 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2153 bl initdram
2154
2155 /*
2156 * Now copy the 4k SPL code into SDRAM and continue execution
2157 * from there.
2158 */
2159 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2160 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2161 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2162 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2163 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2164 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2165 bl nand_boot_relocate
2166
2167 /*
2168 * We're running from SDRAM now!!!
2169 *
2170 * It is necessary for 4xx systems to relocate from running at
2171 * the original location (0xfffffxxx) to somewhere else (SDRAM
2172 * preferably). This is because CS0 needs to be reconfigured for
2173 * NAND access. And we can't reconfigure this CS when currently
2174 * "running" from it.
2175 */
2176
2177 /*
2178 * Finally call nand_boot() to load main NAND U-Boot image from
2179 * NAND and jump to it.
2180 */
2181 bl nand_boot /* will not return */
2182 #endif /* CONFIG_NAND_SPL */
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