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Fix board init code to respect the C runtime environment
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / start.S
1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
10 */
11
12 /*
13 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
14 *
15 * The following description only applies to the NOR flash style booting.
16 * NAND booting is different. For more details about NAND booting on 4xx
17 * take a look at doc/README.nand-boot-ppc440.
18 *
19 * The CPU starts at address 0xfffffffc (last word in the address space).
20 * The U-Boot image therefore has to be located in the "upper" area of the
21 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
22 * the boot chip-select (CS0) is quite big and covers this area. On the
23 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
24 * reconfigure this CS0 (and other chip-selects as well when configured
25 * this way) in the boot process to the "correct" values matching the
26 * board layout.
27 */
28
29 #include <asm-offsets.h>
30 #include <config.h>
31 #include <asm/ppc4xx.h>
32 #include <version.h>
33
34 #include <ppc_asm.tmpl>
35 #include <ppc_defs.h>
36
37 #include <asm/cache.h>
38 #include <asm/mmu.h>
39 #include <asm/ppc4xx-isram.h>
40
41 #ifdef CONFIG_SYS_INIT_DCACHE_CS
42 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
43 # define PBxAP PB1AP
44 # define PBxCR PB0CR
45 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
46 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
47 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
48 # endif
49 # endif
50 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
51 # define PBxAP PB1AP
52 # define PBxCR PB1CR
53 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
54 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
55 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
56 # endif
57 # endif
58 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
59 # define PBxAP PB2AP
60 # define PBxCR PB2CR
61 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
62 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
63 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
64 # endif
65 # endif
66 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
67 # define PBxAP PB3AP
68 # define PBxCR PB3CR
69 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
70 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
71 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
72 # endif
73 # endif
74 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
75 # define PBxAP PB4AP
76 # define PBxCR PB4CR
77 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
78 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
79 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
80 # endif
81 # endif
82 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
83 # define PBxAP PB5AP
84 # define PBxCR PB5CR
85 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
86 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
87 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
88 # endif
89 # endif
90 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
91 # define PBxAP PB6AP
92 # define PBxCR PB6CR
93 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
94 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
95 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
96 # endif
97 # endif
98 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
99 # define PBxAP PB7AP
100 # define PBxCR PB7CR
101 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
102 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
103 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
104 # endif
105 # endif
106 # ifndef PBxAP_VAL
107 # define PBxAP_VAL 0
108 # endif
109 # ifndef PBxCR_VAL
110 # define PBxCR_VAL 0
111 # endif
112 /*
113 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
114 * used as temporary stack pointer for the primordial stack
115 */
116 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
117 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
118 EBC_BXAP_TWT_ENCODE(7) | \
119 EBC_BXAP_BCE_DISABLE | \
120 EBC_BXAP_BCT_2TRANS | \
121 EBC_BXAP_CSN_ENCODE(0) | \
122 EBC_BXAP_OEN_ENCODE(0) | \
123 EBC_BXAP_WBN_ENCODE(0) | \
124 EBC_BXAP_WBF_ENCODE(0) | \
125 EBC_BXAP_TH_ENCODE(2) | \
126 EBC_BXAP_RE_DISABLED | \
127 EBC_BXAP_SOR_NONDELAYED | \
128 EBC_BXAP_BEM_WRITEONLY | \
129 EBC_BXAP_PEN_DISABLED)
130 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
131 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
132 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
133 EBC_BXCR_BS_64MB | \
134 EBC_BXCR_BU_RW | \
135 EBC_BXCR_BW_16BIT)
136 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
137 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
138 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
139 # endif
140 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
141
142 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
143 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
144 #endif
145
146 /*
147 * Unless otherwise overriden, enable two 128MB cachable instruction regions
148 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
149 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
150 */
151 #if !defined(CONFIG_SYS_FLASH_BASE)
152 /* If not already defined, set it to the "last" 128MByte region */
153 # define CONFIG_SYS_FLASH_BASE 0xf8000000
154 #endif
155 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
156 # define CONFIG_SYS_ICACHE_SACR_VALUE \
157 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
158 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
159 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
160 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
161
162 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
163 # define CONFIG_SYS_DCACHE_SACR_VALUE \
164 (0x00000000)
165 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
166
167 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
168 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
169 #endif
170
171 #define function_prolog(func_name) .text; \
172 .align 2; \
173 .globl func_name; \
174 func_name:
175 #define function_epilog(func_name) .type func_name,@function; \
176 .size func_name,.-func_name
177
178 /* We don't want the MMU yet.
179 */
180 #undef MSR_KERNEL
181 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
182
183
184 .extern ext_bus_cntlr_init
185
186 /*
187 * Set up GOT: Global Offset Table
188 *
189 * Use r12 to access the GOT
190 */
191 #if !defined(CONFIG_SPL_BUILD)
192 START_GOT
193 GOT_ENTRY(_GOT2_TABLE_)
194 GOT_ENTRY(_FIXUP_TABLE_)
195
196 GOT_ENTRY(_start)
197 GOT_ENTRY(_start_of_vectors)
198 GOT_ENTRY(_end_of_vectors)
199 GOT_ENTRY(transfer_to_handler)
200
201 GOT_ENTRY(__init_end)
202 GOT_ENTRY(__bss_end)
203 GOT_ENTRY(__bss_start)
204 END_GOT
205 #endif /* CONFIG_SPL_BUILD */
206
207 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
208 /*
209 * 4xx RAM-booting U-Boot image is started from offset 0
210 */
211 .text
212 bl _start_440
213 #endif
214
215 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
216 /*
217 * This is the entry of the real U-Boot from a board port
218 * that supports SPL booting on the PPC4xx. We only need
219 * to call board_init_f() here. Everything else has already
220 * been done in the SPL u-boot version.
221 */
222 GET_GOT /* initialize GOT access */
223 bl board_init_f /* run 1st part of board init code (in Flash)*/
224 /* NOTREACHED - board_init_f() does not return */
225 #endif
226
227 /*
228 * 440 Startup -- on reset only the top 4k of the effective
229 * address space is mapped in by an entry in the instruction
230 * and data shadow TLB. The .bootpg section is located in the
231 * top 4k & does only what's necessary to map in the the rest
232 * of the boot rom. Once the boot rom is mapped in we can
233 * proceed with normal startup.
234 *
235 * NOTE: CS0 only covers the top 2MB of the effective address
236 * space after reset.
237 */
238
239 #if defined(CONFIG_440)
240 .section .bootpg,"ax"
241 .globl _start_440
242
243 /**************************************************************************/
244 _start_440:
245 /*--------------------------------------------------------------------+
246 | 440EPX BUP Change - Hardware team request
247 +--------------------------------------------------------------------*/
248 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
249 sync
250 nop
251 nop
252 #endif
253 /*----------------------------------------------------------------+
254 | Core bug fix. Clear the esr
255 +-----------------------------------------------------------------*/
256 li r0,0
257 mtspr SPRN_ESR,r0
258 /*----------------------------------------------------------------*/
259 /* Clear and set up some registers. */
260 /*----------------------------------------------------------------*/
261 iccci r0,r0 /* NOTE: operands not used for 440 */
262 dccci r0,r0 /* NOTE: operands not used for 440 */
263 sync
264 li r0,0
265 mtspr SPRN_SRR0,r0
266 mtspr SPRN_SRR1,r0
267 mtspr SPRN_CSRR0,r0
268 mtspr SPRN_CSRR1,r0
269 /* NOTE: 440GX adds machine check status regs */
270 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
271 mtspr SPRN_MCSRR0,r0
272 mtspr SPRN_MCSRR1,r0
273 mfspr r1,SPRN_MCSR
274 mtspr SPRN_MCSR,r1
275 #endif
276
277 /*----------------------------------------------------------------*/
278 /* CCR0 init */
279 /*----------------------------------------------------------------*/
280 /* Disable store gathering & broadcast, guarantee inst/data
281 * cache block touch, force load/store alignment
282 * (see errata 1.12: 440_33)
283 */
284 lis r1,0x0030 /* store gathering & broadcast disable */
285 ori r1,r1,0x6000 /* cache touch */
286 mtspr SPRN_CCR0,r1
287
288 /*----------------------------------------------------------------*/
289 /* Initialize debug */
290 /*----------------------------------------------------------------*/
291 mfspr r1,SPRN_DBCR0
292 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
293 bne skip_debug_init /* if set, don't clear debug register */
294 mfspr r1,SPRN_CCR0
295 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
296 mtspr SPRN_CCR0,r1
297 mtspr SPRN_DBCR0,r0
298 mtspr SPRN_DBCR1,r0
299 mtspr SPRN_DBCR2,r0
300 mtspr SPRN_IAC1,r0
301 mtspr SPRN_IAC2,r0
302 mtspr SPRN_IAC3,r0
303 mtspr SPRN_DAC1,r0
304 mtspr SPRN_DAC2,r0
305 mtspr SPRN_DVC1,r0
306 mtspr SPRN_DVC2,r0
307
308 mfspr r1,SPRN_DBSR
309 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
310 skip_debug_init:
311
312 #if defined (CONFIG_440SPE)
313 /*----------------------------------------------------------------+
314 | Initialize Core Configuration Reg1.
315 | a. ICDPEI: Record even parity. Normal operation.
316 | b. ICTPEI: Record even parity. Normal operation.
317 | c. DCTPEI: Record even parity. Normal operation.
318 | d. DCDPEI: Record even parity. Normal operation.
319 | e. DCUPEI: Record even parity. Normal operation.
320 | f. DCMPEI: Record even parity. Normal operation.
321 | g. FCOM: Normal operation
322 | h. MMUPEI: Record even parity. Normal operation.
323 | i. FFF: Flush only as much data as necessary.
324 | j. TCS: Timebase increments from CPU clock.
325 +-----------------------------------------------------------------*/
326 li r0,0
327 mtspr SPRN_CCR1, r0
328
329 /*----------------------------------------------------------------+
330 | Reset the timebase.
331 | The previous write to CCR1 sets the timebase source.
332 +-----------------------------------------------------------------*/
333 mtspr SPRN_TBWL, r0
334 mtspr SPRN_TBWU, r0
335 #endif
336
337 /*----------------------------------------------------------------*/
338 /* Setup interrupt vectors */
339 /*----------------------------------------------------------------*/
340 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
341 li r1,0x0100
342 mtspr SPRN_IVOR0,r1 /* Critical input */
343 li r1,0x0200
344 mtspr SPRN_IVOR1,r1 /* Machine check */
345 li r1,0x0300
346 mtspr SPRN_IVOR2,r1 /* Data storage */
347 li r1,0x0400
348 mtspr SPRN_IVOR3,r1 /* Instruction storage */
349 li r1,0x0500
350 mtspr SPRN_IVOR4,r1 /* External interrupt */
351 li r1,0x0600
352 mtspr SPRN_IVOR5,r1 /* Alignment */
353 li r1,0x0700
354 mtspr SPRN_IVOR6,r1 /* Program check */
355 li r1,0x0800
356 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
357 li r1,0x0c00
358 mtspr SPRN_IVOR8,r1 /* System call */
359 li r1,0x0a00
360 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
361 li r1,0x0900
362 mtspr SPRN_IVOR10,r1 /* Decrementer */
363 li r1,0x1300
364 mtspr SPRN_IVOR13,r1 /* Data TLB error */
365 li r1,0x1400
366 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
367 li r1,0x2000
368 mtspr SPRN_IVOR15,r1 /* Debug */
369
370 /*----------------------------------------------------------------*/
371 /* Configure cache regions */
372 /*----------------------------------------------------------------*/
373 mtspr SPRN_INV0,r0
374 mtspr SPRN_INV1,r0
375 mtspr SPRN_INV2,r0
376 mtspr SPRN_INV3,r0
377 mtspr SPRN_DNV0,r0
378 mtspr SPRN_DNV1,r0
379 mtspr SPRN_DNV2,r0
380 mtspr SPRN_DNV3,r0
381 mtspr SPRN_ITV0,r0
382 mtspr SPRN_ITV1,r0
383 mtspr SPRN_ITV2,r0
384 mtspr SPRN_ITV3,r0
385 mtspr SPRN_DTV0,r0
386 mtspr SPRN_DTV1,r0
387 mtspr SPRN_DTV2,r0
388 mtspr SPRN_DTV3,r0
389
390 /*----------------------------------------------------------------*/
391 /* Cache victim limits */
392 /*----------------------------------------------------------------*/
393 /* floors 0, ceiling max to use the entire cache -- nothing locked
394 */
395 lis r1,0x0001
396 ori r1,r1,0xf800
397 mtspr SPRN_IVLIM,r1
398 mtspr SPRN_DVLIM,r1
399
400 /*----------------------------------------------------------------+
401 |Initialize MMUCR[STID] = 0.
402 +-----------------------------------------------------------------*/
403 mfspr r0,SPRN_MMUCR
404 addis r1,0,0xFFFF
405 ori r1,r1,0xFF00
406 and r0,r0,r1
407 mtspr SPRN_MMUCR,r0
408
409 /*----------------------------------------------------------------*/
410 /* Clear all TLB entries -- TID = 0, TS = 0 */
411 /*----------------------------------------------------------------*/
412 addis r0,0,0x0000
413 #ifdef CONFIG_SYS_RAMBOOT
414 li r4,0 /* Start with TLB #0 */
415 #else
416 li r4,1 /* Start with TLB #1 */
417 #endif
418 li r1,64 /* 64 TLB entries */
419 sub r1,r1,r4 /* calculate last TLB # */
420 mtctr r1
421 rsttlb:
422 #ifdef CONFIG_SYS_RAMBOOT
423 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
424 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
425 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
426 #endif
427 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
428 tlbwe r0,r4,1
429 tlbwe r0,r4,2
430 tlbnxt: addi r4,r4,1 /* Next TLB */
431 bdnz rsttlb
432
433 /*----------------------------------------------------------------*/
434 /* TLB entry setup -- step thru tlbtab */
435 /*----------------------------------------------------------------*/
436 #if defined(CONFIG_440SPE_REVA)
437 /*----------------------------------------------------------------*/
438 /* We have different TLB tables for revA and rev B of 440SPe */
439 /*----------------------------------------------------------------*/
440 mfspr r1, PVR
441 lis r0,0x5342
442 ori r0,r0,0x1891
443 cmpw r7,r1,r0
444 bne r7,..revA
445 bl tlbtabB
446 b ..goon
447 ..revA:
448 bl tlbtabA
449 ..goon:
450 #else
451 bl tlbtab /* Get tlbtab pointer */
452 #endif
453 mr r5,r0
454 li r1,0x003f /* 64 TLB entries max */
455 mtctr r1
456 li r4,0 /* TLB # */
457
458 addi r5,r5,-4
459 1:
460 #ifdef CONFIG_SYS_RAMBOOT
461 tlbre r3,r4,0 /* Read contents from TLB word #0 */
462 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
463 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
464 #endif
465 lwzu r0,4(r5)
466 cmpwi r0,0
467 beq 2f /* 0 marks end */
468 lwzu r1,4(r5)
469 lwzu r2,4(r5)
470 tlbwe r0,r4,0 /* TLB Word 0 */
471 tlbwe r1,r4,1 /* TLB Word 1 */
472 tlbwe r2,r4,2 /* TLB Word 2 */
473 tlbnx2: addi r4,r4,1 /* Next TLB */
474 bdnz 1b
475
476 /*----------------------------------------------------------------*/
477 /* Continue from 'normal' start */
478 /*----------------------------------------------------------------*/
479 2:
480 bl 3f
481 b _start
482
483 3: li r0,0
484 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
485 mflr r1
486 mtspr SPRN_SRR0,r1
487 rfi
488 #endif /* CONFIG_440 */
489
490 /*
491 * r3 - 1st arg to board_init(): IMMP pointer
492 * r4 - 2nd arg to board_init(): boot flag
493 */
494 #if !defined(CONFIG_SPL_BUILD)
495 .text
496 .long 0x27051956 /* U-Boot Magic Number */
497 .globl version_string
498 version_string:
499 .ascii U_BOOT_VERSION_STRING, "\0"
500
501 . = EXC_OFF_SYS_RESET
502 .globl _start_of_vectors
503 _start_of_vectors:
504
505 /* Critical input. */
506 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
507
508 #ifdef CONFIG_440
509 /* Machine check */
510 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
511 #else
512 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
513 #endif /* CONFIG_440 */
514
515 /* Data Storage exception. */
516 STD_EXCEPTION(0x300, DataStorage, UnknownException)
517
518 /* Instruction Storage exception. */
519 STD_EXCEPTION(0x400, InstStorage, UnknownException)
520
521 /* External Interrupt exception. */
522 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
523
524 /* Alignment exception. */
525 . = 0x600
526 Alignment:
527 EXCEPTION_PROLOG(SRR0, SRR1)
528 mfspr r4,DAR
529 stw r4,_DAR(r21)
530 mfspr r5,DSISR
531 stw r5,_DSISR(r21)
532 addi r3,r1,STACK_FRAME_OVERHEAD
533 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
534
535 /* Program check exception */
536 . = 0x700
537 ProgramCheck:
538 EXCEPTION_PROLOG(SRR0, SRR1)
539 addi r3,r1,STACK_FRAME_OVERHEAD
540 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
541 MSR_KERNEL, COPY_EE)
542
543 #ifdef CONFIG_440
544 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
545 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
546 STD_EXCEPTION(0xa00, APU, UnknownException)
547 #endif
548 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
549
550 #ifdef CONFIG_440
551 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
552 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
553 #else
554 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
555 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
556 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
557 #endif
558 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
559
560 .globl _end_of_vectors
561 _end_of_vectors:
562 . = _START_OFFSET
563 #endif
564 .globl _start
565 _start:
566
567 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
568 /*
569 * This is the entry of the real U-Boot from a board port
570 * that supports SPL booting on the PPC4xx. We only need
571 * to call board_init_f() here. Everything else has already
572 * been done in the SPL u-boot version.
573 */
574 GET_GOT /* initialize GOT access */
575 bl board_init_f /* run 1st part of board init code (in Flash)*/
576 /* NOTREACHED - board_init_f() does not return */
577 #endif
578
579 /*****************************************************************************/
580 #if defined(CONFIG_440)
581
582 /*----------------------------------------------------------------*/
583 /* Clear and set up some registers. */
584 /*----------------------------------------------------------------*/
585 li r0,0x0000
586 lis r1,0xffff
587 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
588 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
589 mtspr SPRN_TBWU,r0
590 mtspr SPRN_TSR,r1 /* clear all timer exception status */
591 mtspr SPRN_TCR,r0 /* disable all */
592 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
593 mtxer r0 /* clear integer exception register */
594
595 /*----------------------------------------------------------------*/
596 /* Debug setup -- some (not very good) ice's need an event*/
597 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
598 /* value you need in this case 0x8cff 0000 should do the trick */
599 /*----------------------------------------------------------------*/
600 #if defined(CONFIG_SYS_INIT_DBCR)
601 lis r1,0xffff
602 ori r1,r1,0xffff
603 mtspr SPRN_DBSR,r1 /* Clear all status bits */
604 lis r0,CONFIG_SYS_INIT_DBCR@h
605 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
606 mtspr SPRN_DBCR0,r0
607 isync
608 #endif
609
610 /*----------------------------------------------------------------*/
611 /* Setup the internal SRAM */
612 /*----------------------------------------------------------------*/
613 li r0,0
614
615 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
616 /* Clear Dcache to use as RAM */
617 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
618 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
619 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
620 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
621 rlwinm. r5,r4,0,27,31
622 rlwinm r5,r4,27,5,31
623 beq ..d_ran
624 addi r5,r5,0x0001
625 ..d_ran:
626 mtctr r5
627 ..d_ag:
628 dcbz r0,r3
629 addi r3,r3,32
630 bdnz ..d_ag
631
632 /*
633 * Lock the init-ram/stack in d-cache, so that other regions
634 * may use d-cache as well
635 * Note, that this current implementation locks exactly 4k
636 * of d-cache, so please make sure that you don't define a
637 * bigger init-ram area. Take a look at the lwmon5 440EPx
638 * implementation as a reference.
639 */
640 msync
641 isync
642 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
643 lis r1,0x0201
644 ori r1,r1,0xf808
645 mtspr SPRN_DVLIM,r1
646 lis r1,0x0808
647 ori r1,r1,0x0808
648 mtspr SPRN_DNV0,r1
649 mtspr SPRN_DNV1,r1
650 mtspr SPRN_DNV2,r1
651 mtspr SPRN_DNV3,r1
652 mtspr SPRN_DTV0,r1
653 mtspr SPRN_DTV1,r1
654 mtspr SPRN_DTV2,r1
655 mtspr SPRN_DTV3,r1
656 msync
657 isync
658 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
659
660 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
661 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
662 /* not all PPC's have internal SRAM usable as L2-cache */
663 #if defined(CONFIG_440GX) || \
664 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
665 defined(CONFIG_460SX)
666 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
667 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
668 lis r1, 0x0000
669 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
670 mtdcr L2_CACHE_CFG,r1
671 #endif
672
673 lis r2,0x7fff
674 ori r2,r2,0xffff
675 mfdcr r1,ISRAM0_DPC
676 and r1,r1,r2 /* Disable parity check */
677 mtdcr ISRAM0_DPC,r1
678 mfdcr r1,ISRAM0_PMEG
679 and r1,r1,r2 /* Disable pwr mgmt */
680 mtdcr ISRAM0_PMEG,r1
681
682 lis r1,0x8000 /* BAS = 8000_0000 */
683 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
684 ori r1,r1,0x0980 /* first 64k */
685 mtdcr ISRAM0_SB0CR,r1
686 lis r1,0x8001
687 ori r1,r1,0x0980 /* second 64k */
688 mtdcr ISRAM0_SB1CR,r1
689 lis r1, 0x8002
690 ori r1,r1, 0x0980 /* third 64k */
691 mtdcr ISRAM0_SB2CR,r1
692 lis r1, 0x8003
693 ori r1,r1, 0x0980 /* fourth 64k */
694 mtdcr ISRAM0_SB3CR,r1
695 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
696 defined(CONFIG_460GT)
697 lis r1,0x0000 /* BAS = X_0000_0000 */
698 ori r1,r1,0x0984 /* first 64k */
699 mtdcr ISRAM0_SB0CR,r1
700 lis r1,0x0001
701 ori r1,r1,0x0984 /* second 64k */
702 mtdcr ISRAM0_SB1CR,r1
703 lis r1, 0x0002
704 ori r1,r1, 0x0984 /* third 64k */
705 mtdcr ISRAM0_SB2CR,r1
706 lis r1, 0x0003
707 ori r1,r1, 0x0984 /* fourth 64k */
708 mtdcr ISRAM0_SB3CR,r1
709 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
710 lis r2,0x7fff
711 ori r2,r2,0xffff
712 mfdcr r1,ISRAM1_DPC
713 and r1,r1,r2 /* Disable parity check */
714 mtdcr ISRAM1_DPC,r1
715 mfdcr r1,ISRAM1_PMEG
716 and r1,r1,r2 /* Disable pwr mgmt */
717 mtdcr ISRAM1_PMEG,r1
718
719 lis r1,0x0004 /* BAS = 4_0004_0000 */
720 ori r1,r1,ISRAM1_SIZE /* ocm size */
721 mtdcr ISRAM1_SB0CR,r1
722 #endif
723 #elif defined(CONFIG_460SX)
724 lis r1,0x0000 /* BAS = 0000_0000 */
725 ori r1,r1,0x0B84 /* first 128k */
726 mtdcr ISRAM0_SB0CR,r1
727 lis r1,0x0001
728 ori r1,r1,0x0B84 /* second 128k */
729 mtdcr ISRAM0_SB1CR,r1
730 lis r1, 0x0002
731 ori r1,r1, 0x0B84 /* third 128k */
732 mtdcr ISRAM0_SB2CR,r1
733 lis r1, 0x0003
734 ori r1,r1, 0x0B84 /* fourth 128k */
735 mtdcr ISRAM0_SB3CR,r1
736 #elif defined(CONFIG_440GP)
737 ori r1,r1,0x0380 /* 8k rw */
738 mtdcr ISRAM0_SB0CR,r1
739 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
740 #endif
741 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
742
743 /*----------------------------------------------------------------*/
744 /* Setup the stack in internal SRAM */
745 /*----------------------------------------------------------------*/
746 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
747 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
748 li r0,0
749 stwu r0,-4(r1)
750 stwu r0,-4(r1) /* Terminate call chain */
751
752 stwu r1,-8(r1) /* Save back chain and move SP */
753 lis r0,RESET_VECTOR@h /* Address of reset vector */
754 ori r0,r0, RESET_VECTOR@l
755 stwu r1,-8(r1) /* Save back chain and move SP */
756 stw r0,+12(r1) /* Save return addr (underflow vect) */
757
758 #ifndef CONFIG_SPL_BUILD
759 GET_GOT
760 #endif
761
762 bl cpu_init_f /* run low-level CPU init code (from Flash) */
763 #ifdef CONFIG_SYS_GENERIC_BOARD
764 mr r3, r1
765 bl board_init_f_alloc_reserve
766 mr r1, r3
767 bl board_init_f_init_reserve
768 li r0,0
769 stwu r0, -4(r1)
770 stwu r0, -4(r1)
771 #endif
772 li r3, 0
773 bl board_init_f
774 /* NOTREACHED - board_init_f() does not return */
775
776 #endif /* CONFIG_440 */
777
778 /*****************************************************************************/
779 #if defined(CONFIG_405GP) || \
780 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
781 defined(CONFIG_405EX) || defined(CONFIG_405)
782 /*----------------------------------------------------------------------- */
783 /* Clear and set up some registers. */
784 /*----------------------------------------------------------------------- */
785 addi r4,r0,0x0000
786 #if !defined(CONFIG_405EX)
787 mtspr SPRN_SGR,r4
788 #else
789 /*
790 * On 405EX, completely clearing the SGR leads to PPC hangup
791 * upon PCIe configuration access. The PCIe memory regions
792 * need to be guarded!
793 */
794 lis r3,0x0000
795 ori r3,r3,0x7FFC
796 mtspr SPRN_SGR,r3
797 #endif
798 mtspr SPRN_DCWR,r4
799 mtesr r4 /* clear Exception Syndrome Reg */
800 mttcr r4 /* clear Timer Control Reg */
801 mtxer r4 /* clear Fixed-Point Exception Reg */
802 mtevpr r4 /* clear Exception Vector Prefix Reg */
803 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
804 /* dbsr is cleared by setting bits to 1) */
805 mtdbsr r4 /* clear/reset the dbsr */
806
807 /* Invalidate the i- and d-caches. */
808 bl invalidate_icache
809 bl invalidate_dcache
810
811 /* Set-up icache cacheability. */
812 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
813 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
814 mticcr r4
815 isync
816
817 /* Set-up dcache cacheability. */
818 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
819 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
820 mtdccr r4
821
822 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
823 && !defined (CONFIG_XILINX_405)
824 /*----------------------------------------------------------------------- */
825 /* Tune the speed and size for flash CS0 */
826 /*----------------------------------------------------------------------- */
827 bl ext_bus_cntlr_init
828 #endif
829
830 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
831 /*
832 * For boards that don't have OCM and can't use the data cache
833 * for their primordial stack, setup stack here directly after the
834 * SDRAM is initialized in ext_bus_cntlr_init.
835 */
836 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
837 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
838
839 li r0, 0 /* Make room for stack frame header and */
840 stwu r0, -4(r1) /* clear final stack frame so that */
841 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
842 /*
843 * Set up a dummy frame to store reset vector as return address.
844 * this causes stack underflow to reset board.
845 */
846 stwu r1, -8(r1) /* Save back chain and move SP */
847 lis r0, RESET_VECTOR@h /* Address of reset vector */
848 ori r0, r0, RESET_VECTOR@l
849 stwu r1, -8(r1) /* Save back chain and move SP */
850 stw r0, +12(r1) /* Save return addr (underflow vect) */
851 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
852
853 #if defined(CONFIG_405EP)
854 /*----------------------------------------------------------------------- */
855 /* DMA Status, clear to come up clean */
856 /*----------------------------------------------------------------------- */
857 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
858 ori r3,r3, 0xFFFF
859 mtdcr DMASR, r3
860
861 bl ppc405ep_init /* do ppc405ep specific init */
862 #endif /* CONFIG_405EP */
863
864 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
865 #if defined(CONFIG_405EZ)
866 /********************************************************************
867 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
868 *******************************************************************/
869 /*
870 * We can map the OCM on the PLB3, so map it at
871 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
872 */
873 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
874 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
875 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
876 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
877 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
878 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
879 isync
880
881 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
882 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
883 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
884 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
885 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
886 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
887 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
888 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
889 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
890 mtdcr OCM0_DISDPC,r3
891
892 isync
893 #else /* CONFIG_405EZ */
894 /********************************************************************
895 * Setup OCM - On Chip Memory
896 *******************************************************************/
897 /* Setup OCM */
898 lis r0, 0x7FFF
899 ori r0, r0, 0xFFFF
900 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
901 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
902 and r3, r3, r0 /* disable data-side IRAM */
903 and r4, r4, r0 /* disable data-side IRAM */
904 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
905 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
906 isync
907
908 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
909 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
910 mtdcr OCM0_DSARC, r3
911 addis r4, 0, 0xC000 /* OCM data area enabled */
912 mtdcr OCM0_DSCNTL, r4
913 isync
914 #endif /* CONFIG_405EZ */
915 #endif
916
917 /*----------------------------------------------------------------------- */
918 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
919 /*----------------------------------------------------------------------- */
920 #ifdef CONFIG_SYS_INIT_DCACHE_CS
921 li r4, PBxAP
922 mtdcr EBC0_CFGADDR, r4
923 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
924 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
925 mtdcr EBC0_CFGDATA, r4
926
927 addi r4, 0, PBxCR
928 mtdcr EBC0_CFGADDR, r4
929 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
930 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
931 mtdcr EBC0_CFGDATA, r4
932
933 /*
934 * Enable the data cache for the 128MB storage access control region
935 * at CONFIG_SYS_INIT_RAM_ADDR.
936 */
937 mfdccr r4
938 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
939 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
940 mtdccr r4
941
942 /*
943 * Preallocate data cache lines to be used to avoid a subsequent
944 * cache miss and an ensuing machine check exception when exceptions
945 * are enabled.
946 */
947 li r0, 0
948
949 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
950 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
951
952 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
953 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
954
955 /*
956 * Convert the size, in bytes, to the number of cache lines/blocks
957 * to preallocate.
958 */
959 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
960 srwi r5, r4, L1_CACHE_SHIFT
961 beq ..load_counter
962 addi r5, r5, 0x0001
963 ..load_counter:
964 mtctr r5
965
966 /* Preallocate the computed number of cache blocks. */
967 ..alloc_dcache_block:
968 dcba r0, r3
969 addi r3, r3, L1_CACHE_BYTES
970 bdnz ..alloc_dcache_block
971 sync
972
973 /*
974 * Load the initial stack pointer and data area and convert the size,
975 * in bytes, to the number of words to initialize to a known value.
976 */
977 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
978 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
979
980 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
981 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
982 mtctr r4
983
984 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
985 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
986
987 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
988 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
989
990 ..stackloop:
991 stwu r4, -4(r2)
992 bdnz ..stackloop
993
994 /*
995 * Make room for stack frame header and clear final stack frame so
996 * that stack backtraces terminate cleanly.
997 */
998 stwu r0, -4(r1)
999 stwu r0, -4(r1)
1000
1001 /*
1002 * Set up a dummy frame to store reset vector as return address.
1003 * this causes stack underflow to reset board.
1004 */
1005 stwu r1, -8(r1) /* Save back chain and move SP */
1006 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1007 ori r0, r0, RESET_VECTOR@l
1008 stwu r1, -8(r1) /* Save back chain and move SP */
1009 stw r0, +12(r1) /* Save return addr (underflow vect) */
1010
1011 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1012 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1013 /*
1014 * Stack in OCM.
1015 */
1016
1017 /* Set up Stack at top of OCM */
1018 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1019 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1020
1021 /* Set up a zeroized stack frame so that backtrace works right */
1022 li r0, 0
1023 stwu r0, -4(r1)
1024 stwu r0, -4(r1)
1025
1026 /*
1027 * Set up a dummy frame to store reset vector as return address.
1028 * this causes stack underflow to reset board.
1029 */
1030 stwu r1, -8(r1) /* Save back chain and move SP */
1031 lis r0, RESET_VECTOR@h /* Address of reset vector */
1032 ori r0, r0, RESET_VECTOR@l
1033 stwu r1, -8(r1) /* Save back chain and move SP */
1034 stw r0, +12(r1) /* Save return addr (underflow vect) */
1035 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1036
1037 GET_GOT /* initialize GOT access */
1038
1039 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1040 #ifdef CONFIG_SYS_GENERIC_BOARD
1041 mr r3, r1
1042 bl board_init_f_alloc_reserve
1043 mr r1, r3
1044 bl board_init_f_init_reserve
1045 stwu r0, -4(r1)
1046 stwu r0, -4(r1)
1047 #endif
1048 li r3, 0
1049 bl board_init_f /* run first part of init code (from Flash) */
1050 /* NOTREACHED - board_init_f() does not return */
1051
1052 #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
1053 /*----------------------------------------------------------------------- */
1054
1055
1056 #if !defined(CONFIG_SPL_BUILD)
1057 /*
1058 * This code finishes saving the registers to the exception frame
1059 * and jumps to the appropriate handler for the exception.
1060 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1061 */
1062 .globl transfer_to_handler
1063 transfer_to_handler:
1064 stw r22,_NIP(r21)
1065 lis r22,MSR_POW@h
1066 andc r23,r23,r22
1067 stw r23,_MSR(r21)
1068 SAVE_GPR(7, r21)
1069 SAVE_4GPRS(8, r21)
1070 SAVE_8GPRS(12, r21)
1071 SAVE_8GPRS(24, r21)
1072 mflr r23
1073 andi. r24,r23,0x3f00 /* get vector offset */
1074 stw r24,TRAP(r21)
1075 li r22,0
1076 stw r22,RESULT(r21)
1077 mtspr SPRG2,r22 /* r1 is now kernel sp */
1078 lwz r24,0(r23) /* virtual address of handler */
1079 lwz r23,4(r23) /* where to go when done */
1080 mtspr SRR0,r24
1081 mtspr SRR1,r20
1082 mtlr r23
1083 SYNC
1084 rfi /* jump to handler, enable MMU */
1085
1086 int_return:
1087 mfmsr r28 /* Disable interrupts */
1088 li r4,0
1089 ori r4,r4,MSR_EE
1090 andc r28,r28,r4
1091 SYNC /* Some chip revs need this... */
1092 mtmsr r28
1093 SYNC
1094 lwz r2,_CTR(r1)
1095 lwz r0,_LINK(r1)
1096 mtctr r2
1097 mtlr r0
1098 lwz r2,_XER(r1)
1099 lwz r0,_CCR(r1)
1100 mtspr XER,r2
1101 mtcrf 0xFF,r0
1102 REST_10GPRS(3, r1)
1103 REST_10GPRS(13, r1)
1104 REST_8GPRS(23, r1)
1105 REST_GPR(31, r1)
1106 lwz r2,_NIP(r1) /* Restore environment */
1107 lwz r0,_MSR(r1)
1108 mtspr SRR0,r2
1109 mtspr SRR1,r0
1110 lwz r0,GPR0(r1)
1111 lwz r2,GPR2(r1)
1112 lwz r1,GPR1(r1)
1113 SYNC
1114 rfi
1115
1116 crit_return:
1117 mfmsr r28 /* Disable interrupts */
1118 li r4,0
1119 ori r4,r4,MSR_EE
1120 andc r28,r28,r4
1121 SYNC /* Some chip revs need this... */
1122 mtmsr r28
1123 SYNC
1124 lwz r2,_CTR(r1)
1125 lwz r0,_LINK(r1)
1126 mtctr r2
1127 mtlr r0
1128 lwz r2,_XER(r1)
1129 lwz r0,_CCR(r1)
1130 mtspr XER,r2
1131 mtcrf 0xFF,r0
1132 REST_10GPRS(3, r1)
1133 REST_10GPRS(13, r1)
1134 REST_8GPRS(23, r1)
1135 REST_GPR(31, r1)
1136 lwz r2,_NIP(r1) /* Restore environment */
1137 lwz r0,_MSR(r1)
1138 mtspr SPRN_CSRR0,r2
1139 mtspr SPRN_CSRR1,r0
1140 lwz r0,GPR0(r1)
1141 lwz r2,GPR2(r1)
1142 lwz r1,GPR1(r1)
1143 SYNC
1144 rfci
1145
1146 #ifdef CONFIG_440
1147 mck_return:
1148 mfmsr r28 /* Disable interrupts */
1149 li r4,0
1150 ori r4,r4,MSR_EE
1151 andc r28,r28,r4
1152 SYNC /* Some chip revs need this... */
1153 mtmsr r28
1154 SYNC
1155 lwz r2,_CTR(r1)
1156 lwz r0,_LINK(r1)
1157 mtctr r2
1158 mtlr r0
1159 lwz r2,_XER(r1)
1160 lwz r0,_CCR(r1)
1161 mtspr XER,r2
1162 mtcrf 0xFF,r0
1163 REST_10GPRS(3, r1)
1164 REST_10GPRS(13, r1)
1165 REST_8GPRS(23, r1)
1166 REST_GPR(31, r1)
1167 lwz r2,_NIP(r1) /* Restore environment */
1168 lwz r0,_MSR(r1)
1169 mtspr SPRN_MCSRR0,r2
1170 mtspr SPRN_MCSRR1,r0
1171 lwz r0,GPR0(r1)
1172 lwz r2,GPR2(r1)
1173 lwz r1,GPR1(r1)
1174 SYNC
1175 rfmci
1176 #endif /* CONFIG_440 */
1177
1178
1179 .globl get_pvr
1180 get_pvr:
1181 mfspr r3, PVR
1182 blr
1183
1184 /*------------------------------------------------------------------------------- */
1185 /* Function: out16 */
1186 /* Description: Output 16 bits */
1187 /*------------------------------------------------------------------------------- */
1188 .globl out16
1189 out16:
1190 sth r4,0x0000(r3)
1191 blr
1192
1193 /*------------------------------------------------------------------------------- */
1194 /* Function: out16r */
1195 /* Description: Byte reverse and output 16 bits */
1196 /*------------------------------------------------------------------------------- */
1197 .globl out16r
1198 out16r:
1199 sthbrx r4,r0,r3
1200 blr
1201
1202 /*------------------------------------------------------------------------------- */
1203 /* Function: out32r */
1204 /* Description: Byte reverse and output 32 bits */
1205 /*------------------------------------------------------------------------------- */
1206 .globl out32r
1207 out32r:
1208 stwbrx r4,r0,r3
1209 blr
1210
1211 /*------------------------------------------------------------------------------- */
1212 /* Function: in16 */
1213 /* Description: Input 16 bits */
1214 /*------------------------------------------------------------------------------- */
1215 .globl in16
1216 in16:
1217 lhz r3,0x0000(r3)
1218 blr
1219
1220 /*------------------------------------------------------------------------------- */
1221 /* Function: in16r */
1222 /* Description: Input 16 bits and byte reverse */
1223 /*------------------------------------------------------------------------------- */
1224 .globl in16r
1225 in16r:
1226 lhbrx r3,r0,r3
1227 blr
1228
1229 /*------------------------------------------------------------------------------- */
1230 /* Function: in32r */
1231 /* Description: Input 32 bits and byte reverse */
1232 /*------------------------------------------------------------------------------- */
1233 .globl in32r
1234 in32r:
1235 lwbrx r3,r0,r3
1236 blr
1237
1238 #if !defined(CONFIG_SPL_BUILD)
1239 /*
1240 * void relocate_code (addr_sp, gd, addr_moni)
1241 *
1242 * This "function" does not return, instead it continues in RAM
1243 * after relocating the monitor code.
1244 *
1245 * r3 = Relocated stack pointer
1246 * r4 = Relocated global data pointer
1247 * r5 = Relocated text pointer
1248 */
1249 .globl relocate_code
1250 relocate_code:
1251 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1252 /*
1253 * We need to flush the initial global data (gd_t) and bd_info
1254 * before the dcache will be invalidated.
1255 */
1256
1257 /* Save registers */
1258 mr r9, r3
1259 mr r10, r4
1260 mr r11, r5
1261
1262 /*
1263 * Flush complete dcache, this is faster than flushing the
1264 * ranges for global_data and bd_info instead.
1265 */
1266 bl flush_dcache
1267
1268 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1269 /*
1270 * Undo the earlier data cache set-up for the primordial stack and
1271 * data area. First, invalidate the data cache and then disable data
1272 * cacheability for that area. Finally, restore the EBC values, if
1273 * any.
1274 */
1275
1276 /* Invalidate the primordial stack and data area in cache */
1277 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1278 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1279
1280 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1281 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1282 add r4, r4, r3
1283
1284 bl invalidate_dcache_range
1285
1286 /* Disable cacheability for the region */
1287 mfdccr r3
1288 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1289 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1290 and r3, r3, r4
1291 mtdccr r3
1292
1293 /* Restore the EBC parameters */
1294 li r3, PBxAP
1295 mtdcr EBC0_CFGADDR, r3
1296 lis r3, PBxAP_VAL@h
1297 ori r3, r3, PBxAP_VAL@l
1298 mtdcr EBC0_CFGDATA, r3
1299
1300 li r3, PBxCR
1301 mtdcr EBC0_CFGADDR, r3
1302 lis r3, PBxCR_VAL@h
1303 ori r3, r3, PBxCR_VAL@l
1304 mtdcr EBC0_CFGDATA, r3
1305 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1306
1307 /* Restore registers */
1308 mr r3, r9
1309 mr r4, r10
1310 mr r5, r11
1311 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1312
1313 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1314 /*
1315 * Unlock the previously locked d-cache
1316 */
1317 msync
1318 isync
1319 /* set TFLOOR/NFLOOR to 0 again */
1320 lis r6,0x0001
1321 ori r6,r6,0xf800
1322 mtspr SPRN_DVLIM,r6
1323 lis r6,0x0000
1324 ori r6,r6,0x0000
1325 mtspr SPRN_DNV0,r6
1326 mtspr SPRN_DNV1,r6
1327 mtspr SPRN_DNV2,r6
1328 mtspr SPRN_DNV3,r6
1329 mtspr SPRN_DTV0,r6
1330 mtspr SPRN_DTV1,r6
1331 mtspr SPRN_DTV2,r6
1332 mtspr SPRN_DTV3,r6
1333 msync
1334 isync
1335
1336 /* Invalidate data cache, now no longer our stack */
1337 dccci 0,0
1338 sync
1339 isync
1340 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1341
1342 /*
1343 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1344 * to speed up the boot process. Now this cache needs to be disabled.
1345 */
1346 #if defined(CONFIG_440)
1347 /* Clear all potential pending exceptions */
1348 mfspr r1,SPRN_MCSR
1349 mtspr SPRN_MCSR,r1
1350 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1351 tlbre r0,r1,0x0002 /* Read contents */
1352 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1353 tlbwe r0,r1,0x0002 /* Save it out */
1354 sync
1355 isync
1356 #endif /* defined(CONFIG_440) */
1357 mr r1, r3 /* Set new stack pointer */
1358 mr r9, r4 /* Save copy of Init Data pointer */
1359 mr r10, r5 /* Save copy of Destination Address */
1360
1361 GET_GOT
1362 mr r3, r5 /* Destination Address */
1363 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1364 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1365 lwz r5, GOT(__init_end)
1366 sub r5, r5, r4
1367 li r6, L1_CACHE_BYTES /* Cache Line Size */
1368
1369 /*
1370 * Fix GOT pointer:
1371 *
1372 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1373 *
1374 * Offset:
1375 */
1376 sub r15, r10, r4
1377
1378 /* First our own GOT */
1379 add r12, r12, r15
1380 /* then the one used by the C code */
1381 add r30, r30, r15
1382
1383 /*
1384 * Now relocate code
1385 */
1386
1387 cmplw cr1,r3,r4
1388 addi r0,r5,3
1389 srwi. r0,r0,2
1390 beq cr1,4f /* In place copy is not necessary */
1391 beq 7f /* Protect against 0 count */
1392 mtctr r0
1393 bge cr1,2f
1394
1395 la r8,-4(r4)
1396 la r7,-4(r3)
1397 1: lwzu r0,4(r8)
1398 stwu r0,4(r7)
1399 bdnz 1b
1400 b 4f
1401
1402 2: slwi r0,r0,2
1403 add r8,r4,r0
1404 add r7,r3,r0
1405 3: lwzu r0,-4(r8)
1406 stwu r0,-4(r7)
1407 bdnz 3b
1408
1409 /*
1410 * Now flush the cache: note that we must start from a cache aligned
1411 * address. Otherwise we might miss one cache line.
1412 */
1413 4: cmpwi r6,0
1414 add r5,r3,r5
1415 beq 7f /* Always flush prefetch queue in any case */
1416 subi r0,r6,1
1417 andc r3,r3,r0
1418 mr r4,r3
1419 5: dcbst 0,r4
1420 add r4,r4,r6
1421 cmplw r4,r5
1422 blt 5b
1423 sync /* Wait for all dcbst to complete on bus */
1424 mr r4,r3
1425 6: icbi 0,r4
1426 add r4,r4,r6
1427 cmplw r4,r5
1428 blt 6b
1429 7: sync /* Wait for all icbi to complete on bus */
1430 isync
1431
1432 /*
1433 * We are done. Do not return, instead branch to second part of board
1434 * initialization, now running from RAM.
1435 */
1436
1437 addi r0, r10, in_ram - _start + _START_OFFSET
1438 mtlr r0
1439 blr /* NEVER RETURNS! */
1440
1441 in_ram:
1442
1443 /*
1444 * Relocation Function, r12 point to got2+0x8000
1445 *
1446 * Adjust got2 pointers, no need to check for 0, this code
1447 * already puts a few entries in the table.
1448 */
1449 li r0,__got2_entries@sectoff@l
1450 la r3,GOT(_GOT2_TABLE_)
1451 lwz r11,GOT(_GOT2_TABLE_)
1452 mtctr r0
1453 sub r11,r3,r11
1454 addi r3,r3,-4
1455 1: lwzu r0,4(r3)
1456 cmpwi r0,0
1457 beq- 2f
1458 add r0,r0,r11
1459 stw r0,0(r3)
1460 2: bdnz 1b
1461
1462 /*
1463 * Now adjust the fixups and the pointers to the fixups
1464 * in case we need to move ourselves again.
1465 */
1466 li r0,__fixup_entries@sectoff@l
1467 lwz r3,GOT(_FIXUP_TABLE_)
1468 cmpwi r0,0
1469 mtctr r0
1470 addi r3,r3,-4
1471 beq 4f
1472 3: lwzu r4,4(r3)
1473 lwzux r0,r4,r11
1474 cmpwi r0,0
1475 add r0,r0,r11
1476 stw r4,0(r3)
1477 beq- 5f
1478 stw r0,0(r4)
1479 5: bdnz 3b
1480 4:
1481 clear_bss:
1482 /*
1483 * Now clear BSS segment
1484 */
1485 lwz r3,GOT(__bss_start)
1486 lwz r4,GOT(__bss_end)
1487
1488 cmplw 0, r3, r4
1489 beq 7f
1490
1491 li r0, 0
1492
1493 andi. r5, r4, 3
1494 beq 6f
1495 sub r4, r4, r5
1496 mtctr r5
1497 mr r5, r4
1498 5: stb r0, 0(r5)
1499 addi r5, r5, 1
1500 bdnz 5b
1501 6:
1502 stw r0, 0(r3)
1503 addi r3, r3, 4
1504 cmplw 0, r3, r4
1505 bne 6b
1506
1507 7:
1508 mr r3, r9 /* Init Data pointer */
1509 mr r4, r10 /* Destination Address */
1510 bl board_init_r
1511
1512 /*
1513 * Copy exception vector code to low memory
1514 *
1515 * r3: dest_addr
1516 * r7: source address, r8: end address, r9: target address
1517 */
1518 .globl trap_init
1519 trap_init:
1520 mflr r4 /* save link register */
1521 GET_GOT
1522 lwz r7, GOT(_start_of_vectors)
1523 lwz r8, GOT(_end_of_vectors)
1524
1525 li r9, 0x100 /* reset vector always at 0x100 */
1526
1527 cmplw 0, r7, r8
1528 bgelr /* return if r7>=r8 - just in case */
1529 1:
1530 lwz r0, 0(r7)
1531 stw r0, 0(r9)
1532 addi r7, r7, 4
1533 addi r9, r9, 4
1534 cmplw 0, r7, r8
1535 bne 1b
1536
1537 /*
1538 * relocate `hdlr' and `int_return' entries
1539 */
1540 li r7, .L_MachineCheck - _start + _START_OFFSET
1541 li r8, Alignment - _start + _START_OFFSET
1542 2:
1543 bl trap_reloc
1544 addi r7, r7, 0x100 /* next exception vector */
1545 cmplw 0, r7, r8
1546 blt 2b
1547
1548 li r7, .L_Alignment - _start + _START_OFFSET
1549 bl trap_reloc
1550
1551 li r7, .L_ProgramCheck - _start + _START_OFFSET
1552 bl trap_reloc
1553
1554 #ifdef CONFIG_440
1555 li r7, .L_FPUnavailable - _start + _START_OFFSET
1556 bl trap_reloc
1557
1558 li r7, .L_Decrementer - _start + _START_OFFSET
1559 bl trap_reloc
1560
1561 li r7, .L_APU - _start + _START_OFFSET
1562 bl trap_reloc
1563
1564 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1565 bl trap_reloc
1566
1567 li r7, .L_DataTLBError - _start + _START_OFFSET
1568 bl trap_reloc
1569 #else /* CONFIG_440 */
1570 li r7, .L_PIT - _start + _START_OFFSET
1571 bl trap_reloc
1572
1573 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1574 bl trap_reloc
1575
1576 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1577 bl trap_reloc
1578 #endif /* CONFIG_440 */
1579
1580 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1581 bl trap_reloc
1582
1583 #if !defined(CONFIG_440)
1584 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1585 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1586 mtmsr r7 /* change MSR */
1587 #else
1588 bl __440_msr_set
1589 b __440_msr_continue
1590
1591 __440_msr_set:
1592 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1593 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1594 mtspr SPRN_SRR1,r7
1595 mflr r7
1596 mtspr SPRN_SRR0,r7
1597 rfi
1598 __440_msr_continue:
1599 #endif
1600
1601 mtlr r4 /* restore link register */
1602 blr
1603 #endif /* CONFIG_SPL_BUILD */
1604
1605 #if defined(CONFIG_440)
1606 /*----------------------------------------------------------------------------+
1607 | dcbz_area.
1608 +----------------------------------------------------------------------------*/
1609 function_prolog(dcbz_area)
1610 rlwinm. r5,r4,0,27,31
1611 rlwinm r5,r4,27,5,31
1612 beq ..d_ra2
1613 addi r5,r5,0x0001
1614 ..d_ra2:mtctr r5
1615 ..d_ag2:dcbz r0,r3
1616 addi r3,r3,32
1617 bdnz ..d_ag2
1618 sync
1619 blr
1620 function_epilog(dcbz_area)
1621 #endif /* CONFIG_440 */
1622 #endif /* CONFIG_SPL_BUILD */
1623
1624 /*------------------------------------------------------------------------------- */
1625 /* Function: in8 */
1626 /* Description: Input 8 bits */
1627 /*------------------------------------------------------------------------------- */
1628 .globl in8
1629 in8:
1630 lbz r3,0x0000(r3)
1631 blr
1632
1633 /*------------------------------------------------------------------------------- */
1634 /* Function: out8 */
1635 /* Description: Output 8 bits */
1636 /*------------------------------------------------------------------------------- */
1637 .globl out8
1638 out8:
1639 stb r4,0x0000(r3)
1640 blr
1641
1642 /*------------------------------------------------------------------------------- */
1643 /* Function: out32 */
1644 /* Description: Output 32 bits */
1645 /*------------------------------------------------------------------------------- */
1646 .globl out32
1647 out32:
1648 stw r4,0x0000(r3)
1649 blr
1650
1651 /*------------------------------------------------------------------------------- */
1652 /* Function: in32 */
1653 /* Description: Input 32 bits */
1654 /*------------------------------------------------------------------------------- */
1655 .globl in32
1656 in32:
1657 lwz 3,0x0000(3)
1658 blr
1659
1660 /**************************************************************************/
1661 /* PPC405EP specific stuff */
1662 /**************************************************************************/
1663 #ifdef CONFIG_405EP
1664 ppc405ep_init:
1665
1666 #ifdef CONFIG_BUBINGA
1667 /*
1668 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1669 * function) to support FPGA and NVRAM accesses below.
1670 */
1671
1672 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1673 ori r3,r3,GPIO0_OSRH@l
1674 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1675 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1676 stw r4,0(r3)
1677 lis r3,GPIO0_OSRL@h
1678 ori r3,r3,GPIO0_OSRL@l
1679 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1680 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1681 stw r4,0(r3)
1682
1683 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1684 ori r3,r3,GPIO0_ISR1H@l
1685 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1686 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1687 stw r4,0(r3)
1688 lis r3,GPIO0_ISR1L@h
1689 ori r3,r3,GPIO0_ISR1L@l
1690 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1691 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1692 stw r4,0(r3)
1693
1694 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1695 ori r3,r3,GPIO0_TSRH@l
1696 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1697 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1698 stw r4,0(r3)
1699 lis r3,GPIO0_TSRL@h
1700 ori r3,r3,GPIO0_TSRL@l
1701 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1702 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1703 stw r4,0(r3)
1704
1705 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1706 ori r3,r3,GPIO0_TCR@l
1707 lis r4,CONFIG_SYS_GPIO0_TCR@h
1708 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1709 stw r4,0(r3)
1710
1711 li r3,PB1AP /* program EBC bank 1 for RTC access */
1712 mtdcr EBC0_CFGADDR,r3
1713 lis r3,CONFIG_SYS_EBC_PB1AP@h
1714 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1715 mtdcr EBC0_CFGDATA,r3
1716 li r3,PB1CR
1717 mtdcr EBC0_CFGADDR,r3
1718 lis r3,CONFIG_SYS_EBC_PB1CR@h
1719 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1720 mtdcr EBC0_CFGDATA,r3
1721
1722 li r3,PB1AP /* program EBC bank 1 for RTC access */
1723 mtdcr EBC0_CFGADDR,r3
1724 lis r3,CONFIG_SYS_EBC_PB1AP@h
1725 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1726 mtdcr EBC0_CFGDATA,r3
1727 li r3,PB1CR
1728 mtdcr EBC0_CFGADDR,r3
1729 lis r3,CONFIG_SYS_EBC_PB1CR@h
1730 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1731 mtdcr EBC0_CFGDATA,r3
1732
1733 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1734 mtdcr EBC0_CFGADDR,r3
1735 lis r3,CONFIG_SYS_EBC_PB4AP@h
1736 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1737 mtdcr EBC0_CFGDATA,r3
1738 li r3,PB4CR
1739 mtdcr EBC0_CFGADDR,r3
1740 lis r3,CONFIG_SYS_EBC_PB4CR@h
1741 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1742 mtdcr EBC0_CFGDATA,r3
1743 #endif
1744
1745 /*
1746 !-----------------------------------------------------------------------
1747 ! Check to see if chip is in bypass mode.
1748 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1749 ! CPU reset Otherwise, skip this step and keep going.
1750 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1751 ! will not be fast enough for the SDRAM (min 66MHz)
1752 !-----------------------------------------------------------------------
1753 */
1754 mfdcr r5, CPC0_PLLMR1
1755 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1756 cmpi cr0,0,r4,0x1
1757
1758 beq pll_done /* if SSCS =b'1' then PLL has */
1759 /* already been set */
1760 /* and CPU has been reset */
1761 /* so skip to next section */
1762
1763 #ifdef CONFIG_BUBINGA
1764 /*
1765 !-----------------------------------------------------------------------
1766 ! Read NVRAM to get value to write in PLLMR.
1767 ! If value has not been correctly saved, write default value
1768 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1769 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1770 !
1771 ! WARNING: This code assumes the first three words in the nvram_t
1772 ! structure in openbios.h. Changing the beginning of
1773 ! the structure will break this code.
1774 !
1775 !-----------------------------------------------------------------------
1776 */
1777 addis r3,0,NVRAM_BASE@h
1778 addi r3,r3,NVRAM_BASE@l
1779
1780 lwz r4, 0(r3)
1781 addis r5,0,NVRVFY1@h
1782 addi r5,r5,NVRVFY1@l
1783 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1784 bne ..no_pllset
1785 addi r3,r3,4
1786 lwz r4, 0(r3)
1787 addis r5,0,NVRVFY2@h
1788 addi r5,r5,NVRVFY2@l
1789 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1790 bne ..no_pllset
1791 addi r3,r3,8 /* Skip over conf_size */
1792 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1793 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1794 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1795 cmpi cr0,0,r5,1 /* See if PLL is locked */
1796 beq pll_write
1797 ..no_pllset:
1798 #endif /* CONFIG_BUBINGA */
1799
1800 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1801 ori r3,r3,PLLMR0_DEFAULT@l /* */
1802 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1803 ori r4,r4,PLLMR1_DEFAULT@l /* */
1804
1805 1:
1806 b pll_write /* Write the CPC0_PLLMR with new value */
1807
1808 pll_done:
1809 /*
1810 !-----------------------------------------------------------------------
1811 ! Clear Soft Reset Register
1812 ! This is needed to enable PCI if not booting from serial EPROM
1813 !-----------------------------------------------------------------------
1814 */
1815 addi r3, 0, 0x0
1816 mtdcr CPC0_SRR, r3
1817
1818 addis r3,0,0x0010
1819 mtctr r3
1820 pci_wait:
1821 bdnz pci_wait
1822
1823 blr /* return to main code */
1824
1825 /*
1826 !-----------------------------------------------------------------------------
1827 ! Function: pll_write
1828 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1829 ! That is:
1830 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1831 ! 2. PLL is reset
1832 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1833 ! 4. PLL Reset is cleared
1834 ! 5. Wait 100us for PLL to lock
1835 ! 6. A core reset is performed
1836 ! Input: r3 = Value to write to CPC0_PLLMR0
1837 ! Input: r4 = Value to write to CPC0_PLLMR1
1838 ! Output r3 = none
1839 !-----------------------------------------------------------------------------
1840 */
1841 .globl pll_write
1842 pll_write:
1843 mfdcr r5, CPC0_UCR
1844 andis. r5,r5,0xFFFF
1845 ori r5,r5,0x0101 /* Stop the UART clocks */
1846 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1847
1848 mfdcr r5, CPC0_PLLMR1
1849 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1850 mtdcr CPC0_PLLMR1,r5
1851 oris r5,r5,0x4000 /* Set PLL Reset */
1852 mtdcr CPC0_PLLMR1,r5
1853
1854 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1855 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1856 oris r5,r5,0x4000 /* Set PLL Reset */
1857 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1858 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1859 mtdcr CPC0_PLLMR1,r5
1860
1861 /*
1862 ! Wait min of 100us for PLL to lock.
1863 ! See CMOS 27E databook for more info.
1864 ! At 200MHz, that means waiting 20,000 instructions
1865 */
1866 addi r3,0,20000 /* 2000 = 0x4e20 */
1867 mtctr r3
1868 pll_wait:
1869 bdnz pll_wait
1870
1871 oris r5,r5,0x8000 /* Enable PLL */
1872 mtdcr CPC0_PLLMR1,r5 /* Engage */
1873
1874 /*
1875 * Reset CPU to guarantee timings are OK
1876 * Not sure if this is needed...
1877 */
1878 addis r3,0,0x1000
1879 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
1880 /* execution will continue from the poweron */
1881 /* vector of 0xfffffffc */
1882 #endif /* CONFIG_405EP */
1883
1884 #if defined(CONFIG_440)
1885 /*----------------------------------------------------------------------------+
1886 | mttlb3.
1887 +----------------------------------------------------------------------------*/
1888 function_prolog(mttlb3)
1889 TLBWE(4,3,2)
1890 blr
1891 function_epilog(mttlb3)
1892
1893 /*----------------------------------------------------------------------------+
1894 | mftlb3.
1895 +----------------------------------------------------------------------------*/
1896 function_prolog(mftlb3)
1897 TLBRE(3,3,2)
1898 blr
1899 function_epilog(mftlb3)
1900
1901 /*----------------------------------------------------------------------------+
1902 | mttlb2.
1903 +----------------------------------------------------------------------------*/
1904 function_prolog(mttlb2)
1905 TLBWE(4,3,1)
1906 blr
1907 function_epilog(mttlb2)
1908
1909 /*----------------------------------------------------------------------------+
1910 | mftlb2.
1911 +----------------------------------------------------------------------------*/
1912 function_prolog(mftlb2)
1913 TLBRE(3,3,1)
1914 blr
1915 function_epilog(mftlb2)
1916
1917 /*----------------------------------------------------------------------------+
1918 | mttlb1.
1919 +----------------------------------------------------------------------------*/
1920 function_prolog(mttlb1)
1921 TLBWE(4,3,0)
1922 blr
1923 function_epilog(mttlb1)
1924
1925 /*----------------------------------------------------------------------------+
1926 | mftlb1.
1927 +----------------------------------------------------------------------------*/
1928 function_prolog(mftlb1)
1929 TLBRE(3,3,0)
1930 blr
1931 function_epilog(mftlb1)
1932 #endif /* CONFIG_440 */
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