3 * MPC8xx Internal Memory Map
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
6 * The I/O on the MPC860 is comprised of blocks of special registers
7 * and the dual port ram for the Communication Processor Module.
8 * Within this space are functional units such as the SIU, memory
9 * controller, system timers, and other control functions. It is
10 * a combination that I found difficult to separate into logical
11 * functional files.....but anyone else is welcome to try. -- Dan
16 /* System configuration registers.
18 typedef struct sys_conf
{
34 /* PCMCIA configuration registers.
36 typedef struct pcmcia_conf
{
64 /* Memory controller registers.
66 typedef struct mem_ctlr
{
95 /* System Integration Timers.
97 typedef struct sys_int_timers
{
116 #define TBSCR_TBIRQ_MASK ((ushort)0xff00)
117 #define TBSCR_REFA ((ushort)0x0080)
118 #define TBSCR_REFB ((ushort)0x0040)
119 #define TBSCR_REFAE ((ushort)0x0008)
120 #define TBSCR_REFBE ((ushort)0x0004)
121 #define TBSCR_TBF ((ushort)0x0002)
122 #define TBSCR_TBE ((ushort)0x0001)
124 #define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
125 #define RTCSC_SEC ((ushort)0x0080)
126 #define RTCSC_ALR ((ushort)0x0040)
127 #define RTCSC_38K ((ushort)0x0010)
128 #define RTCSC_SIE ((ushort)0x0008)
129 #define RTCSC_ALE ((ushort)0x0004)
130 #define RTCSC_RTF ((ushort)0x0002)
131 #define RTCSC_RTE ((ushort)0x0001)
133 #define PISCR_PIRQ_MASK ((ushort)0xff00)
134 #define PISCR_PS ((ushort)0x0080)
135 #define PISCR_PIE ((ushort)0x0004)
136 #define PISCR_PTF ((ushort)0x0002)
137 #define PISCR_PTE ((ushort)0x0001)
141 typedef struct clk_and_reset
{
145 char res
[0x74]; /* Reserved area */
148 /* System Integration Timers keys.
150 typedef struct sitk
{
166 /* Clocks and reset keys.
168 typedef struct cark
{
175 /* The key to unlock registers maintained by keep-alive power.
177 #define KAPWR_KEY ((unsigned int)0x55ccaa33)
179 /* Video interface. MPC823 Only.
181 typedef struct vid823
{
199 /* LCD interface. 823 Only.
229 /* DMA control/status registers.
231 typedef struct sdma_csr
{
248 /* Communication Processor Module Interrupt Controller.
250 typedef struct cpm_ic
{
259 /* Input/Output Port control/status registers.
261 typedef struct io_port
{
281 /* Communication Processor Module Timers
283 typedef struct cpm_timers
{
309 /* Finally, the Communication Processor stuff.....
311 typedef struct scc
{ /* Serial communication channels */
326 typedef struct smc
{ /* Serial management channels */
336 /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
337 * it fits within the address space.
341 uint fec_addr_low
; /* lower 32 bits of station address */
342 ushort fec_addr_high
; /* upper 16 bits of station address */
343 ushort res1
; /* reserved */
344 uint fec_hash_table_high
; /* upper 32-bits of hash table */
345 uint fec_hash_table_low
; /* lower 32-bits of hash table */
346 uint fec_r_des_start
; /* beginning of Rx descriptor ring */
347 uint fec_x_des_start
; /* beginning of Tx descriptor ring */
348 uint fec_r_buff_size
; /* Rx buffer size */
349 uint res2
[9]; /* reserved */
350 uint fec_ecntrl
; /* ethernet control register */
351 uint fec_ievent
; /* interrupt event register */
352 uint fec_imask
; /* interrupt mask register */
353 uint fec_ivec
; /* interrupt level and vector status */
354 uint fec_r_des_active
; /* Rx ring updated flag */
355 uint fec_x_des_active
; /* Tx ring updated flag */
356 uint res3
[10]; /* reserved */
357 uint fec_mii_data
; /* MII data register */
358 uint fec_mii_speed
; /* MII speed control register */
359 uint res4
[17]; /* reserved */
360 uint fec_r_bound
; /* end of RAM (read-only) */
361 uint fec_r_fstart
; /* Rx FIFO start address */
362 uint res5
[6]; /* reserved */
363 uint fec_x_fstart
; /* Tx FIFO start address */
364 uint res6
[17]; /* reserved */
365 uint fec_fun_code
; /* fec SDMA function code */
366 uint res7
[3]; /* reserved */
367 uint fec_r_cntrl
; /* Rx control register */
368 uint fec_r_hash
; /* Rx hash register */
369 uint res8
[14]; /* reserved */
370 uint fec_x_cntrl
; /* Tx control register */
371 uint res9
[0x1e]; /* reserved */
374 /* The FEC and LCD color map share the same address space....
375 * I guess we will never see an 823T :-).
379 u_char fl_un_cmap
[0x200];
382 typedef struct comm_proc
{
383 /* General control and status registers.
401 /* Baud rate generators.
408 /* Serial Communication Channels.
412 /* Serial Management Channels.
416 /* Serial Peripheral Interface.
427 /* Parallel Interface Port.
439 /* Port E - MPC87x/88x only.
447 /* Communications Processor Timing Register -
448 Contains RMII Timing for the FECs on MPC87x/88x only.
452 /* Serial Interface and Time Slot Assignment.
464 /* 256 bytes of MPC823 video controller RAM array.
466 u_char cp_vcram
[0x100];
467 u_char cp_siram
[0x200];
469 /* The fast ethernet controller is not really part of the CPM,
470 * but it resides in the address space.
471 * The LCD color map is also here.
474 #define cp_fec fl_un.fl_un_fec
475 #define lcd_cmap fl_un.fl_un_cmap
478 /* The MPC885 family has a second FEC here */
480 #define cp_fec1 cp_fec /* consistency macro */
482 /* Dual Ported RAM follows.
483 * There are many different formats for this memory area
484 * depending upon the devices used and options chosen.
485 * Some processors don't have all of it populated.
487 u_char cp_dpmem
[0x1C00]; /* BD / Data / ucode */
488 u_char cp_dparam
[0x400]; /* Parameter RAM */
491 /* Internal memory map.
493 typedef struct immap
{
494 sysconf8xx_t im_siu_conf
; /* SIU Configuration */
495 pcmconf8xx_t im_pcmcia
; /* PCMCIA Configuration */
496 memctl8xx_t im_memctl
; /* Memory Controller */
497 sit8xx_t im_sit
; /* System integration timers */
498 car8xx_t im_clkrst
; /* Clocks and reset */
499 sitk8xx_t im_sitk
; /* Sys int timer keys */
500 cark8xx_t im_clkrstk
; /* Clocks and reset keys */
501 vid823_t im_vid
; /* Video (823 only) */
502 lcd823_t im_lcd
; /* LCD (823 only) */
503 i2c8xx_t im_i2c
; /* I2C control/status */
504 sdma8xx_t im_sdma
; /* SDMA control/status */
505 cpic8xx_t im_cpic
; /* CPM Interrupt Controller */
506 iop8xx_t im_ioport
; /* IO Port control/status */
507 cpmtimer8xx_t im_cpmtimer
; /* CPM timers */
508 cpm8xx_t im_cpm
; /* Communication processor */
511 #endif /* __IMMAP_8XX__ */