arch/powerpc/include/asm/book3s/64/mmu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
   3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
   4
   5 #ifndef __ASSEMBLY__
   6 /*
   7  * Page size definition
   8  *
   9  *    shift : is the "PAGE_SHIFT" value for that page size
  10  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
  11  *            directly to a slbmte "vsid" value
  12  *    penc  : is the HPTE encoding mask for the "LP" field:
  13  *
  14  */
  15 struct mmu_psize_def {
  16         unsigned int    shift;  /* number of bits */
  17         int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
  18         unsigned int    tlbiel; /* tlbiel supported for that page size */
  19         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
  20         union {
  21                 unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
  22                 unsigned long ap;       /* Ap encoding used by PowerISA 3.0 */
  23         };
  24 };
  25 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  26
  27 #endif /* __ASSEMBLY__ */
  28
  29 /* 64-bit classic hash table MMU */
  30 #include <asm/book3s/64/mmu-hash.h>
  31
  32 #ifndef __ASSEMBLY__
  33 /*
  34  * ISA 3.0 partition and process table entry format
  35  */
  36 struct prtb_entry {
  37         __be64 prtb0;
  38         __be64 prtb1;
  39 };
  40 extern struct prtb_entry *process_tb;
  41
  42 struct patb_entry {
  43         __be64 patb0;
  44         __be64 patb1;
  45 };
  46 extern struct patb_entry *partition_tb;
  47
  48 /* Bits in patb0 field */
  49 #define PATB_HR         (1UL << 63)
  50 #define RPDB_MASK       0x0fffffffffffff00UL
  51 #define RPDB_SHIFT      (1UL << 8)
  52 #define RTS1_SHIFT      61              /* top 2 bits of radix tree size */
  53 #define RTS1_MASK       (3UL << RTS1_SHIFT)
  54 #define RTS2_SHIFT      5               /* bottom 3 bits of radix tree size */
  55 #define RTS2_MASK       (7UL << RTS2_SHIFT)
  56 #define RPDS_MASK       0x1f            /* root page dir. size field */
  57
  58 /* Bits in patb1 field */
  59 #define PATB_GR         (1UL << 63)     /* guest uses radix; must match HR */
  60 #define PRTS_MASK       0x1f            /* process table size field */
  61 #define PRTB_MASK       0x0ffffffffffff000UL
  62
  63 /* Number of supported PID bits */
  64 extern unsigned int mmu_pid_bits;
  65
  66 /* Base PID to allocate from */
  67 extern unsigned int mmu_base_pid;
  68
  69 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4)
  70 #define PRTB_ENTRIES    (1ul << mmu_pid_bits)
  71
  72 /*
  73  * Power9 currently only support 64K partition table size.
  74  */
  75 #define PATB_SIZE_SHIFT 16
  76
  77 typedef unsigned long mm_context_id_t;
  78 struct spinlock;
  79
  80 /* Maximum possible number of NPUs in a system. */
  81 #define NV_MAX_NPUS 8
  82
  83 typedef struct {
  84         mm_context_id_t id;
  85         u16 user_psize;         /* page size index */
  86
  87         /* Number of bits in the mm_cpumask */
  88         atomic_t active_cpus;
  89
  90         /* NPU NMMU context */
  91         struct npu_context *npu_context;
  92
  93 #ifdef CONFIG_PPC_MM_SLICES
  94         u64 low_slices_psize;   /* SLB page size encodings */
  95         unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
  96         unsigned long addr_limit;
  97 #else
  98         u16 sllp;               /* SLB page size encoding */
  99 #endif
 100         unsigned long vdso_base;
 101 #ifdef CONFIG_PPC_SUBPAGE_PROT
 102         struct subpage_prot_table spt;
 103 #endif /* CONFIG_PPC_SUBPAGE_PROT */
 104 #ifdef CONFIG_PPC_64K_PAGES
 105         /* for 4K PTE fragment support */
 106         void *pte_frag;
 107 #endif
 108 #ifdef CONFIG_SPAPR_TCE_IOMMU
 109         struct list_head iommu_group_mem_list;
 110 #endif
 111 } mm_context_t;
 112
 113 /*
 114  * The current system page and segment sizes
 115  */
 116 extern int mmu_linear_psize;
 117 extern int mmu_virtual_psize;
 118 extern int mmu_vmalloc_psize;
 119 extern int mmu_vmemmap_psize;
 120 extern int mmu_io_psize;
 121
 122 /* MMU initialization */
 123 void mmu_early_init_devtree(void);
 124 void hash__early_init_devtree(void);
 125 void radix__early_init_devtree(void);
 126 extern void radix_init_native(void);
 127 extern void hash__early_init_mmu(void);
 128 extern void radix__early_init_mmu(void);
 129 static inline void early_init_mmu(void)
 130 {
 131         if (radix_enabled())
 132                 return radix__early_init_mmu();
 133         return hash__early_init_mmu();
 134 }
 135 extern void hash__early_init_mmu_secondary(void);
 136 extern void radix__early_init_mmu_secondary(void);
 137 static inline void early_init_mmu_secondary(void)
 138 {
 139         if (radix_enabled())
 140                 return radix__early_init_mmu_secondary();
 141         return hash__early_init_mmu_secondary();
 142 }
 143
 144 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 145                                          phys_addr_t first_memblock_size);
 146 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 147                                          phys_addr_t first_memblock_size);
 148 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 149                                               phys_addr_t first_memblock_size)
 150 {
 151         if (early_radix_enabled())
 152                 return radix__setup_initial_memory_limit(first_memblock_base,
 153                                                    first_memblock_size);
 154         return hash__setup_initial_memory_limit(first_memblock_base,
 155                                            first_memblock_size);
 156 }
 157
 158 extern int (*register_process_table)(unsigned long base, unsigned long page_size,
 159                                      unsigned long tbl_size);
 160
 161 #ifdef CONFIG_PPC_PSERIES
 162 extern void radix_init_pseries(void);
 163 #else
 164 static inline void radix_init_pseries(void) { };
 165 #endif
 166
 167 #endif /* __ASSEMBLY__ */
 168 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */