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git.ipfire.org Git - thirdparty/kernel/stable.git/blob - arch/powerpc/include/asm/book3s/64/pgtable.h
1 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
4 #include <asm-generic/5level-fixup.h>
7 #include <linux/mmdebug.h>
11 * Common bits between hash and Radix page table
13 #define _PAGE_BIT_SWAP_TYPE 0
16 #define _PAGE_SHARED 0
18 #define _PAGE_EXEC 0x00001 /* execute permission */
19 #define _PAGE_WRITE 0x00002 /* write access allowed */
20 #define _PAGE_READ 0x00004 /* read access allowed */
21 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
22 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
23 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
24 #define _PAGE_SAO 0x00010 /* Strong access order */
25 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
26 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
27 #define _PAGE_DIRTY 0x00080 /* C: page changed */
28 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
32 #define _RPAGE_SW0 0x2000000000000000UL
33 #define _RPAGE_SW1 0x00800
34 #define _RPAGE_SW2 0x00400
35 #define _RPAGE_SW3 0x00200
36 #define _RPAGE_RSV1 0x1000000000000000UL
37 #define _RPAGE_RSV2 0x0800000000000000UL
38 #define _RPAGE_RSV3 0x0400000000000000UL
39 #define _RPAGE_RSV4 0x0200000000000000UL
41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
45 * Top and bottom bits of RPN which can be used by hash
46 * translation mode, because we expect them to be zero
49 #define _RPAGE_RPN0 0x01000
50 #define _RPAGE_RPN1 0x02000
51 #define _RPAGE_RPN44 0x0100000000000000UL
52 #define _RPAGE_RPN43 0x0080000000000000UL
53 #define _RPAGE_RPN42 0x0040000000000000UL
54 #define _RPAGE_RPN41 0x0020000000000000UL
56 /* Max physical address bit as per radix table */
57 #define _RPAGE_PA_MAX 57
60 * Max physical address bit we will use for now.
62 * This is mostly a hardware limitation and for now Power9 has
65 * This is different from the number of physical bit required to address
66 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
67 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
68 * number of sections we can support (SECTIONS_SHIFT).
70 * This is different from Radix page table limitation above and
71 * should always be less than that. The limit is done such that
72 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
73 * for hash linux page table specific bits.
75 * In order to be compatible with future hardware generations we keep
76 * some offsets and limit this for now to 53
78 #define _PAGE_PA_MAX 53
80 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
81 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
83 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
84 * Instead of fixing all of them, add an alternate define which
85 * maps CI pte mapping.
87 #define _PAGE_NO_CACHE _PAGE_TOLERANT
89 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
90 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
91 * and every thing below PAGE_SHIFT;
93 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
95 * set of bits not changed in pmd_modify. Even though we have hash specific bits
96 * in here, on radix we expect them to be zero.
98 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
99 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
102 * user access blocked by key
104 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
105 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
106 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
107 _PAGE_RW | _PAGE_EXEC)
109 * No page size encoding in the linux PTE
111 #define _PAGE_PSIZE 0
113 * _PAGE_CHG_MASK masks of bits that are to be preserved across
116 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
117 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
120 * Mask of bits returned by pte_pgprot()
122 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
123 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
124 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
127 * We define 2 sets of base prot bits, one for basic pages (ie,
128 * cacheable kernel and user pages) and one for non cacheable
129 * pages. We always set _PAGE_COHERENT when SMP is enabled or
130 * the processor might need it for DMA coherency.
132 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
133 #define _PAGE_BASE (_PAGE_BASE_NC)
135 /* Permission masks used to generate the __P and __S table,
137 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
139 * Write permissions imply read permissions for now (we could make write-only
140 * pages on BookE but we don't bother for now). Execute permission control is
141 * possible on platforms that define _PAGE_EXEC
143 * Note due to the way vm flags are laid out, the bits are XWR
145 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
146 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
147 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
148 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
149 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
150 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
151 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
153 #define __P000 PAGE_NONE
154 #define __P001 PAGE_READONLY
155 #define __P010 PAGE_COPY
156 #define __P011 PAGE_COPY
157 #define __P100 PAGE_READONLY_X
158 #define __P101 PAGE_READONLY_X
159 #define __P110 PAGE_COPY_X
160 #define __P111 PAGE_COPY_X
162 #define __S000 PAGE_NONE
163 #define __S001 PAGE_READONLY
164 #define __S010 PAGE_SHARED
165 #define __S011 PAGE_SHARED
166 #define __S100 PAGE_READONLY_X
167 #define __S101 PAGE_READONLY_X
168 #define __S110 PAGE_SHARED_X
169 #define __S111 PAGE_SHARED_X
171 /* Permission masks used for kernel mappings */
172 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
173 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
175 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
176 _PAGE_NON_IDEMPOTENT)
177 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
178 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
179 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
182 * Protection used for kernel text. We want the debuggers to be able to
183 * set breakpoints anywhere, so don't write protect the kernel text
184 * on platforms where such control is possible.
186 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
187 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
188 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
190 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
193 /* Make modules code happy. We don't set RO yet */
194 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
195 #define PAGE_AGP (PAGE_KERNEL_NC)
201 extern unsigned long __pte_index_size
;
202 extern unsigned long __pmd_index_size
;
203 extern unsigned long __pud_index_size
;
204 extern unsigned long __pgd_index_size
;
205 extern unsigned long __pmd_cache_index
;
206 #define PTE_INDEX_SIZE __pte_index_size
207 #define PMD_INDEX_SIZE __pmd_index_size
208 #define PUD_INDEX_SIZE __pud_index_size
209 #define PGD_INDEX_SIZE __pgd_index_size
210 #define PMD_CACHE_INDEX __pmd_cache_index
212 * Because of use of pte fragments and THP, size of page table
213 * are not always derived out of index size above.
215 extern unsigned long __pte_table_size
;
216 extern unsigned long __pmd_table_size
;
217 extern unsigned long __pud_table_size
;
218 extern unsigned long __pgd_table_size
;
219 #define PTE_TABLE_SIZE __pte_table_size
220 #define PMD_TABLE_SIZE __pmd_table_size
221 #define PUD_TABLE_SIZE __pud_table_size
222 #define PGD_TABLE_SIZE __pgd_table_size
224 extern unsigned long __pmd_val_bits
;
225 extern unsigned long __pud_val_bits
;
226 extern unsigned long __pgd_val_bits
;
227 #define PMD_VAL_BITS __pmd_val_bits
228 #define PUD_VAL_BITS __pud_val_bits
229 #define PGD_VAL_BITS __pgd_val_bits
231 extern unsigned long __pte_frag_nr
;
232 #define PTE_FRAG_NR __pte_frag_nr
233 extern unsigned long __pte_frag_size_shift
;
234 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
235 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
237 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
238 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
239 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
240 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
242 /* PMD_SHIFT determines what a second-level page table entry can map */
243 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
244 #define PMD_SIZE (1UL << PMD_SHIFT)
245 #define PMD_MASK (~(PMD_SIZE-1))
247 /* PUD_SHIFT determines what a third-level page table entry can map */
248 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
249 #define PUD_SIZE (1UL << PUD_SHIFT)
250 #define PUD_MASK (~(PUD_SIZE-1))
252 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
253 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
254 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
255 #define PGDIR_MASK (~(PGDIR_SIZE-1))
257 /* Bits to mask out from a PMD to get to the PTE page */
258 #define PMD_MASKED_BITS 0xc0000000000000ffUL
259 /* Bits to mask out from a PUD to get to the PMD page */
260 #define PUD_MASKED_BITS 0xc0000000000000ffUL
261 /* Bits to mask out from a PGD to get to the PUD page */
262 #define PGD_MASKED_BITS 0xc0000000000000ffUL
264 extern unsigned long __vmalloc_start
;
265 extern unsigned long __vmalloc_end
;
266 #define VMALLOC_START __vmalloc_start
267 #define VMALLOC_END __vmalloc_end
269 extern unsigned long __kernel_virt_start
;
270 extern unsigned long __kernel_virt_size
;
271 #define KERN_VIRT_START __kernel_virt_start
272 #define KERN_VIRT_SIZE __kernel_virt_size
273 extern struct page
*vmemmap
;
274 extern unsigned long ioremap_bot
;
275 extern unsigned long pci_io_base
;
276 #endif /* __ASSEMBLY__ */
278 #include <asm/book3s/64/hash.h>
279 #include <asm/book3s/64/radix.h>
281 #ifdef CONFIG_PPC_64K_PAGES
282 #include <asm/book3s/64/pgtable-64k.h>
284 #include <asm/book3s/64/pgtable-4k.h>
287 #include <asm/barrier.h>
289 * The second half of the kernel virtual space is used for IO mappings,
290 * it's itself carved into the PIO region (ISA and PHB IO space) and
293 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
294 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
295 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
297 #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
298 #define FULL_IO_SIZE 0x80000000ul
299 #define ISA_IO_BASE (KERN_IO_START)
300 #define ISA_IO_END (KERN_IO_START + 0x10000ul)
301 #define PHB_IO_BASE (ISA_IO_END)
302 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
303 #define IOREMAP_BASE (PHB_IO_END)
304 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
306 /* Advertise special mapping type for AGP */
307 #define HAVE_PAGE_AGP
309 /* Advertise support for _PAGE_SPECIAL */
310 #define __HAVE_ARCH_PTE_SPECIAL
315 * This is the default implementation of various PTE accessors, it's
316 * used in all cases except Book3S with 64K pages where we have a
317 * concept of sub-pages
321 #define __real_pte(e,p) ((real_pte_t){(e)})
322 #define __rpte_to_pte(r) ((r).pte)
323 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
325 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
328 shift = mmu_psize_defs[psize].shift; \
330 #define pte_iterate_hashed_end() } while(0)
333 * We expect this to be called only for user addresses or kernel virtual
334 * addresses other than the linear mapping.
336 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
338 #endif /* __real_pte */
340 static inline unsigned long pte_update(struct mm_struct
*mm
, unsigned long addr
,
341 pte_t
*ptep
, unsigned long clr
,
342 unsigned long set
, int huge
)
345 return radix__pte_update(mm
, addr
, ptep
, clr
, set
, huge
);
346 return hash__pte_update(mm
, addr
, ptep
, clr
, set
, huge
);
349 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
350 * We currently remove entries from the hashtable regardless of whether
351 * the entry was young or dirty.
353 * We should be more intelligent about this but for the moment we override
354 * these functions and force a tlb flush unconditionally
355 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
356 * function for both hash and radix.
358 static inline int __ptep_test_and_clear_young(struct mm_struct
*mm
,
359 unsigned long addr
, pte_t
*ptep
)
363 if ((pte_raw(*ptep
) & cpu_to_be64(_PAGE_ACCESSED
| H_PAGE_HASHPTE
)) == 0)
365 old
= pte_update(mm
, addr
, ptep
, _PAGE_ACCESSED
, 0, 0);
366 return (old
& _PAGE_ACCESSED
) != 0;
369 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
370 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
373 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
377 static inline int __pte_write(pte_t pte
)
379 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_WRITE
));
382 #ifdef CONFIG_NUMA_BALANCING
383 #define pte_savedwrite pte_savedwrite
384 static inline bool pte_savedwrite(pte_t pte
)
387 * Saved write ptes are prot none ptes that doesn't have
388 * privileged bit sit. We mark prot none as one which has
389 * present and pviliged bit set and RWX cleared. To mark
390 * protnone which used to have _PAGE_WRITE set we clear
391 * the privileged bit.
393 return !(pte_raw(pte
) & cpu_to_be64(_PAGE_RWX
| _PAGE_PRIVILEGED
));
396 #define pte_savedwrite pte_savedwrite
397 static inline bool pte_savedwrite(pte_t pte
)
403 static inline int pte_write(pte_t pte
)
405 return __pte_write(pte
) || pte_savedwrite(pte
);
408 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
409 static inline void ptep_set_wrprotect(struct mm_struct
*mm
, unsigned long addr
,
412 if (__pte_write(*ptep
))
413 pte_update(mm
, addr
, ptep
, _PAGE_WRITE
, 0, 0);
414 else if (unlikely(pte_savedwrite(*ptep
)))
415 pte_update(mm
, addr
, ptep
, 0, _PAGE_PRIVILEGED
, 0);
418 static inline void huge_ptep_set_wrprotect(struct mm_struct
*mm
,
419 unsigned long addr
, pte_t
*ptep
)
422 * We should not find protnone for hugetlb, but this complete the
425 if (__pte_write(*ptep
))
426 pte_update(mm
, addr
, ptep
, _PAGE_WRITE
, 0, 1);
427 else if (unlikely(pte_savedwrite(*ptep
)))
428 pte_update(mm
, addr
, ptep
, 0, _PAGE_PRIVILEGED
, 1);
431 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
432 static inline pte_t
ptep_get_and_clear(struct mm_struct
*mm
,
433 unsigned long addr
, pte_t
*ptep
)
435 unsigned long old
= pte_update(mm
, addr
, ptep
, ~0UL, 0, 0);
439 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
440 static inline pte_t
ptep_get_and_clear_full(struct mm_struct
*mm
,
442 pte_t
*ptep
, int full
)
444 if (full
&& radix_enabled()) {
446 * Let's skip the DD1 style pte update here. We know that
447 * this is a full mm pte clear and hence can be sure there is
448 * no parallel set_pte.
450 return radix__ptep_get_and_clear_full(mm
, addr
, ptep
, full
);
452 return ptep_get_and_clear(mm
, addr
, ptep
);
456 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
,
459 pte_update(mm
, addr
, ptep
, ~0UL, 0, 0);
462 static inline int pte_dirty(pte_t pte
)
464 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_DIRTY
));
467 static inline int pte_young(pte_t pte
)
469 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_ACCESSED
));
472 static inline int pte_special(pte_t pte
)
474 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_SPECIAL
));
477 static inline pgprot_t
pte_pgprot(pte_t pte
) { return __pgprot(pte_val(pte
) & PAGE_PROT_BITS
); }
479 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
480 static inline bool pte_soft_dirty(pte_t pte
)
482 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_SOFT_DIRTY
));
485 static inline pte_t
pte_mksoft_dirty(pte_t pte
)
487 return __pte(pte_val(pte
) | _PAGE_SOFT_DIRTY
);
490 static inline pte_t
pte_clear_soft_dirty(pte_t pte
)
492 return __pte(pte_val(pte
) & ~_PAGE_SOFT_DIRTY
);
494 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
496 #ifdef CONFIG_NUMA_BALANCING
497 static inline int pte_protnone(pte_t pte
)
499 return (pte_raw(pte
) & cpu_to_be64(_PAGE_PRESENT
| _PAGE_PTE
| _PAGE_RWX
)) ==
500 cpu_to_be64(_PAGE_PRESENT
| _PAGE_PTE
);
503 #define pte_mk_savedwrite pte_mk_savedwrite
504 static inline pte_t
pte_mk_savedwrite(pte_t pte
)
507 * Used by Autonuma subsystem to preserve the write bit
508 * while marking the pte PROT_NONE. Only allow this
511 VM_BUG_ON((pte_raw(pte
) & cpu_to_be64(_PAGE_PRESENT
| _PAGE_RWX
| _PAGE_PRIVILEGED
)) !=
512 cpu_to_be64(_PAGE_PRESENT
| _PAGE_PRIVILEGED
));
513 return __pte(pte_val(pte
) & ~_PAGE_PRIVILEGED
);
516 #define pte_clear_savedwrite pte_clear_savedwrite
517 static inline pte_t
pte_clear_savedwrite(pte_t pte
)
520 * Used by KSM subsystem to make a protnone pte readonly.
522 VM_BUG_ON(!pte_protnone(pte
));
523 return __pte(pte_val(pte
) | _PAGE_PRIVILEGED
);
526 #define pte_clear_savedwrite pte_clear_savedwrite
527 static inline pte_t
pte_clear_savedwrite(pte_t pte
)
530 return __pte(pte_val(pte
) & ~_PAGE_WRITE
);
532 #endif /* CONFIG_NUMA_BALANCING */
534 static inline int pte_present(pte_t pte
)
536 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_PRESENT
));
539 * Conversion functions: convert a page and protection to a page entry,
540 * and a page entry and page directory to the page they refer to.
542 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
545 static inline pte_t
pfn_pte(unsigned long pfn
, pgprot_t pgprot
)
547 return __pte((((pte_basic_t
)(pfn
) << PAGE_SHIFT
) & PTE_RPN_MASK
) |
551 static inline unsigned long pte_pfn(pte_t pte
)
553 return (pte_val(pte
) & PTE_RPN_MASK
) >> PAGE_SHIFT
;
556 /* Generic modifiers for PTE bits */
557 static inline pte_t
pte_wrprotect(pte_t pte
)
559 if (unlikely(pte_savedwrite(pte
)))
560 return pte_clear_savedwrite(pte
);
561 return __pte(pte_val(pte
) & ~_PAGE_WRITE
);
564 static inline pte_t
pte_mkclean(pte_t pte
)
566 return __pte(pte_val(pte
) & ~_PAGE_DIRTY
);
569 static inline pte_t
pte_mkold(pte_t pte
)
571 return __pte(pte_val(pte
) & ~_PAGE_ACCESSED
);
574 static inline pte_t
pte_mkwrite(pte_t pte
)
577 * write implies read, hence set both
579 return __pte(pte_val(pte
) | _PAGE_RW
);
582 static inline pte_t
pte_mkdirty(pte_t pte
)
584 return __pte(pte_val(pte
) | _PAGE_DIRTY
| _PAGE_SOFT_DIRTY
);
587 static inline pte_t
pte_mkyoung(pte_t pte
)
589 return __pte(pte_val(pte
) | _PAGE_ACCESSED
);
592 static inline pte_t
pte_mkspecial(pte_t pte
)
594 return __pte(pte_val(pte
) | _PAGE_SPECIAL
);
597 static inline pte_t
pte_mkhuge(pte_t pte
)
602 static inline pte_t
pte_modify(pte_t pte
, pgprot_t newprot
)
604 /* FIXME!! check whether this need to be a conditional */
605 return __pte((pte_val(pte
) & _PAGE_CHG_MASK
) | pgprot_val(newprot
));
608 static inline bool pte_user(pte_t pte
)
610 return !(pte_raw(pte
) & cpu_to_be64(_PAGE_PRIVILEGED
));
613 /* Encode and de-code a swap entry */
614 #define MAX_SWAPFILES_CHECK() do { \
615 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
617 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
618 * We filter HPTEFLAGS on set_pte. \
620 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
621 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
624 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
626 #define SWP_TYPE_BITS 5
627 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
628 & ((1UL << SWP_TYPE_BITS) - 1))
629 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
630 #define __swp_entry(type, offset) ((swp_entry_t) { \
631 ((type) << _PAGE_BIT_SWAP_TYPE) \
632 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
634 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
635 * swap type and offset we get from swap and convert that to pte to find a
636 * matching pte in linux page table.
637 * Clear bits not found in swap entries here.
639 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
640 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
642 #ifdef CONFIG_MEM_SOFT_DIRTY
643 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
645 #define _PAGE_SWP_SOFT_DIRTY 0UL
646 #endif /* CONFIG_MEM_SOFT_DIRTY */
648 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
649 static inline pte_t
pte_swp_mksoft_dirty(pte_t pte
)
651 return __pte(pte_val(pte
) | _PAGE_SWP_SOFT_DIRTY
);
654 static inline bool pte_swp_soft_dirty(pte_t pte
)
656 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY
));
659 static inline pte_t
pte_swp_clear_soft_dirty(pte_t pte
)
661 return __pte(pte_val(pte
) & ~_PAGE_SWP_SOFT_DIRTY
);
663 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
665 static inline bool check_pte_access(unsigned long access
, unsigned long ptev
)
668 * This check for _PAGE_RWX and _PAGE_PRESENT bits
673 * This check for access to privilege space
675 if ((access
& _PAGE_PRIVILEGED
) != (ptev
& _PAGE_PRIVILEGED
))
681 * Generic functions with hash/radix callbacks
684 static inline void __ptep_set_access_flags(struct mm_struct
*mm
,
685 pte_t
*ptep
, pte_t entry
,
686 unsigned long address
)
689 return radix__ptep_set_access_flags(mm
, ptep
, entry
, address
);
690 return hash__ptep_set_access_flags(ptep
, entry
);
693 #define __HAVE_ARCH_PTE_SAME
694 static inline int pte_same(pte_t pte_a
, pte_t pte_b
)
697 return radix__pte_same(pte_a
, pte_b
);
698 return hash__pte_same(pte_a
, pte_b
);
701 static inline int pte_none(pte_t pte
)
704 return radix__pte_none(pte
);
705 return hash__pte_none(pte
);
708 static inline void __set_pte_at(struct mm_struct
*mm
, unsigned long addr
,
709 pte_t
*ptep
, pte_t pte
, int percpu
)
712 return radix__set_pte_at(mm
, addr
, ptep
, pte
, percpu
);
713 return hash__set_pte_at(mm
, addr
, ptep
, pte
, percpu
);
716 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
718 #define pgprot_noncached pgprot_noncached
719 static inline pgprot_t
pgprot_noncached(pgprot_t prot
)
721 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
) |
722 _PAGE_NON_IDEMPOTENT
);
725 #define pgprot_noncached_wc pgprot_noncached_wc
726 static inline pgprot_t
pgprot_noncached_wc(pgprot_t prot
)
728 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
) |
732 #define pgprot_cached pgprot_cached
733 static inline pgprot_t
pgprot_cached(pgprot_t prot
)
735 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
));
738 #define pgprot_writecombine pgprot_writecombine
739 static inline pgprot_t
pgprot_writecombine(pgprot_t prot
)
741 return pgprot_noncached_wc(prot
);
744 * check a pte mapping have cache inhibited property
746 static inline bool pte_ci(pte_t pte
)
748 unsigned long pte_v
= pte_val(pte
);
750 if (((pte_v
& _PAGE_CACHE_CTL
) == _PAGE_TOLERANT
) ||
751 ((pte_v
& _PAGE_CACHE_CTL
) == _PAGE_NON_IDEMPOTENT
))
756 static inline void pmd_set(pmd_t
*pmdp
, unsigned long val
)
761 static inline void pmd_clear(pmd_t
*pmdp
)
766 static inline int pmd_none(pmd_t pmd
)
768 return !pmd_raw(pmd
);
771 static inline int pmd_present(pmd_t pmd
)
774 return !pmd_none(pmd
);
777 static inline int pmd_bad(pmd_t pmd
)
780 return radix__pmd_bad(pmd
);
781 return hash__pmd_bad(pmd
);
784 static inline void pud_set(pud_t
*pudp
, unsigned long val
)
789 static inline void pud_clear(pud_t
*pudp
)
794 static inline int pud_none(pud_t pud
)
796 return !pud_raw(pud
);
799 static inline int pud_present(pud_t pud
)
801 return !pud_none(pud
);
804 extern struct page
*pud_page(pud_t pud
);
805 extern struct page
*pmd_page(pmd_t pmd
);
806 static inline pte_t
pud_pte(pud_t pud
)
808 return __pte_raw(pud_raw(pud
));
811 static inline pud_t
pte_pud(pte_t pte
)
813 return __pud_raw(pte_raw(pte
));
815 #define pud_write(pud) pte_write(pud_pte(pud))
817 static inline int pud_bad(pud_t pud
)
820 return radix__pud_bad(pud
);
821 return hash__pud_bad(pud
);
825 #define pgd_write(pgd) pte_write(pgd_pte(pgd))
826 static inline void pgd_set(pgd_t
*pgdp
, unsigned long val
)
831 static inline void pgd_clear(pgd_t
*pgdp
)
836 static inline int pgd_none(pgd_t pgd
)
838 return !pgd_raw(pgd
);
841 static inline int pgd_present(pgd_t pgd
)
843 return !pgd_none(pgd
);
846 static inline pte_t
pgd_pte(pgd_t pgd
)
848 return __pte_raw(pgd_raw(pgd
));
851 static inline pgd_t
pte_pgd(pte_t pte
)
853 return __pgd_raw(pte_raw(pte
));
856 static inline int pgd_bad(pgd_t pgd
)
859 return radix__pgd_bad(pgd
);
860 return hash__pgd_bad(pgd
);
863 extern struct page
*pgd_page(pgd_t pgd
);
865 /* Pointers in the page table tree are physical addresses */
866 #define __pgtable_ptr_val(ptr) __pa(ptr)
868 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
869 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
870 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
872 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
873 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
874 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
875 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
878 * Find an entry in a page-table-directory. We combine the address region
879 * (the high order N bits) and the pgd portion of the address.
882 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
884 #define pud_offset(pgdp, addr) \
885 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
886 #define pmd_offset(pudp,addr) \
887 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
888 #define pte_offset_kernel(dir,addr) \
889 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
891 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
892 #define pte_unmap(pte) do { } while(0)
894 /* to find an entry in a kernel page-table-directory */
895 /* This now only contains the vmalloc pages */
896 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
898 #define pte_ERROR(e) \
899 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
900 #define pmd_ERROR(e) \
901 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
902 #define pud_ERROR(e) \
903 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
904 #define pgd_ERROR(e) \
905 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
907 static inline int map_kernel_page(unsigned long ea
, unsigned long pa
,
910 if (radix_enabled()) {
911 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
912 unsigned long page_size
= 1 << mmu_psize_defs
[mmu_io_psize
].shift
;
913 WARN((page_size
!= PAGE_SIZE
), "I/O page size != PAGE_SIZE");
915 return radix__map_kernel_page(ea
, pa
, __pgprot(flags
), PAGE_SIZE
);
917 return hash__map_kernel_page(ea
, pa
, flags
);
920 static inline int __meminit
vmemmap_create_mapping(unsigned long start
,
921 unsigned long page_size
,
925 return radix__vmemmap_create_mapping(start
, page_size
, phys
);
926 return hash__vmemmap_create_mapping(start
, page_size
, phys
);
929 #ifdef CONFIG_MEMORY_HOTPLUG
930 static inline void vmemmap_remove_mapping(unsigned long start
,
931 unsigned long page_size
)
934 return radix__vmemmap_remove_mapping(start
, page_size
);
935 return hash__vmemmap_remove_mapping(start
, page_size
);
938 struct page
*realmode_pfn_to_page(unsigned long pfn
);
940 static inline pte_t
pmd_pte(pmd_t pmd
)
942 return __pte_raw(pmd_raw(pmd
));
945 static inline pmd_t
pte_pmd(pte_t pte
)
947 return __pmd_raw(pte_raw(pte
));
950 static inline pte_t
*pmdp_ptep(pmd_t
*pmd
)
954 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
955 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
956 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
957 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
958 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
959 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
960 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
961 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
962 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
963 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
964 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
966 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
967 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
968 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
969 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
970 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
972 #ifdef CONFIG_NUMA_BALANCING
973 static inline int pmd_protnone(pmd_t pmd
)
975 return pte_protnone(pmd_pte(pmd
));
977 #endif /* CONFIG_NUMA_BALANCING */
979 #define __HAVE_ARCH_PMD_WRITE
980 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
981 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
982 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
984 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
985 extern pmd_t
pfn_pmd(unsigned long pfn
, pgprot_t pgprot
);
986 extern pmd_t
mk_pmd(struct page
*page
, pgprot_t pgprot
);
987 extern pmd_t
pmd_modify(pmd_t pmd
, pgprot_t newprot
);
988 extern void set_pmd_at(struct mm_struct
*mm
, unsigned long addr
,
989 pmd_t
*pmdp
, pmd_t pmd
);
990 extern void update_mmu_cache_pmd(struct vm_area_struct
*vma
, unsigned long addr
,
992 extern int hash__has_transparent_hugepage(void);
993 static inline int has_transparent_hugepage(void)
996 return radix__has_transparent_hugepage();
997 return hash__has_transparent_hugepage();
999 #define has_transparent_hugepage has_transparent_hugepage
1001 static inline unsigned long
1002 pmd_hugepage_update(struct mm_struct
*mm
, unsigned long addr
, pmd_t
*pmdp
,
1003 unsigned long clr
, unsigned long set
)
1005 if (radix_enabled())
1006 return radix__pmd_hugepage_update(mm
, addr
, pmdp
, clr
, set
);
1007 return hash__pmd_hugepage_update(mm
, addr
, pmdp
, clr
, set
);
1010 static inline int pmd_large(pmd_t pmd
)
1012 return !!(pmd_raw(pmd
) & cpu_to_be64(_PAGE_PTE
));
1015 static inline pmd_t
pmd_mknotpresent(pmd_t pmd
)
1017 return __pmd(pmd_val(pmd
) & ~_PAGE_PRESENT
);
1020 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1021 * the below will work for radix too
1023 static inline int __pmdp_test_and_clear_young(struct mm_struct
*mm
,
1024 unsigned long addr
, pmd_t
*pmdp
)
1028 if ((pmd_raw(*pmdp
) & cpu_to_be64(_PAGE_ACCESSED
| H_PAGE_HASHPTE
)) == 0)
1030 old
= pmd_hugepage_update(mm
, addr
, pmdp
, _PAGE_ACCESSED
, 0);
1031 return ((old
& _PAGE_ACCESSED
) != 0);
1034 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1035 static inline void pmdp_set_wrprotect(struct mm_struct
*mm
, unsigned long addr
,
1038 if (__pmd_write((*pmdp
)))
1039 pmd_hugepage_update(mm
, addr
, pmdp
, _PAGE_WRITE
, 0);
1040 else if (unlikely(pmd_savedwrite(*pmdp
)))
1041 pmd_hugepage_update(mm
, addr
, pmdp
, 0, _PAGE_PRIVILEGED
);
1044 static inline int pmd_trans_huge(pmd_t pmd
)
1046 if (radix_enabled())
1047 return radix__pmd_trans_huge(pmd
);
1048 return hash__pmd_trans_huge(pmd
);
1051 #define __HAVE_ARCH_PMD_SAME
1052 static inline int pmd_same(pmd_t pmd_a
, pmd_t pmd_b
)
1054 if (radix_enabled())
1055 return radix__pmd_same(pmd_a
, pmd_b
);
1056 return hash__pmd_same(pmd_a
, pmd_b
);
1059 static inline pmd_t
pmd_mkhuge(pmd_t pmd
)
1061 if (radix_enabled())
1062 return radix__pmd_mkhuge(pmd
);
1063 return hash__pmd_mkhuge(pmd
);
1066 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1067 extern int pmdp_set_access_flags(struct vm_area_struct
*vma
,
1068 unsigned long address
, pmd_t
*pmdp
,
1069 pmd_t entry
, int dirty
);
1071 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1072 extern int pmdp_test_and_clear_young(struct vm_area_struct
*vma
,
1073 unsigned long address
, pmd_t
*pmdp
);
1075 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1076 static inline pmd_t
pmdp_huge_get_and_clear(struct mm_struct
*mm
,
1077 unsigned long addr
, pmd_t
*pmdp
)
1079 if (radix_enabled())
1080 return radix__pmdp_huge_get_and_clear(mm
, addr
, pmdp
);
1081 return hash__pmdp_huge_get_and_clear(mm
, addr
, pmdp
);
1084 static inline pmd_t
pmdp_collapse_flush(struct vm_area_struct
*vma
,
1085 unsigned long address
, pmd_t
*pmdp
)
1087 if (radix_enabled())
1088 return radix__pmdp_collapse_flush(vma
, address
, pmdp
);
1089 return hash__pmdp_collapse_flush(vma
, address
, pmdp
);
1091 #define pmdp_collapse_flush pmdp_collapse_flush
1093 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1094 static inline void pgtable_trans_huge_deposit(struct mm_struct
*mm
,
1095 pmd_t
*pmdp
, pgtable_t pgtable
)
1097 if (radix_enabled())
1098 return radix__pgtable_trans_huge_deposit(mm
, pmdp
, pgtable
);
1099 return hash__pgtable_trans_huge_deposit(mm
, pmdp
, pgtable
);
1102 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1103 static inline pgtable_t
pgtable_trans_huge_withdraw(struct mm_struct
*mm
,
1106 if (radix_enabled())
1107 return radix__pgtable_trans_huge_withdraw(mm
, pmdp
);
1108 return hash__pgtable_trans_huge_withdraw(mm
, pmdp
);
1111 #define __HAVE_ARCH_PMDP_INVALIDATE
1112 extern void pmdp_invalidate(struct vm_area_struct
*vma
, unsigned long address
,
1115 #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
1116 static inline void pmdp_huge_split_prepare(struct vm_area_struct
*vma
,
1117 unsigned long address
, pmd_t
*pmdp
)
1119 if (radix_enabled())
1120 return radix__pmdp_huge_split_prepare(vma
, address
, pmdp
);
1121 return hash__pmdp_huge_split_prepare(vma
, address
, pmdp
);
1124 #define pmd_move_must_withdraw pmd_move_must_withdraw
1126 static inline int pmd_move_must_withdraw(struct spinlock
*new_pmd_ptl
,
1127 struct spinlock
*old_pmd_ptl
,
1128 struct vm_area_struct
*vma
)
1130 if (radix_enabled())
1133 * Archs like ppc64 use pgtable to store per pmd
1134 * specific information. So when we switch the pmd,
1135 * we should also withdraw and deposit the pgtable
1141 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1142 static inline bool arch_needs_pgtable_deposit(void)
1144 if (radix_enabled())
1149 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1150 #endif /* __ASSEMBLY__ */
1151 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */