]>
git.ipfire.org Git - thirdparty/kernel/stable.git/blob - arch/powerpc/include/asm/book3s/64/pgtable.h
fb8380a2d8d551d60a7974a9340065cc65033b19
1 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
4 #include <asm-generic/5level-fixup.h>
7 #include <linux/mmdebug.h>
11 * Common bits between hash and Radix page table
13 #define _PAGE_BIT_SWAP_TYPE 0
17 #define _PAGE_EXEC 0x00001 /* execute permission */
18 #define _PAGE_WRITE 0x00002 /* write access allowed */
19 #define _PAGE_READ 0x00004 /* read access allowed */
20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
23 #define _PAGE_SAO 0x00010 /* Strong access order */
24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
26 #define _PAGE_DIRTY 0x00080 /* C: page changed */
27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
31 #define _RPAGE_SW0 0x2000000000000000UL
32 #define _RPAGE_SW1 0x00800
33 #define _RPAGE_SW2 0x00400
34 #define _RPAGE_SW3 0x00200
35 #define _RPAGE_RSV1 0x1000000000000000UL
36 #define _RPAGE_RSV2 0x0800000000000000UL
37 #define _RPAGE_RSV3 0x0400000000000000UL
38 #define _RPAGE_RSV4 0x0200000000000000UL
40 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
41 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
44 * Top and bottom bits of RPN which can be used by hash
45 * translation mode, because we expect them to be zero
48 #define _RPAGE_RPN0 0x01000
49 #define _RPAGE_RPN1 0x02000
50 #define _RPAGE_RPN44 0x0100000000000000UL
51 #define _RPAGE_RPN43 0x0080000000000000UL
52 #define _RPAGE_RPN42 0x0040000000000000UL
53 #define _RPAGE_RPN41 0x0020000000000000UL
55 /* Max physical address bit as per radix table */
56 #define _RPAGE_PA_MAX 57
59 * Max physical address bit we will use for now.
61 * This is mostly a hardware limitation and for now Power9 has
64 * This is different from the number of physical bit required to address
65 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
66 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
67 * number of sections we can support (SECTIONS_SHIFT).
69 * This is different from Radix page table limitation above and
70 * should always be less than that. The limit is done such that
71 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
72 * for hash linux page table specific bits.
74 * In order to be compatible with future hardware generations we keep
75 * some offsets and limit this for now to 53
77 #define _PAGE_PA_MAX 53
79 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
80 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
82 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
83 * Instead of fixing all of them, add an alternate define which
84 * maps CI pte mapping.
86 #define _PAGE_NO_CACHE _PAGE_TOLERANT
88 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
89 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
90 * and every thing below PAGE_SHIFT;
92 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
94 * set of bits not changed in pmd_modify. Even though we have hash specific bits
95 * in here, on radix we expect them to be zero.
97 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
98 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
101 * user access blocked by key
103 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
104 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
105 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
106 _PAGE_RW | _PAGE_EXEC)
108 * No page size encoding in the linux PTE
110 #define _PAGE_PSIZE 0
112 * _PAGE_CHG_MASK masks of bits that are to be preserved across
115 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
116 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
119 * Mask of bits returned by pte_pgprot()
121 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
122 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
123 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
126 * We define 2 sets of base prot bits, one for basic pages (ie,
127 * cacheable kernel and user pages) and one for non cacheable
128 * pages. We always set _PAGE_COHERENT when SMP is enabled or
129 * the processor might need it for DMA coherency.
131 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
132 #define _PAGE_BASE (_PAGE_BASE_NC)
134 /* Permission masks used to generate the __P and __S table,
136 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
138 * Write permissions imply read permissions for now (we could make write-only
139 * pages on BookE but we don't bother for now). Execute permission control is
140 * possible on platforms that define _PAGE_EXEC
142 * Note due to the way vm flags are laid out, the bits are XWR
144 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
145 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
146 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
147 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
148 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
149 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
150 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
152 #define __P000 PAGE_NONE
153 #define __P001 PAGE_READONLY
154 #define __P010 PAGE_COPY
155 #define __P011 PAGE_COPY
156 #define __P100 PAGE_READONLY_X
157 #define __P101 PAGE_READONLY_X
158 #define __P110 PAGE_COPY_X
159 #define __P111 PAGE_COPY_X
161 #define __S000 PAGE_NONE
162 #define __S001 PAGE_READONLY
163 #define __S010 PAGE_SHARED
164 #define __S011 PAGE_SHARED
165 #define __S100 PAGE_READONLY_X
166 #define __S101 PAGE_READONLY_X
167 #define __S110 PAGE_SHARED_X
168 #define __S111 PAGE_SHARED_X
170 /* Permission masks used for kernel mappings */
171 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
172 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
174 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
175 _PAGE_NON_IDEMPOTENT)
176 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
177 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
178 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
181 * Protection used for kernel text. We want the debuggers to be able to
182 * set breakpoints anywhere, so don't write protect the kernel text
183 * on platforms where such control is possible.
185 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
186 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
187 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
189 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
192 /* Make modules code happy. We don't set RO yet */
193 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
194 #define PAGE_AGP (PAGE_KERNEL_NC)
200 extern unsigned long __pte_index_size
;
201 extern unsigned long __pmd_index_size
;
202 extern unsigned long __pud_index_size
;
203 extern unsigned long __pgd_index_size
;
204 extern unsigned long __pmd_cache_index
;
205 #define PTE_INDEX_SIZE __pte_index_size
206 #define PMD_INDEX_SIZE __pmd_index_size
207 #define PUD_INDEX_SIZE __pud_index_size
208 #define PGD_INDEX_SIZE __pgd_index_size
209 #define PMD_CACHE_INDEX __pmd_cache_index
211 * Because of use of pte fragments and THP, size of page table
212 * are not always derived out of index size above.
214 extern unsigned long __pte_table_size
;
215 extern unsigned long __pmd_table_size
;
216 extern unsigned long __pud_table_size
;
217 extern unsigned long __pgd_table_size
;
218 #define PTE_TABLE_SIZE __pte_table_size
219 #define PMD_TABLE_SIZE __pmd_table_size
220 #define PUD_TABLE_SIZE __pud_table_size
221 #define PGD_TABLE_SIZE __pgd_table_size
223 extern unsigned long __pmd_val_bits
;
224 extern unsigned long __pud_val_bits
;
225 extern unsigned long __pgd_val_bits
;
226 #define PMD_VAL_BITS __pmd_val_bits
227 #define PUD_VAL_BITS __pud_val_bits
228 #define PGD_VAL_BITS __pgd_val_bits
230 extern unsigned long __pte_frag_nr
;
231 #define PTE_FRAG_NR __pte_frag_nr
232 extern unsigned long __pte_frag_size_shift
;
233 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
234 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
236 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
237 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
238 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
239 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
241 /* PMD_SHIFT determines what a second-level page table entry can map */
242 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
243 #define PMD_SIZE (1UL << PMD_SHIFT)
244 #define PMD_MASK (~(PMD_SIZE-1))
246 /* PUD_SHIFT determines what a third-level page table entry can map */
247 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
248 #define PUD_SIZE (1UL << PUD_SHIFT)
249 #define PUD_MASK (~(PUD_SIZE-1))
251 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
252 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
253 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
254 #define PGDIR_MASK (~(PGDIR_SIZE-1))
256 /* Bits to mask out from a PMD to get to the PTE page */
257 #define PMD_MASKED_BITS 0xc0000000000000ffUL
258 /* Bits to mask out from a PUD to get to the PMD page */
259 #define PUD_MASKED_BITS 0xc0000000000000ffUL
260 /* Bits to mask out from a PGD to get to the PUD page */
261 #define PGD_MASKED_BITS 0xc0000000000000ffUL
263 extern unsigned long __vmalloc_start
;
264 extern unsigned long __vmalloc_end
;
265 #define VMALLOC_START __vmalloc_start
266 #define VMALLOC_END __vmalloc_end
268 extern unsigned long __kernel_virt_start
;
269 extern unsigned long __kernel_virt_size
;
270 #define KERN_VIRT_START __kernel_virt_start
271 #define KERN_VIRT_SIZE __kernel_virt_size
272 extern struct page
*vmemmap
;
273 extern unsigned long ioremap_bot
;
274 extern unsigned long pci_io_base
;
275 #endif /* __ASSEMBLY__ */
277 #include <asm/book3s/64/hash.h>
278 #include <asm/book3s/64/radix.h>
280 #ifdef CONFIG_PPC_64K_PAGES
281 #include <asm/book3s/64/pgtable-64k.h>
283 #include <asm/book3s/64/pgtable-4k.h>
286 #include <asm/barrier.h>
288 * The second half of the kernel virtual space is used for IO mappings,
289 * it's itself carved into the PIO region (ISA and PHB IO space) and
292 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
293 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
294 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
296 #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
297 #define FULL_IO_SIZE 0x80000000ul
298 #define ISA_IO_BASE (KERN_IO_START)
299 #define ISA_IO_END (KERN_IO_START + 0x10000ul)
300 #define PHB_IO_BASE (ISA_IO_END)
301 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
302 #define IOREMAP_BASE (PHB_IO_END)
303 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
305 /* Advertise special mapping type for AGP */
306 #define HAVE_PAGE_AGP
308 /* Advertise support for _PAGE_SPECIAL */
309 #define __HAVE_ARCH_PTE_SPECIAL
314 * This is the default implementation of various PTE accessors, it's
315 * used in all cases except Book3S with 64K pages where we have a
316 * concept of sub-pages
320 #define __real_pte(e,p) ((real_pte_t){(e)})
321 #define __rpte_to_pte(r) ((r).pte)
322 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
324 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
327 shift = mmu_psize_defs[psize].shift; \
329 #define pte_iterate_hashed_end() } while(0)
332 * We expect this to be called only for user addresses or kernel virtual
333 * addresses other than the linear mapping.
335 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
337 #endif /* __real_pte */
339 static inline unsigned long pte_update(struct mm_struct
*mm
, unsigned long addr
,
340 pte_t
*ptep
, unsigned long clr
,
341 unsigned long set
, int huge
)
344 return radix__pte_update(mm
, addr
, ptep
, clr
, set
, huge
);
345 return hash__pte_update(mm
, addr
, ptep
, clr
, set
, huge
);
348 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
349 * We currently remove entries from the hashtable regardless of whether
350 * the entry was young or dirty.
352 * We should be more intelligent about this but for the moment we override
353 * these functions and force a tlb flush unconditionally
354 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
355 * function for both hash and radix.
357 static inline int __ptep_test_and_clear_young(struct mm_struct
*mm
,
358 unsigned long addr
, pte_t
*ptep
)
362 if ((pte_raw(*ptep
) & cpu_to_be64(_PAGE_ACCESSED
| H_PAGE_HASHPTE
)) == 0)
364 old
= pte_update(mm
, addr
, ptep
, _PAGE_ACCESSED
, 0, 0);
365 return (old
& _PAGE_ACCESSED
) != 0;
368 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
369 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
372 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
376 static inline int __pte_write(pte_t pte
)
378 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_WRITE
));
381 #ifdef CONFIG_NUMA_BALANCING
382 #define pte_savedwrite pte_savedwrite
383 static inline bool pte_savedwrite(pte_t pte
)
386 * Saved write ptes are prot none ptes that doesn't have
387 * privileged bit sit. We mark prot none as one which has
388 * present and pviliged bit set and RWX cleared. To mark
389 * protnone which used to have _PAGE_WRITE set we clear
390 * the privileged bit.
392 return !(pte_raw(pte
) & cpu_to_be64(_PAGE_RWX
| _PAGE_PRIVILEGED
));
395 #define pte_savedwrite pte_savedwrite
396 static inline bool pte_savedwrite(pte_t pte
)
402 static inline int pte_write(pte_t pte
)
404 return __pte_write(pte
) || pte_savedwrite(pte
);
407 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
408 static inline void ptep_set_wrprotect(struct mm_struct
*mm
, unsigned long addr
,
411 if (__pte_write(*ptep
))
412 pte_update(mm
, addr
, ptep
, _PAGE_WRITE
, 0, 0);
413 else if (unlikely(pte_savedwrite(*ptep
)))
414 pte_update(mm
, addr
, ptep
, 0, _PAGE_PRIVILEGED
, 0);
417 static inline void huge_ptep_set_wrprotect(struct mm_struct
*mm
,
418 unsigned long addr
, pte_t
*ptep
)
421 * We should not find protnone for hugetlb, but this complete the
424 if (__pte_write(*ptep
))
425 pte_update(mm
, addr
, ptep
, _PAGE_WRITE
, 0, 1);
426 else if (unlikely(pte_savedwrite(*ptep
)))
427 pte_update(mm
, addr
, ptep
, 0, _PAGE_PRIVILEGED
, 1);
430 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
431 static inline pte_t
ptep_get_and_clear(struct mm_struct
*mm
,
432 unsigned long addr
, pte_t
*ptep
)
434 unsigned long old
= pte_update(mm
, addr
, ptep
, ~0UL, 0, 0);
438 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
439 static inline pte_t
ptep_get_and_clear_full(struct mm_struct
*mm
,
441 pte_t
*ptep
, int full
)
443 if (full
&& radix_enabled()) {
445 * Let's skip the DD1 style pte update here. We know that
446 * this is a full mm pte clear and hence can be sure there is
447 * no parallel set_pte.
449 return radix__ptep_get_and_clear_full(mm
, addr
, ptep
, full
);
451 return ptep_get_and_clear(mm
, addr
, ptep
);
455 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
,
458 pte_update(mm
, addr
, ptep
, ~0UL, 0, 0);
461 static inline int pte_dirty(pte_t pte
)
463 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_DIRTY
));
466 static inline int pte_young(pte_t pte
)
468 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_ACCESSED
));
471 static inline int pte_special(pte_t pte
)
473 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_SPECIAL
));
476 static inline pgprot_t
pte_pgprot(pte_t pte
) { return __pgprot(pte_val(pte
) & PAGE_PROT_BITS
); }
478 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
479 static inline bool pte_soft_dirty(pte_t pte
)
481 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_SOFT_DIRTY
));
484 static inline pte_t
pte_mksoft_dirty(pte_t pte
)
486 return __pte(pte_val(pte
) | _PAGE_SOFT_DIRTY
);
489 static inline pte_t
pte_clear_soft_dirty(pte_t pte
)
491 return __pte(pte_val(pte
) & ~_PAGE_SOFT_DIRTY
);
493 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
495 #ifdef CONFIG_NUMA_BALANCING
496 static inline int pte_protnone(pte_t pte
)
498 return (pte_raw(pte
) & cpu_to_be64(_PAGE_PRESENT
| _PAGE_PTE
| _PAGE_RWX
)) ==
499 cpu_to_be64(_PAGE_PRESENT
| _PAGE_PTE
);
502 #define pte_mk_savedwrite pte_mk_savedwrite
503 static inline pte_t
pte_mk_savedwrite(pte_t pte
)
506 * Used by Autonuma subsystem to preserve the write bit
507 * while marking the pte PROT_NONE. Only allow this
510 VM_BUG_ON((pte_raw(pte
) & cpu_to_be64(_PAGE_PRESENT
| _PAGE_RWX
| _PAGE_PRIVILEGED
)) !=
511 cpu_to_be64(_PAGE_PRESENT
| _PAGE_PRIVILEGED
));
512 return __pte(pte_val(pte
) & ~_PAGE_PRIVILEGED
);
515 #define pte_clear_savedwrite pte_clear_savedwrite
516 static inline pte_t
pte_clear_savedwrite(pte_t pte
)
519 * Used by KSM subsystem to make a protnone pte readonly.
521 VM_BUG_ON(!pte_protnone(pte
));
522 return __pte(pte_val(pte
) | _PAGE_PRIVILEGED
);
525 #define pte_clear_savedwrite pte_clear_savedwrite
526 static inline pte_t
pte_clear_savedwrite(pte_t pte
)
529 return __pte(pte_val(pte
) & ~_PAGE_WRITE
);
531 #endif /* CONFIG_NUMA_BALANCING */
533 static inline int pte_present(pte_t pte
)
535 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_PRESENT
));
538 * Conversion functions: convert a page and protection to a page entry,
539 * and a page entry and page directory to the page they refer to.
541 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
544 static inline pte_t
pfn_pte(unsigned long pfn
, pgprot_t pgprot
)
546 return __pte((((pte_basic_t
)(pfn
) << PAGE_SHIFT
) & PTE_RPN_MASK
) |
550 static inline unsigned long pte_pfn(pte_t pte
)
552 return (pte_val(pte
) & PTE_RPN_MASK
) >> PAGE_SHIFT
;
555 /* Generic modifiers for PTE bits */
556 static inline pte_t
pte_wrprotect(pte_t pte
)
558 if (unlikely(pte_savedwrite(pte
)))
559 return pte_clear_savedwrite(pte
);
560 return __pte(pte_val(pte
) & ~_PAGE_WRITE
);
563 static inline pte_t
pte_mkclean(pte_t pte
)
565 return __pte(pte_val(pte
) & ~_PAGE_DIRTY
);
568 static inline pte_t
pte_mkold(pte_t pte
)
570 return __pte(pte_val(pte
) & ~_PAGE_ACCESSED
);
573 static inline pte_t
pte_mkwrite(pte_t pte
)
576 * write implies read, hence set both
578 return __pte(pte_val(pte
) | _PAGE_RW
);
581 static inline pte_t
pte_mkdirty(pte_t pte
)
583 return __pte(pte_val(pte
) | _PAGE_DIRTY
| _PAGE_SOFT_DIRTY
);
586 static inline pte_t
pte_mkyoung(pte_t pte
)
588 return __pte(pte_val(pte
) | _PAGE_ACCESSED
);
591 static inline pte_t
pte_mkspecial(pte_t pte
)
593 return __pte(pte_val(pte
) | _PAGE_SPECIAL
);
596 static inline pte_t
pte_mkhuge(pte_t pte
)
601 static inline pte_t
pte_modify(pte_t pte
, pgprot_t newprot
)
603 /* FIXME!! check whether this need to be a conditional */
604 return __pte((pte_val(pte
) & _PAGE_CHG_MASK
) | pgprot_val(newprot
));
607 static inline bool pte_user(pte_t pte
)
609 return !(pte_raw(pte
) & cpu_to_be64(_PAGE_PRIVILEGED
));
612 /* Encode and de-code a swap entry */
613 #define MAX_SWAPFILES_CHECK() do { \
614 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
616 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
617 * We filter HPTEFLAGS on set_pte. \
619 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
620 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
623 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
625 #define SWP_TYPE_BITS 5
626 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
627 & ((1UL << SWP_TYPE_BITS) - 1))
628 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
629 #define __swp_entry(type, offset) ((swp_entry_t) { \
630 ((type) << _PAGE_BIT_SWAP_TYPE) \
631 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
633 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
634 * swap type and offset we get from swap and convert that to pte to find a
635 * matching pte in linux page table.
636 * Clear bits not found in swap entries here.
638 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
639 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
641 #ifdef CONFIG_MEM_SOFT_DIRTY
642 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
644 #define _PAGE_SWP_SOFT_DIRTY 0UL
645 #endif /* CONFIG_MEM_SOFT_DIRTY */
647 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
648 static inline pte_t
pte_swp_mksoft_dirty(pte_t pte
)
650 return __pte(pte_val(pte
) | _PAGE_SWP_SOFT_DIRTY
);
653 static inline bool pte_swp_soft_dirty(pte_t pte
)
655 return !!(pte_raw(pte
) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY
));
658 static inline pte_t
pte_swp_clear_soft_dirty(pte_t pte
)
660 return __pte(pte_val(pte
) & ~_PAGE_SWP_SOFT_DIRTY
);
662 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
664 static inline bool check_pte_access(unsigned long access
, unsigned long ptev
)
667 * This check for _PAGE_RWX and _PAGE_PRESENT bits
672 * This check for access to privilege space
674 if ((access
& _PAGE_PRIVILEGED
) != (ptev
& _PAGE_PRIVILEGED
))
680 * Generic functions with hash/radix callbacks
683 static inline void __ptep_set_access_flags(struct mm_struct
*mm
,
684 pte_t
*ptep
, pte_t entry
,
685 unsigned long address
)
688 return radix__ptep_set_access_flags(mm
, ptep
, entry
, address
);
689 return hash__ptep_set_access_flags(ptep
, entry
);
692 #define __HAVE_ARCH_PTE_SAME
693 static inline int pte_same(pte_t pte_a
, pte_t pte_b
)
696 return radix__pte_same(pte_a
, pte_b
);
697 return hash__pte_same(pte_a
, pte_b
);
700 static inline int pte_none(pte_t pte
)
703 return radix__pte_none(pte
);
704 return hash__pte_none(pte
);
707 static inline void __set_pte_at(struct mm_struct
*mm
, unsigned long addr
,
708 pte_t
*ptep
, pte_t pte
, int percpu
)
711 return radix__set_pte_at(mm
, addr
, ptep
, pte
, percpu
);
712 return hash__set_pte_at(mm
, addr
, ptep
, pte
, percpu
);
715 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
717 #define pgprot_noncached pgprot_noncached
718 static inline pgprot_t
pgprot_noncached(pgprot_t prot
)
720 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
) |
721 _PAGE_NON_IDEMPOTENT
);
724 #define pgprot_noncached_wc pgprot_noncached_wc
725 static inline pgprot_t
pgprot_noncached_wc(pgprot_t prot
)
727 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
) |
731 #define pgprot_cached pgprot_cached
732 static inline pgprot_t
pgprot_cached(pgprot_t prot
)
734 return __pgprot((pgprot_val(prot
) & ~_PAGE_CACHE_CTL
));
737 #define pgprot_writecombine pgprot_writecombine
738 static inline pgprot_t
pgprot_writecombine(pgprot_t prot
)
740 return pgprot_noncached_wc(prot
);
743 * check a pte mapping have cache inhibited property
745 static inline bool pte_ci(pte_t pte
)
747 unsigned long pte_v
= pte_val(pte
);
749 if (((pte_v
& _PAGE_CACHE_CTL
) == _PAGE_TOLERANT
) ||
750 ((pte_v
& _PAGE_CACHE_CTL
) == _PAGE_NON_IDEMPOTENT
))
755 static inline void pmd_set(pmd_t
*pmdp
, unsigned long val
)
760 static inline void pmd_clear(pmd_t
*pmdp
)
765 static inline int pmd_none(pmd_t pmd
)
767 return !pmd_raw(pmd
);
770 static inline int pmd_present(pmd_t pmd
)
773 return !pmd_none(pmd
);
776 static inline int pmd_bad(pmd_t pmd
)
779 return radix__pmd_bad(pmd
);
780 return hash__pmd_bad(pmd
);
783 static inline void pud_set(pud_t
*pudp
, unsigned long val
)
788 static inline void pud_clear(pud_t
*pudp
)
793 static inline int pud_none(pud_t pud
)
795 return !pud_raw(pud
);
798 static inline int pud_present(pud_t pud
)
800 return !pud_none(pud
);
803 extern struct page
*pud_page(pud_t pud
);
804 extern struct page
*pmd_page(pmd_t pmd
);
805 static inline pte_t
pud_pte(pud_t pud
)
807 return __pte_raw(pud_raw(pud
));
810 static inline pud_t
pte_pud(pte_t pte
)
812 return __pud_raw(pte_raw(pte
));
814 #define pud_write(pud) pte_write(pud_pte(pud))
816 static inline int pud_bad(pud_t pud
)
819 return radix__pud_bad(pud
);
820 return hash__pud_bad(pud
);
824 #define pgd_write(pgd) pte_write(pgd_pte(pgd))
825 static inline void pgd_set(pgd_t
*pgdp
, unsigned long val
)
830 static inline void pgd_clear(pgd_t
*pgdp
)
835 static inline int pgd_none(pgd_t pgd
)
837 return !pgd_raw(pgd
);
840 static inline int pgd_present(pgd_t pgd
)
842 return !pgd_none(pgd
);
845 static inline pte_t
pgd_pte(pgd_t pgd
)
847 return __pte_raw(pgd_raw(pgd
));
850 static inline pgd_t
pte_pgd(pte_t pte
)
852 return __pgd_raw(pte_raw(pte
));
855 static inline int pgd_bad(pgd_t pgd
)
858 return radix__pgd_bad(pgd
);
859 return hash__pgd_bad(pgd
);
862 extern struct page
*pgd_page(pgd_t pgd
);
864 /* Pointers in the page table tree are physical addresses */
865 #define __pgtable_ptr_val(ptr) __pa(ptr)
867 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
868 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
869 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
871 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
872 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
873 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
874 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
877 * Find an entry in a page-table-directory. We combine the address region
878 * (the high order N bits) and the pgd portion of the address.
881 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
883 #define pud_offset(pgdp, addr) \
884 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
885 #define pmd_offset(pudp,addr) \
886 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
887 #define pte_offset_kernel(dir,addr) \
888 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
890 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
891 #define pte_unmap(pte) do { } while(0)
893 /* to find an entry in a kernel page-table-directory */
894 /* This now only contains the vmalloc pages */
895 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
897 #define pte_ERROR(e) \
898 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
899 #define pmd_ERROR(e) \
900 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
901 #define pud_ERROR(e) \
902 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
903 #define pgd_ERROR(e) \
904 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
906 static inline int map_kernel_page(unsigned long ea
, unsigned long pa
,
909 if (radix_enabled()) {
910 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
911 unsigned long page_size
= 1 << mmu_psize_defs
[mmu_io_psize
].shift
;
912 WARN((page_size
!= PAGE_SIZE
), "I/O page size != PAGE_SIZE");
914 return radix__map_kernel_page(ea
, pa
, __pgprot(flags
), PAGE_SIZE
);
916 return hash__map_kernel_page(ea
, pa
, flags
);
919 static inline int __meminit
vmemmap_create_mapping(unsigned long start
,
920 unsigned long page_size
,
924 return radix__vmemmap_create_mapping(start
, page_size
, phys
);
925 return hash__vmemmap_create_mapping(start
, page_size
, phys
);
928 #ifdef CONFIG_MEMORY_HOTPLUG
929 static inline void vmemmap_remove_mapping(unsigned long start
,
930 unsigned long page_size
)
933 return radix__vmemmap_remove_mapping(start
, page_size
);
934 return hash__vmemmap_remove_mapping(start
, page_size
);
937 struct page
*realmode_pfn_to_page(unsigned long pfn
);
939 static inline pte_t
pmd_pte(pmd_t pmd
)
941 return __pte_raw(pmd_raw(pmd
));
944 static inline pmd_t
pte_pmd(pte_t pte
)
946 return __pmd_raw(pte_raw(pte
));
949 static inline pte_t
*pmdp_ptep(pmd_t
*pmd
)
953 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
954 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
955 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
956 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
957 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
958 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
959 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
960 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
961 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
962 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
963 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
965 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
966 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
967 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
968 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
969 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
971 #ifdef CONFIG_NUMA_BALANCING
972 static inline int pmd_protnone(pmd_t pmd
)
974 return pte_protnone(pmd_pte(pmd
));
976 #endif /* CONFIG_NUMA_BALANCING */
978 #define __HAVE_ARCH_PMD_WRITE
979 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
980 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
981 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
983 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
984 extern pmd_t
pfn_pmd(unsigned long pfn
, pgprot_t pgprot
);
985 extern pmd_t
mk_pmd(struct page
*page
, pgprot_t pgprot
);
986 extern pmd_t
pmd_modify(pmd_t pmd
, pgprot_t newprot
);
987 extern void set_pmd_at(struct mm_struct
*mm
, unsigned long addr
,
988 pmd_t
*pmdp
, pmd_t pmd
);
989 extern void update_mmu_cache_pmd(struct vm_area_struct
*vma
, unsigned long addr
,
991 extern int hash__has_transparent_hugepage(void);
992 static inline int has_transparent_hugepage(void)
995 return radix__has_transparent_hugepage();
996 return hash__has_transparent_hugepage();
998 #define has_transparent_hugepage has_transparent_hugepage
1000 static inline unsigned long
1001 pmd_hugepage_update(struct mm_struct
*mm
, unsigned long addr
, pmd_t
*pmdp
,
1002 unsigned long clr
, unsigned long set
)
1004 if (radix_enabled())
1005 return radix__pmd_hugepage_update(mm
, addr
, pmdp
, clr
, set
);
1006 return hash__pmd_hugepage_update(mm
, addr
, pmdp
, clr
, set
);
1009 static inline int pmd_large(pmd_t pmd
)
1011 return !!(pmd_raw(pmd
) & cpu_to_be64(_PAGE_PTE
));
1014 static inline pmd_t
pmd_mknotpresent(pmd_t pmd
)
1016 return __pmd(pmd_val(pmd
) & ~_PAGE_PRESENT
);
1019 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1020 * the below will work for radix too
1022 static inline int __pmdp_test_and_clear_young(struct mm_struct
*mm
,
1023 unsigned long addr
, pmd_t
*pmdp
)
1027 if ((pmd_raw(*pmdp
) & cpu_to_be64(_PAGE_ACCESSED
| H_PAGE_HASHPTE
)) == 0)
1029 old
= pmd_hugepage_update(mm
, addr
, pmdp
, _PAGE_ACCESSED
, 0);
1030 return ((old
& _PAGE_ACCESSED
) != 0);
1033 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1034 static inline void pmdp_set_wrprotect(struct mm_struct
*mm
, unsigned long addr
,
1037 if (__pmd_write((*pmdp
)))
1038 pmd_hugepage_update(mm
, addr
, pmdp
, _PAGE_WRITE
, 0);
1039 else if (unlikely(pmd_savedwrite(*pmdp
)))
1040 pmd_hugepage_update(mm
, addr
, pmdp
, 0, _PAGE_PRIVILEGED
);
1043 static inline int pmd_trans_huge(pmd_t pmd
)
1045 if (radix_enabled())
1046 return radix__pmd_trans_huge(pmd
);
1047 return hash__pmd_trans_huge(pmd
);
1050 #define __HAVE_ARCH_PMD_SAME
1051 static inline int pmd_same(pmd_t pmd_a
, pmd_t pmd_b
)
1053 if (radix_enabled())
1054 return radix__pmd_same(pmd_a
, pmd_b
);
1055 return hash__pmd_same(pmd_a
, pmd_b
);
1058 static inline pmd_t
pmd_mkhuge(pmd_t pmd
)
1060 if (radix_enabled())
1061 return radix__pmd_mkhuge(pmd
);
1062 return hash__pmd_mkhuge(pmd
);
1065 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1066 extern int pmdp_set_access_flags(struct vm_area_struct
*vma
,
1067 unsigned long address
, pmd_t
*pmdp
,
1068 pmd_t entry
, int dirty
);
1070 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1071 extern int pmdp_test_and_clear_young(struct vm_area_struct
*vma
,
1072 unsigned long address
, pmd_t
*pmdp
);
1074 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1075 static inline pmd_t
pmdp_huge_get_and_clear(struct mm_struct
*mm
,
1076 unsigned long addr
, pmd_t
*pmdp
)
1078 if (radix_enabled())
1079 return radix__pmdp_huge_get_and_clear(mm
, addr
, pmdp
);
1080 return hash__pmdp_huge_get_and_clear(mm
, addr
, pmdp
);
1083 static inline pmd_t
pmdp_collapse_flush(struct vm_area_struct
*vma
,
1084 unsigned long address
, pmd_t
*pmdp
)
1086 if (radix_enabled())
1087 return radix__pmdp_collapse_flush(vma
, address
, pmdp
);
1088 return hash__pmdp_collapse_flush(vma
, address
, pmdp
);
1090 #define pmdp_collapse_flush pmdp_collapse_flush
1092 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1093 static inline void pgtable_trans_huge_deposit(struct mm_struct
*mm
,
1094 pmd_t
*pmdp
, pgtable_t pgtable
)
1096 if (radix_enabled())
1097 return radix__pgtable_trans_huge_deposit(mm
, pmdp
, pgtable
);
1098 return hash__pgtable_trans_huge_deposit(mm
, pmdp
, pgtable
);
1101 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1102 static inline pgtable_t
pgtable_trans_huge_withdraw(struct mm_struct
*mm
,
1105 if (radix_enabled())
1106 return radix__pgtable_trans_huge_withdraw(mm
, pmdp
);
1107 return hash__pgtable_trans_huge_withdraw(mm
, pmdp
);
1110 #define __HAVE_ARCH_PMDP_INVALIDATE
1111 extern void pmdp_invalidate(struct vm_area_struct
*vma
, unsigned long address
,
1114 #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
1115 static inline void pmdp_huge_split_prepare(struct vm_area_struct
*vma
,
1116 unsigned long address
, pmd_t
*pmdp
)
1118 if (radix_enabled())
1119 return radix__pmdp_huge_split_prepare(vma
, address
, pmdp
);
1120 return hash__pmdp_huge_split_prepare(vma
, address
, pmdp
);
1123 #define pmd_move_must_withdraw pmd_move_must_withdraw
1125 static inline int pmd_move_must_withdraw(struct spinlock
*new_pmd_ptl
,
1126 struct spinlock
*old_pmd_ptl
,
1127 struct vm_area_struct
*vma
)
1129 if (radix_enabled())
1132 * Archs like ppc64 use pgtable to store per pmd
1133 * specific information. So when we switch the pmd,
1134 * we should also withdraw and deposit the pgtable
1140 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1141 static inline bool arch_needs_pgtable_deposit(void)
1143 if (radix_enabled())
1148 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1149 #endif /* __ASSEMBLY__ */
1150 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */