arch/powerpc/include/asm/book3s/64/radix.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H
   3 #define _ASM_POWERPC_PGTABLE_RADIX_H
   4
   5 #include <asm/asm-const.h>
   6
   7 #ifndef __ASSEMBLY__
   8 #include <asm/cmpxchg.h>
   9 #endif
  10
  11 #ifdef CONFIG_PPC_64K_PAGES
  12 #include <asm/book3s/64/radix-64k.h>
  13 #else
  14 #include <asm/book3s/64/radix-4k.h>
  15 #endif
  16
  17 #ifndef __ASSEMBLY__
  18 #include <asm/book3s/64/tlbflush-radix.h>
  19 #include <asm/cpu_has_feature.h>
  20 #endif
  21
  22 /* An empty PTE can still have a R or C writeback */
  23 #define RADIX_PTE_NONE_MASK             (_PAGE_DIRTY | _PAGE_ACCESSED)
  24
  25 /* Bits to set in a RPMD/RPUD/RPGD */
  26 #define RADIX_PMD_VAL_BITS              (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
  27 #define RADIX_PUD_VAL_BITS              (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
  28 #define RADIX_PGD_VAL_BITS              (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
  29
  30 /* Don't have anything in the reserved bits and leaf bits */
  31 #define RADIX_PMD_BAD_BITS              0x60000000000000e0UL
  32 #define RADIX_PUD_BAD_BITS              0x60000000000000e0UL
  33 #define RADIX_PGD_BAD_BITS              0x60000000000000e0UL
  34
  35 #define RADIX_PMD_SHIFT         (PAGE_SHIFT + RADIX_PTE_INDEX_SIZE)
  36 #define RADIX_PUD_SHIFT         (RADIX_PMD_SHIFT + RADIX_PMD_INDEX_SIZE)
  37 #define RADIX_PGD_SHIFT         (RADIX_PUD_SHIFT + RADIX_PUD_INDEX_SIZE)
  38 /*
  39  * Size of EA range mapped by our pagetables.
  40  */
  41 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
  42                               RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
  43 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
  44
  45 /*
  46  * We support 52 bit address space, Use top bit for kernel
  47  * virtual mapping. Also make sure kernel fit in the top
  48  * quadrant.
  49  *
  50  *           +------------------+
  51  *           +------------------+  Kernel virtual map (0xc008000000000000)
  52  *           |                  |
  53  *           |                  |
  54  *           |                  |
  55  * 0b11......+------------------+  Kernel linear map (0xc....)
  56  *           |                  |
  57  *           |     2 quadrant   |
  58  *           |                  |
  59  * 0b10......+------------------+
  60  *           |                  |
  61  *           |    1 quadrant    |
  62  *           |                  |
  63  * 0b01......+------------------+
  64  *           |                  |
  65  *           |    0 quadrant    |
  66  *           |                  |
  67  * 0b00......+------------------+
  68  *
  69  *
  70  * 3rd quadrant expanded:
  71  * +------------------------------+
  72  * |                              |
  73  * |                              |
  74  * |                              |
  75  * +------------------------------+  Kernel vmemmap end (0xc010000000000000)
  76  * |                              |
  77  * |           512TB              |
  78  * |                              |
  79  * +------------------------------+  Kernel IO map end/vmemap start
  80  * |                              |
  81  * |           512TB              |
  82  * |                              |
  83  * +------------------------------+  Kernel vmap end/ IO map start
  84  * |                              |
  85  * |           512TB              |
  86  * |                              |
  87  * +------------------------------+  Kernel virt start (0xc008000000000000)
  88  * |                              |
  89  * |                              |
  90  * |                              |
  91  * +------------------------------+  Kernel linear (0xc.....)
  92  */
  93
  94 #define RADIX_KERN_VIRT_START   ASM_CONST(0xc008000000000000)
  95 /*
  96  * 49 =  MAX_EA_BITS_PER_CONTEXT (hash specific). To make sure we pick
  97  * the same value as hash.
  98  */
  99 #define RADIX_KERN_MAP_SIZE     (1UL << 49)
 100
 101 #define RADIX_VMALLOC_START     RADIX_KERN_VIRT_START
 102 #define RADIX_VMALLOC_SIZE      RADIX_KERN_MAP_SIZE
 103 #define RADIX_VMALLOC_END       (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
 104
 105 #define RADIX_KERN_IO_START     RADIX_VMALLOC_END
 106 #define RADIX_KERN_IO_SIZE      RADIX_KERN_MAP_SIZE
 107 #define RADIX_KERN_IO_END       (RADIX_KERN_IO_START + RADIX_KERN_IO_SIZE)
 108
 109 #define RADIX_VMEMMAP_START     RADIX_KERN_IO_END
 110 #define RADIX_VMEMMAP_SIZE      RADIX_KERN_MAP_SIZE
 111 #define RADIX_VMEMMAP_END       (RADIX_VMEMMAP_START + RADIX_VMEMMAP_SIZE)
 112
 113 #ifndef __ASSEMBLY__
 114 #define RADIX_PTE_TABLE_SIZE    (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
 115 #define RADIX_PMD_TABLE_SIZE    (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
 116 #define RADIX_PUD_TABLE_SIZE    (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
 117 #define RADIX_PGD_TABLE_SIZE    (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
 118
 119 #ifdef CONFIG_STRICT_KERNEL_RWX
 120 extern void radix__mark_rodata_ro(void);
 121 extern void radix__mark_initmem_nx(void);
 122 #endif
 123
 124 extern void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
 125                                          pte_t entry, unsigned long address,
 126                                          int psize);
 127
 128 extern void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
 129                                            unsigned long addr, pte_t *ptep,
 130                                            pte_t old_pte, pte_t pte);
 131
 132 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
 133                                                unsigned long set)
 134 {
 135         __be64 old_be, tmp_be;
 136
 137         __asm__ __volatile__(
 138         "1:     ldarx   %0,0,%3         # pte_update\n"
 139         "       andc    %1,%0,%5        \n"
 140         "       or      %1,%1,%4        \n"
 141         "       stdcx.  %1,0,%3         \n"
 142         "       bne-    1b"
 143         : "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
 144         : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr))
 145         : "cc" );
 146
 147         return be64_to_cpu(old_be);
 148 }
 149
 150 static inline unsigned long radix__pte_update(struct mm_struct *mm,
 151                                         unsigned long addr,
 152                                         pte_t *ptep, unsigned long clr,
 153                                         unsigned long set,
 154                                         int huge)
 155 {
 156         unsigned long old_pte;
 157
 158         old_pte = __radix_pte_update(ptep, clr, set);
 159         if (!huge)
 160                 assert_pte_locked(mm, addr);
 161
 162         return old_pte;
 163 }
 164
 165 static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
 166                                                    unsigned long addr,
 167                                                    pte_t *ptep, int full)
 168 {
 169         unsigned long old_pte;
 170
 171         if (full) {
 172                 old_pte = pte_val(*ptep);
 173                 *ptep = __pte(0);
 174         } else
 175                 old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
 176
 177         return __pte(old_pte);
 178 }
 179
 180 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
 181 {
 182         return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
 183 }
 184
 185 static inline int radix__pte_none(pte_t pte)
 186 {
 187         return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
 188 }
 189
 190 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
 191                                  pte_t *ptep, pte_t pte, int percpu)
 192 {
 193         *ptep = pte;
 194
 195         /*
 196          * The architecture suggests a ptesync after setting the pte, which
 197          * orders the store that updates the pte with subsequent page table
 198          * walk accesses which may load the pte. Without this it may be
 199          * possible for a subsequent access to result in spurious fault.
 200          *
 201          * This is not necessary for correctness, because a spurious fault
 202          * is tolerated by the page fault handler, and this store will
 203          * eventually be seen. In testing, there was no noticable increase
 204          * in user faults on POWER9. Avoiding ptesync here is a significant
 205          * win for things like fork. If a future microarchitecture benefits
 206          * from ptesync, it should probably go into update_mmu_cache, rather
 207          * than set_pte_at (which is used to set ptes unrelated to faults).
 208          *
 209          * Spurious faults to vmalloc region are not tolerated, so there is
 210          * a ptesync in flush_cache_vmap.
 211          */
 212 }
 213
 214 static inline int radix__pmd_bad(pmd_t pmd)
 215 {
 216         return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
 217 }
 218
 219 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
 220 {
 221         return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
 222 }
 223
 224 static inline int radix__pud_bad(pud_t pud)
 225 {
 226         return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
 227 }
 228
 229
 230 static inline int radix__pgd_bad(pgd_t pgd)
 231 {
 232         return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
 233 }
 234
 235 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 236
 237 static inline int radix__pmd_trans_huge(pmd_t pmd)
 238 {
 239         return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE;
 240 }
 241
 242 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
 243 {
 244         return __pmd(pmd_val(pmd) | _PAGE_PTE);
 245 }
 246
 247 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
 248                                           pmd_t *pmdp, unsigned long clr,
 249                                           unsigned long set);
 250 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
 251                                   unsigned long address, pmd_t *pmdp);
 252 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
 253                                         pgtable_t pgtable);
 254 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
 255 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
 256                                       unsigned long addr, pmd_t *pmdp);
 257 static inline int radix__has_transparent_hugepage(void)
 258 {
 259         /* For radix 2M at PMD level means thp */
 260         if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
 261                 return 1;
 262         return 0;
 263 }
 264 #endif
 265
 266 extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
 267                                              unsigned long page_size,
 268                                              unsigned long phys);
 269 extern void radix__vmemmap_remove_mapping(unsigned long start,
 270                                     unsigned long page_size);
 271
 272 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
 273                                  pgprot_t flags, unsigned int psz);
 274
 275 static inline unsigned long radix__get_tree_size(void)
 276 {
 277         unsigned long rts_field;
 278         /*
 279          * We support 52 bits, hence:
 280          * bits 52 - 31 = 21, 0b10101
 281          * RTS encoding details
 282          * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
 283          * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
 284          */
 285         rts_field = (0x5UL << 5); /* 6 - 8 bits */
 286         rts_field |= (0x2UL << 61);
 287
 288         return rts_field;
 289 }
 290
 291 #ifdef CONFIG_MEMORY_HOTPLUG
 292 int radix__create_section_mapping(unsigned long start, unsigned long end, int nid);
 293 int radix__remove_section_mapping(unsigned long start, unsigned long end);
 294 #endif /* CONFIG_MEMORY_HOTPLUG */
 295 #endif /* __ASSEMBLY__ */
 296 #endif