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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/powerpc/include/asm/config_mpc85xx.h
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2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #include <fsl_ddrc_version.h>
23 #define CONFIG_SYS_FSL_DDR_BE
26 #define CONFIG_SYS_FSL_IFC_BE
27 #define CONFIG_SYS_FSL_SEC_BE
28 #define CONFIG_SYS_FSL_SFP_BE
29 #define CONFIG_SYS_FSL_SEC_MON_BE
31 /* Number of TLB CAM entries we have on FSL Book-E chips */
32 #if defined(CONFIG_E500MC)
33 #define CONFIG_SYS_NUM_TLBCAMS 64
34 #elif defined(CONFIG_E500)
35 #define CONFIG_SYS_NUM_TLBCAMS 16
38 #if defined(CONFIG_ARCH_MPC8536)
39 #define CONFIG_MAX_CPUS 1
40 #define CONFIG_SYS_FSL_NUM_LAWS 12
41 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
42 #define CONFIG_SYS_FSL_SEC_COMPAT 2
43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
44 #define CONFIG_SYS_FSL_ERRATUM_A004508
45 #define CONFIG_SYS_FSL_ERRATUM_A005125
47 #elif defined(CONFIG_ARCH_MPC8540)
48 #define CONFIG_MAX_CPUS 1
49 #define CONFIG_SYS_FSL_NUM_LAWS 8
50 #define CONFIG_SYS_FSL_DDRC_GEN1
51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
53 #elif defined(CONFIG_ARCH_MPC8541)
54 #define CONFIG_MAX_CPUS 1
55 #define CONFIG_SYS_FSL_NUM_LAWS 8
56 #define CONFIG_SYS_FSL_DDRC_GEN1
57 #define CONFIG_SYS_FSL_SEC_COMPAT 2
58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
60 #elif defined(CONFIG_ARCH_MPC8544)
61 #define CONFIG_MAX_CPUS 1
62 #define CONFIG_SYS_FSL_NUM_LAWS 10
63 #define CONFIG_SYS_FSL_DDRC_GEN2
64 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
65 #define CONFIG_SYS_FSL_SEC_COMPAT 2
66 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
67 #define CONFIG_SYS_FSL_ERRATUM_A005125
69 #elif defined(CONFIG_ARCH_MPC8548)
70 #define CONFIG_MAX_CPUS 1
71 #define CONFIG_SYS_FSL_NUM_LAWS 10
72 #define CONFIG_SYS_FSL_DDRC_GEN2
73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
74 #define CONFIG_SYS_FSL_SEC_COMPAT 2
75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
82 #define CONFIG_SYS_FSL_RMU
83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
84 #define CONFIG_SYS_FSL_ERRATUM_A005125
85 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
86 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
88 #elif defined(CONFIG_ARCH_MPC8555)
89 #define CONFIG_MAX_CPUS 1
90 #define CONFIG_SYS_FSL_NUM_LAWS 8
91 #define CONFIG_SYS_FSL_DDRC_GEN1
92 #define CONFIG_SYS_FSL_SEC_COMPAT 2
93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
95 #elif defined(CONFIG_ARCH_MPC8560)
96 #define CONFIG_MAX_CPUS 1
97 #define CONFIG_SYS_FSL_NUM_LAWS 8
98 #define CONFIG_SYS_FSL_DDRC_GEN1
99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
101 #elif defined(CONFIG_ARCH_MPC8568)
102 #define CONFIG_MAX_CPUS 1
103 #define CONFIG_SYS_FSL_NUM_LAWS 10
104 #define CONFIG_SYS_FSL_DDRC_GEN2
105 #define CONFIG_SYS_FSL_SEC_COMPAT 2
106 #define QE_MURAM_SIZE 0x10000UL
107 #define MAX_QE_RISC 2
108 #define QE_NUM_OF_SNUM 28
109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
113 #define CONFIG_SYS_FSL_RMU
114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
116 #elif defined(CONFIG_ARCH_MPC8569)
117 #define CONFIG_MAX_CPUS 1
118 #define CONFIG_SYS_FSL_NUM_LAWS 10
119 #define CONFIG_SYS_FSL_SEC_COMPAT 2
120 #define QE_MURAM_SIZE 0x20000UL
121 #define MAX_QE_RISC 4
122 #define QE_NUM_OF_SNUM 46
123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
124 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
125 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
126 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
127 #define CONFIG_SYS_FSL_RMU
128 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
129 #define CONFIG_SYS_FSL_ERRATUM_A004508
130 #define CONFIG_SYS_FSL_ERRATUM_A005125
132 #elif defined(CONFIG_ARCH_MPC8572)
133 #define CONFIG_MAX_CPUS 2
134 #define CONFIG_SYS_FSL_NUM_LAWS 12
135 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
136 #define CONFIG_SYS_FSL_SEC_COMPAT 2
137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
138 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
139 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
140 #define CONFIG_SYS_FSL_ERRATUM_A004508
141 #define CONFIG_SYS_FSL_ERRATUM_A005125
143 #elif defined(CONFIG_ARCH_P1010)
144 #define CONFIG_MAX_CPUS 1
145 #define CONFIG_FSL_SDHC_V2_3
146 #define CONFIG_SYS_FSL_NUM_LAWS 12
147 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
148 #define CONFIG_TSECV2
149 #define CONFIG_SYS_FSL_SEC_COMPAT 4
150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
151 #define CONFIG_NUM_DDR_CONTROLLERS 1
152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
153 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
154 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
155 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
156 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
157 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
158 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
159 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
160 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
161 #define CONFIG_SYS_FSL_ERRATUM_A005125
162 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
163 #define CONFIG_SYS_FSL_ERRATUM_A004508
164 #define CONFIG_SYS_FSL_ERRATUM_A007075
165 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
166 #define CONFIG_SYS_FSL_ERRATUM_A006261
167 #define CONFIG_SYS_FSL_ERRATUM_A004477
168 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
169 #define CONFIG_ESDHC_HC_BLK_ADDR
171 /* P1011 is single core version of P1020 */
172 #elif defined(CONFIG_ARCH_P1011)
173 #define CONFIG_MAX_CPUS 1
174 #define CONFIG_SYS_FSL_NUM_LAWS 12
175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
176 #define CONFIG_TSECV2
177 #define CONFIG_FSL_PCIE_DISABLE_ASPM
178 #define CONFIG_SYS_FSL_SEC_COMPAT 2
179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
180 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
181 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
183 #define CONFIG_SYS_FSL_ERRATUM_A004508
184 #define CONFIG_SYS_FSL_ERRATUM_A005125
186 #elif defined(CONFIG_ARCH_P1020)
187 #define CONFIG_MAX_CPUS 2
188 #define CONFIG_SYS_FSL_NUM_LAWS 12
189 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
190 #define CONFIG_TSECV2
191 #define CONFIG_FSL_PCIE_DISABLE_ASPM
192 #define CONFIG_SYS_FSL_SEC_COMPAT 2
193 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
194 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
195 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
196 #define CONFIG_SYS_FSL_ERRATUM_A004508
197 #define CONFIG_SYS_FSL_ERRATUM_A005125
198 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
199 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
202 #elif defined(CONFIG_ARCH_P1021)
203 #define CONFIG_MAX_CPUS 2
204 #define CONFIG_SYS_FSL_NUM_LAWS 12
205 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
206 #define CONFIG_TSECV2
207 #define CONFIG_FSL_PCIE_DISABLE_ASPM
208 #define CONFIG_SYS_FSL_SEC_COMPAT 2
209 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
210 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
211 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
212 #define QE_MURAM_SIZE 0x6000UL
213 #define MAX_QE_RISC 1
214 #define QE_NUM_OF_SNUM 28
215 #define CONFIG_SYS_FSL_ERRATUM_A004508
216 #define CONFIG_SYS_FSL_ERRATUM_A005125
217 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
219 #elif defined(CONFIG_ARCH_P1022)
220 #define CONFIG_MAX_CPUS 2
221 #define CONFIG_SYS_FSL_NUM_LAWS 12
222 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
223 #define CONFIG_TSECV2
224 #define CONFIG_SYS_FSL_SEC_COMPAT 2
225 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
226 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
227 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
228 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
229 #define CONFIG_FSL_SATA_ERRATUM_A001
230 #define CONFIG_SYS_FSL_ERRATUM_A004508
231 #define CONFIG_SYS_FSL_ERRATUM_A005125
232 #define CONFIG_SYS_FSL_ERRATUM_A004477
234 #elif defined(CONFIG_ARCH_P1023)
235 #define CONFIG_MAX_CPUS 2
236 #define CONFIG_SYS_FSL_NUM_LAWS 12
237 #define CONFIG_SYS_FSL_SEC_COMPAT 4
238 #define CONFIG_SYS_NUM_FMAN 1
239 #define CONFIG_SYS_NUM_FM1_DTSEC 2
240 #define CONFIG_NUM_DDR_CONTROLLERS 1
241 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
242 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
243 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
244 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
245 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
246 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
247 #define CONFIG_SYS_FSL_ERRATUM_A004508
248 #define CONFIG_SYS_FSL_ERRATUM_A005125
249 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
250 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
252 /* P1024 is lower end variant of P1020 */
253 #elif defined(CONFIG_ARCH_P1024)
254 #define CONFIG_MAX_CPUS 2
255 #define CONFIG_SYS_FSL_NUM_LAWS 12
256 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
257 #define CONFIG_TSECV2
258 #define CONFIG_FSL_PCIE_DISABLE_ASPM
259 #define CONFIG_SYS_FSL_SEC_COMPAT 2
260 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
262 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
263 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
264 #define CONFIG_SYS_FSL_ERRATUM_A004508
265 #define CONFIG_SYS_FSL_ERRATUM_A005125
267 /* P1025 is lower end variant of P1021 */
268 #elif defined(CONFIG_ARCH_P1025)
269 #define CONFIG_MAX_CPUS 2
270 #define CONFIG_SYS_FSL_NUM_LAWS 12
271 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
272 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
273 #define CONFIG_TSECV2
274 #define CONFIG_FSL_PCIE_DISABLE_ASPM
275 #define CONFIG_SYS_FSL_SEC_COMPAT 2
276 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
277 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
278 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
279 #define QE_MURAM_SIZE 0x6000UL
280 #define MAX_QE_RISC 1
281 #define QE_NUM_OF_SNUM 28
282 #define CONFIG_SYS_FSL_ERRATUM_A004508
283 #define CONFIG_SYS_FSL_ERRATUM_A005125
285 #elif defined(CONFIG_ARCH_P2020)
286 #define CONFIG_MAX_CPUS 2
287 #define CONFIG_SYS_FSL_NUM_LAWS 12
288 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
289 #define CONFIG_SYS_FSL_SEC_COMPAT 2
290 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
291 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
292 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
293 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
294 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
295 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
296 #define CONFIG_SYS_FSL_RMU
297 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
298 #define CONFIG_SYS_FSL_ERRATUM_A004508
299 #define CONFIG_SYS_FSL_ERRATUM_A005125
300 #define CONFIG_SYS_FSL_ERRATUM_A004477
301 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
303 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
304 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
305 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
306 #define CONFIG_MAX_CPUS 4
307 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
308 #define CONFIG_SYS_FSL_NUM_LAWS 32
309 #define CONFIG_SYS_FSL_SEC_COMPAT 4
310 #define CONFIG_SYS_NUM_FMAN 1
311 #define CONFIG_SYS_NUM_FM1_DTSEC 5
312 #define CONFIG_SYS_NUM_FM1_10GEC 1
313 #define CONFIG_NUM_DDR_CONTROLLERS 1
314 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
315 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
316 #define CONFIG_SYS_FSL_TBCLK_DIV 32
317 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
318 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
319 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
320 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
321 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
322 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
323 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
324 #define CONFIG_SYS_FSL_ERRATUM_USB14
325 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
326 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
327 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
328 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
329 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
330 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
331 #define CONFIG_SYS_FSL_ERRATUM_A004510
332 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
333 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
334 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
335 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
336 #define CONFIG_SYS_FSL_ERRATUM_A004849
337 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
338 #define CONFIG_SYS_FSL_ERRATUM_A006261
339 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
341 #elif defined(CONFIG_ARCH_P3041)
342 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
343 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
344 #define CONFIG_MAX_CPUS 4
345 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
346 #define CONFIG_SYS_FSL_NUM_LAWS 32
347 #define CONFIG_SYS_FSL_SEC_COMPAT 4
348 #define CONFIG_SYS_NUM_FMAN 1
349 #define CONFIG_SYS_NUM_FM1_DTSEC 5
350 #define CONFIG_SYS_NUM_FM1_10GEC 1
351 #define CONFIG_NUM_DDR_CONTROLLERS 1
352 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
353 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
354 #define CONFIG_SYS_FSL_TBCLK_DIV 32
355 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
356 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
357 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
358 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
359 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
360 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
361 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
362 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
363 #define CONFIG_SYS_FSL_ERRATUM_USB14
364 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
365 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
366 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
367 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
368 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
369 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
370 #define CONFIG_SYS_FSL_ERRATUM_A004510
371 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
372 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
373 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
374 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
375 #define CONFIG_SYS_FSL_ERRATUM_A004849
376 #define CONFIG_SYS_FSL_ERRATUM_A005812
377 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
378 #define CONFIG_SYS_FSL_ERRATUM_A006261
379 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
381 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
382 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
383 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
384 #define CONFIG_MAX_CPUS 8
385 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
386 #define CONFIG_SYS_FSL_NUM_LAWS 32
387 #define CONFIG_SYS_FSL_SEC_COMPAT 4
388 #define CONFIG_SYS_NUM_FMAN 2
389 #define CONFIG_SYS_NUM_FM1_DTSEC 4
390 #define CONFIG_SYS_NUM_FM2_DTSEC 4
391 #define CONFIG_SYS_NUM_FM1_10GEC 1
392 #define CONFIG_SYS_NUM_FM2_10GEC 1
393 #define CONFIG_NUM_DDR_CONTROLLERS 2
394 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
395 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
396 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
397 #define CONFIG_SYS_FSL_TBCLK_DIV 16
398 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
399 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
400 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
401 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
402 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
403 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
404 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
405 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
406 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
407 #define CONFIG_SYS_P4080_ERRATUM_CPU22
408 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
409 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
410 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
411 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
412 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
413 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
414 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
415 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
416 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
417 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
418 #define CONFIG_SYS_FSL_RMU
419 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
420 #define CONFIG_SYS_FSL_ERRATUM_A004510
421 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
422 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
423 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
424 #define CONFIG_SYS_FSL_ERRATUM_A004849
425 #define CONFIG_SYS_FSL_ERRATUM_A004580
426 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
427 #define CONFIG_SYS_FSL_ERRATUM_A005812
428 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
429 #define CONFIG_SYS_FSL_ERRATUM_A007075
430 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
432 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
433 #define CONFIG_SYS_PPC64 /* 64-bit core */
434 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
435 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
436 #define CONFIG_MAX_CPUS 2
437 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
438 #define CONFIG_SYS_FSL_NUM_LAWS 32
439 #define CONFIG_SYS_FSL_SEC_COMPAT 4
440 #define CONFIG_SYS_NUM_FMAN 1
441 #define CONFIG_SYS_NUM_FM1_DTSEC 5
442 #define CONFIG_SYS_NUM_FM1_10GEC 1
443 #define CONFIG_NUM_DDR_CONTROLLERS 2
444 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
445 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
446 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
447 #define CONFIG_SYS_FSL_TBCLK_DIV 32
448 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
449 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
450 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
451 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
452 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
453 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
454 #define CONFIG_SYS_FSL_ERRATUM_USB14
455 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
456 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
457 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
458 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
459 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
460 #define CONFIG_SYS_FSL_ERRATUM_A004510
461 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
462 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
463 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
464 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
465 #define CONFIG_SYS_FSL_ERRATUM_A006261
466 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
468 #elif defined(CONFIG_PPC_P5040)
469 #define CONFIG_SYS_PPC64
470 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
471 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
472 #define CONFIG_MAX_CPUS 4
473 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
474 #define CONFIG_SYS_FSL_NUM_LAWS 32
475 #define CONFIG_SYS_FSL_SEC_COMPAT 4
476 #define CONFIG_SYS_NUM_FMAN 2
477 #define CONFIG_SYS_NUM_FM1_DTSEC 5
478 #define CONFIG_SYS_NUM_FM1_10GEC 1
479 #define CONFIG_SYS_NUM_FM2_DTSEC 5
480 #define CONFIG_SYS_NUM_FM2_10GEC 1
481 #define CONFIG_NUM_DDR_CONTROLLERS 2
482 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
483 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
484 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
485 #define CONFIG_SYS_FSL_TBCLK_DIV 16
486 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
487 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
488 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
489 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
490 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
491 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
492 #define CONFIG_SYS_FSL_ERRATUM_USB14
493 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
494 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
495 #define CONFIG_SYS_FSL_ERRATUM_A004699
496 #define CONFIG_SYS_FSL_ERRATUM_A004510
497 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
498 #define CONFIG_SYS_FSL_ERRATUM_A006261
499 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
500 #define CONFIG_SYS_FSL_ERRATUM_A005812
502 #elif defined(CONFIG_ARCH_BSC9131)
503 #define CONFIG_MAX_CPUS 1
504 #define CONFIG_FSL_SDHC_V2_3
505 #define CONFIG_SYS_FSL_NUM_LAWS 12
506 #define CONFIG_TSECV2
507 #define CONFIG_SYS_FSL_SEC_COMPAT 4
508 #define CONFIG_NUM_DDR_CONTROLLERS 1
509 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
510 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
511 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
512 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
513 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
514 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
515 #define CONFIG_NAND_FSL_IFC
516 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
517 #define CONFIG_SYS_FSL_ERRATUM_A005125
518 #define CONFIG_SYS_FSL_ERRATUM_A004477
519 #define CONFIG_ESDHC_HC_BLK_ADDR
521 #elif defined(CONFIG_ARCH_BSC9132)
522 #define CONFIG_MAX_CPUS 2
523 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
524 #define CONFIG_FSL_SDHC_V2_3
525 #define CONFIG_SYS_FSL_NUM_LAWS 12
526 #define CONFIG_TSECV2
527 #define CONFIG_SYS_FSL_SEC_COMPAT 4
528 #define CONFIG_NUM_DDR_CONTROLLERS 2
529 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
530 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
531 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
532 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
533 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
534 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
535 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
536 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
537 #define CONFIG_NAND_FSL_IFC
538 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
539 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
540 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
541 #define CONFIG_SYS_FSL_ERRATUM_A005125
542 #define CONFIG_SYS_FSL_ERRATUM_A005434
543 #define CONFIG_SYS_FSL_ERRATUM_A004477
544 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
545 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
546 #define CONFIG_ESDHC_HC_BLK_ADDR
548 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
549 defined(CONFIG_PPC_T4080)
551 #define CONFIG_SYS_PPC64 /* 64-bit core */
552 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
553 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
554 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
555 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
556 #ifdef CONFIG_PPC_T4240
557 #define CONFIG_MAX_CPUS 12
558 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
559 #define CONFIG_SYS_NUM_FM1_DTSEC 8
560 #define CONFIG_SYS_NUM_FM1_10GEC 2
561 #define CONFIG_SYS_NUM_FM2_DTSEC 8
562 #define CONFIG_SYS_NUM_FM2_10GEC 2
563 #define CONFIG_NUM_DDR_CONTROLLERS 3
564 #define CONFIG_SYS_FSL_ERRATUM_A006261
566 #define CONFIG_SYS_NUM_FM1_DTSEC 6
567 #define CONFIG_SYS_NUM_FM1_10GEC 1
568 #define CONFIG_SYS_NUM_FM2_DTSEC 8
569 #define CONFIG_SYS_NUM_FM2_10GEC 1
570 #define CONFIG_NUM_DDR_CONTROLLERS 2
571 #if defined(CONFIG_PPC_T4160)
572 #define CONFIG_MAX_CPUS 8
573 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
574 #elif defined(CONFIG_PPC_T4080)
575 #define CONFIG_MAX_CPUS 4
576 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
579 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
580 #define CONFIG_SYS_FSL_NUM_LAWS 32
581 #define CONFIG_SYS_FSL_SRDS_1
582 #define CONFIG_SYS_FSL_SRDS_2
583 #define CONFIG_SYS_FSL_SRDS_3
584 #define CONFIG_SYS_FSL_SRDS_4
585 #define CONFIG_SYS_FSL_SEC_COMPAT 4
586 #define CONFIG_SYS_NUM_FMAN 2
587 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
588 #define CONFIG_SYS_PME_CLK 0
589 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
590 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
591 #define CONFIG_SYS_FMAN_V3
592 #define CONFIG_SYS_FM1_CLK 3
593 #define CONFIG_SYS_FM2_CLK 3
594 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
595 #define CONFIG_SYS_FSL_TBCLK_DIV 16
596 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
597 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
598 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
599 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
600 #define CONFIG_SYS_FSL_SRIO_LIODN
601 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
602 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
603 #define CONFIG_SYS_FSL_ERRATUM_A004468
604 #define CONFIG_SYS_FSL_ERRATUM_A_004934
605 #define CONFIG_SYS_FSL_ERRATUM_A005871
606 #define CONFIG_SYS_FSL_ERRATUM_A006379
607 #define CONFIG_SYS_FSL_ERRATUM_A007186
608 #define CONFIG_SYS_FSL_ERRATUM_A006593
609 #define CONFIG_SYS_FSL_ERRATUM_A007798
610 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
611 #define CONFIG_SYS_FSL_SFP_VER_3_0
612 #define CONFIG_SYS_FSL_PCI_VER_3_X
614 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
616 #define CONFIG_SYS_PPC64 /* 64-bit core */
617 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
618 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
619 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
620 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
621 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
622 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
623 #define CONFIG_SYS_FSL_NUM_LAWS 32
624 #define CONFIG_SYS_FSL_SRDS_1
625 #define CONFIG_SYS_FSL_SRDS_2
626 #define CONFIG_SYS_MAPLE
627 #define CONFIG_SYS_CPRI
628 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
629 #define CONFIG_SYS_FSL_SEC_COMPAT 4
630 #define CONFIG_SYS_NUM_FMAN 1
631 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
632 #define CONFIG_SYS_FM1_CLK 0
633 #define CONFIG_SYS_CPRI_CLK 3
634 #define CONFIG_SYS_ULB_CLK 4
635 #define CONFIG_SYS_ETVPE_CLK 1
636 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
637 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
638 #define CONFIG_SYS_FMAN_V3
639 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
640 #define CONFIG_SYS_FSL_TBCLK_DIV 16
641 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
642 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
643 #define CONFIG_SYS_FSL_ERRATUM_A_004934
644 #define CONFIG_SYS_FSL_ERRATUM_A005871
645 #define CONFIG_SYS_FSL_ERRATUM_A006379
646 #define CONFIG_SYS_FSL_ERRATUM_A007186
647 #define CONFIG_SYS_FSL_ERRATUM_A006593
648 #define CONFIG_SYS_FSL_ERRATUM_A007075
649 #define CONFIG_SYS_FSL_ERRATUM_A006475
650 #define CONFIG_SYS_FSL_ERRATUM_A006384
651 #define CONFIG_SYS_FSL_ERRATUM_A007212
652 #define CONFIG_SYS_FSL_ERRATUM_A004477
653 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
654 #define CONFIG_SYS_FSL_SFP_VER_3_0
656 #ifdef CONFIG_PPC_B4860
657 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
658 #define CONFIG_MAX_CPUS 4
659 #define CONFIG_MAX_DSP_CPUS 12
660 #define CONFIG_NUM_DSP_CPUS 6
661 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
662 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
663 #define CONFIG_SYS_NUM_FM1_DTSEC 6
664 #define CONFIG_SYS_NUM_FM1_10GEC 2
665 #define CONFIG_NUM_DDR_CONTROLLERS 2
666 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
667 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
668 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
669 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
670 #define CONFIG_SYS_FSL_SRIO_LIODN
672 #define CONFIG_MAX_CPUS 2
673 #define CONFIG_MAX_DSP_CPUS 2
674 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
675 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
676 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
677 #define CONFIG_SYS_NUM_FM1_DTSEC 4
678 #define CONFIG_SYS_NUM_FM1_10GEC 0
679 #define CONFIG_NUM_DDR_CONTROLLERS 1
682 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
683 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
685 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
686 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
687 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
688 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
689 #ifdef CONFIG_SYS_FSL_DDR4
690 #define CONFIG_SYS_FSL_DDRC_GEN4
692 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
693 #define CONFIG_MAX_CPUS 4
694 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
695 #define CONFIG_MAX_CPUS 2
697 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
698 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
699 #define CONFIG_SYS_FSL_NUM_LAWS 16
700 #define CONFIG_SYS_FSL_SRDS_1
701 #define CONFIG_SYS_FSL_SEC_COMPAT 5
702 #define CONFIG_SYS_NUM_FMAN 1
703 #define CONFIG_SYS_NUM_FM1_DTSEC 5
704 #define CONFIG_NUM_DDR_CONTROLLERS 1
705 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
706 #define CONFIG_PME_PLAT_CLK_DIV 2
707 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
708 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
709 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
710 #define CONFIG_SYS_FSL_ERRATUM_A008044
711 #define CONFIG_SYS_FMAN_V3
712 #define CONFIG_FM_PLAT_CLK_DIV 1
713 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
714 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
715 per rcw field value */
716 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
717 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
718 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
719 #define CONFIG_SYS_FSL_TBCLK_DIV 16
720 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
721 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
722 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
723 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
724 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
725 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
726 #define QE_MURAM_SIZE 0x6000UL
727 #define MAX_QE_RISC 1
728 #define QE_NUM_OF_SNUM 28
729 #define CONFIG_SYS_FSL_SFP_VER_3_0
730 #define CONFIG_SYS_FSL_ERRATUM_A008378
731 #define CONFIG_SYS_FSL_ERRATUM_A009663
733 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
734 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
736 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
737 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
738 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
739 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
740 #define CONFIG_SYS_FMAN_V3
741 #ifdef CONFIG_SYS_FSL_DDR4
742 #define CONFIG_SYS_FSL_DDRC_GEN4
744 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
745 #define CONFIG_MAX_CPUS 2
746 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
747 #define CONFIG_MAX_CPUS 1
749 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
750 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
751 #define CONFIG_SYS_FSL_NUM_LAWS 16
752 #define CONFIG_SYS_FSL_SRDS_1
753 #define CONFIG_SYS_FSL_SEC_COMPAT 5
754 #define CONFIG_SYS_NUM_FMAN 1
755 #define CONFIG_SYS_NUM_FM1_DTSEC 4
756 #define CONFIG_SYS_NUM_FM1_10GEC 1
757 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
758 #define CONFIG_NUM_DDR_CONTROLLERS 1
759 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
760 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
761 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
762 #define CONFIG_SYS_FM1_CLK 0
763 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
764 per rcw field value */
765 #define CONFIG_QBMAN_CLK_DIV 1
766 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
767 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
768 #define CONFIG_SYS_FSL_TBCLK_DIV 16
769 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
770 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
771 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
772 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
773 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
774 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
775 #define QE_MURAM_SIZE 0x6000UL
776 #define MAX_QE_RISC 1
777 #define QE_NUM_OF_SNUM 28
778 #define CONFIG_SYS_FSL_SFP_VER_3_0
779 #define CONFIG_SYS_FSL_ERRATUM_A008378
780 #define CONFIG_SYS_FSL_ERRATUM_A009663
782 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
784 #define CONFIG_SYS_PPC64 /* 64-bit core */
785 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
786 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
787 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
788 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
789 #define CONFIG_SYS_FSL_QMAN_V3
790 #define CONFIG_MAX_CPUS 4
791 #define CONFIG_SYS_FSL_NUM_LAWS 32
792 #define CONFIG_SYS_FSL_SEC_COMPAT 4
793 #define CONFIG_SYS_NUM_FMAN 1
794 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
795 #define CONFIG_SYS_FSL_SRDS_1
796 #define CONFIG_SYS_FSL_PCI_VER_3_X
797 #if defined(CONFIG_PPC_T2080)
798 #define CONFIG_SYS_NUM_FM1_DTSEC 8
799 #define CONFIG_SYS_NUM_FM1_10GEC 4
800 #define CONFIG_SYS_FSL_SRDS_2
801 #define CONFIG_SYS_FSL_SRIO_LIODN
802 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
803 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
804 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
805 #elif defined(CONFIG_PPC_T2081)
806 #define CONFIG_SYS_NUM_FM1_DTSEC 6
807 #define CONFIG_SYS_NUM_FM1_10GEC 2
809 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
810 #define CONFIG_NUM_DDR_CONTROLLERS 1
811 #define CONFIG_PME_PLAT_CLK_DIV 1
812 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
813 #define CONFIG_SYS_FM1_CLK 0
814 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
815 per rcw field value */
816 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
817 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
818 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
819 #define CONFIG_SYS_FMAN_V3
820 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
821 #define CONFIG_SYS_FSL_TBCLK_DIV 16
822 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
823 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
824 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
825 #define CONFIG_SYS_FSL_ERRATUM_A007212
826 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
827 #define CONFIG_SYS_FSL_SFP_VER_3_0
828 #define CONFIG_SYS_FSL_ISBC_VER 2
829 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
830 #define CONFIG_SYS_FSL_ERRATUM_A006593
831 #define CONFIG_SYS_FSL_ERRATUM_A007186
832 #define CONFIG_SYS_FSL_ERRATUM_A006379
833 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
834 #define CONFIG_SYS_FSL_SFP_VER_3_0
837 #elif defined(CONFIG_ARCH_C29X)
838 #define CONFIG_MAX_CPUS 1
839 #define CONFIG_FSL_SDHC_V2_3
840 #define CONFIG_SYS_FSL_NUM_LAWS 12
841 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
842 #define CONFIG_TSECV2_1
843 #define CONFIG_SYS_FSL_SEC_COMPAT 6
844 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
845 #define CONFIG_NUM_DDR_CONTROLLERS 1
846 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
847 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
848 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
849 #define CONFIG_SYS_FSL_ERRATUM_A005125
850 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
851 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
853 #elif defined(CONFIG_QEMU_E500)
854 #define CONFIG_MAX_CPUS 1
855 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
858 #error Processor type not defined for this platform
861 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
862 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
866 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
868 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
871 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
872 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
873 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
874 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
875 #define CONFIG_SYS_FSL_DDRC_GEN3
878 #if !defined(CONFIG_ARCH_C29X)
879 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
882 #endif /* _ASM_MPC85xx_CONFIG_H_ */