2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
14 #define LAW_EN 0x80000000
16 #define SET_LAW_ENTRY(idx, a, sz, trgt) \
17 { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
19 #define SET_LAW(a, sz, trgt) \
20 { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
49 #define law_size_bits(sz) (__ilog2_u64(sz) - 1)
50 #define lawar_size(x) (1ULL << ((x & 0x3f) + 1))
52 #ifdef CONFIG_FSL_CORENET
54 LAW_TRGT_IF_PCIE_1
= 0x00,
55 LAW_TRGT_IF_PCIE_2
= 0x01,
56 LAW_TRGT_IF_PCIE_3
= 0x02,
57 LAW_TRGT_IF_PCIE_4
= 0x03,
58 LAW_TRGT_IF_RIO_1
= 0x08,
59 LAW_TRGT_IF_RIO_2
= 0x09,
61 LAW_TRGT_IF_DDR_1
= 0x10,
62 LAW_TRGT_IF_DDR_2
= 0x11, /* 2nd controller */
63 LAW_TRGT_IF_DDR_3
= 0x12,
64 LAW_TRGT_IF_DDR_4
= 0x13,
65 LAW_TRGT_IF_DDR_INTRLV
= 0x14,
66 LAW_TRGT_IF_DDR_INTLV_34
= 0x15,
67 LAW_TRGT_IF_DDR_INTLV_123
= 0x17,
68 LAW_TRGT_IF_DDR_INTLV_1234
= 0x16,
69 LAW_TRGT_IF_BMAN
= 0x18,
70 LAW_TRGT_IF_DCSR
= 0x1d,
71 LAW_TRGT_IF_CCSR
= 0x1e,
72 LAW_TRGT_IF_LBC
= 0x1f,
73 LAW_TRGT_IF_QMAN
= 0x3c,
75 LAW_TRGT_IF_MAPLE
= 0x50,
77 #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
78 #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
81 LAW_TRGT_IF_PCI
= 0x00,
82 LAW_TRGT_IF_PCI_2
= 0x01,
83 #ifndef CONFIG_MPC8641
84 LAW_TRGT_IF_PCIE_1
= 0x02,
86 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
87 LAW_TRGT_IF_OCN_DSP
= 0x03,
89 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
90 LAW_TRGT_IF_PCIE_3
= 0x03,
93 LAW_TRGT_IF_LBC
= 0x04,
94 LAW_TRGT_IF_CCSR
= 0x08,
95 LAW_TRGT_IF_DSP_CCSR
= 0x09,
96 LAW_TRGT_IF_PLATFORM_SRAM
= 0x0a,
97 LAW_TRGT_IF_DDR_INTRLV
= 0x0b,
98 LAW_TRGT_IF_RIO
= 0x0c,
99 #if defined(CONFIG_BSC9132)
100 LAW_TRGT_IF_CLASS_DSP
= 0x0d,
102 LAW_TRGT_IF_RIO_2
= 0x0d,
104 LAW_TRGT_IF_DPAA_SWP_SRAM
= 0x0e,
105 LAW_TRGT_IF_DDR
= 0x0f,
106 LAW_TRGT_IF_DDR_2
= 0x16, /* 2nd controller */
107 /* place holder for 3-way and 4-way interleaving */
110 LAW_TRGT_IF_DDR_INTLV_34
,
111 LAW_TRGT_IF_DDR_INTLV_123
,
112 LAW_TRGT_IF_DDR_INTLV_1234
,
114 #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
115 #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
116 #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
117 #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
118 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
119 #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
121 #ifdef CONFIG_MPC8641
122 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
125 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
126 #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
128 #endif /* CONFIG_FSL_CORENET */
134 enum law_trgt_if trgt_id
;
137 extern void set_law(u8 idx
, phys_addr_t addr
, enum law_size sz
, enum law_trgt_if id
);
138 extern int set_next_law(phys_addr_t addr
, enum law_size sz
, enum law_trgt_if id
);
139 extern int set_last_law(phys_addr_t addr
, enum law_size sz
, enum law_trgt_if id
);
140 extern int set_ddr_laws(u64 start
, u64 sz
, enum law_trgt_if id
);
141 extern struct law_entry
find_law(phys_addr_t addr
);
142 extern void disable_law(u8 idx
);
143 extern void init_laws(void);
144 extern void print_laws(void);
146 /* define in board code */
147 extern struct law_entry law_table
[];
148 extern int num_law_entries
;