arch/powerpc/include/asm/fsl_secure_boot.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_SECURE_BOOT_H
   8 #define __FSL_SECURE_BOOT_H
   9 #include <asm/config_mpc85xx.h>
  10
  11 #ifdef CONFIG_SECURE_BOOT
  12
  13 #ifndef CONFIG_FIT_SIGNATURE
  14 #define CONFIG_CHAIN_OF_TRUST
  15 #endif
  16
  17 #if defined(CONFIG_FSL_CORENET)
  18 #define CONFIG_SYS_PBI_FLASH_BASE               0xc0000000
  19 #elif defined(CONFIG_TARGET_BSC9132QDS)
  20 #define CONFIG_SYS_PBI_FLASH_BASE               0xc8000000
  21 #elif defined(CONFIG_TARGET_C29XPCIE)
  22 #define CONFIG_SYS_PBI_FLASH_BASE               0xcc000000
  23 #else
  24 #define CONFIG_SYS_PBI_FLASH_BASE               0xce000000
  25 #endif
  26 #define CONFIG_SYS_PBI_FLASH_WINDOW             0xcff80000
  27
  28 #if defined(CONFIG_TARGET_B4860QDS) || \
  29         defined(CONFIG_TARGET_B4420QDS) || \
  30         defined(CONFIG_TARGET_T4160QDS) || \
  31         defined(CONFIG_TARGET_T4240QDS) || \
  32         defined(CONFIG_TARGET_T2080QDS) || \
  33         defined(CONFIG_TARGET_T2080RDB) || \
  34         defined(CONFIG_TARGET_T1040QDS) || \
  35         defined(CONFIG_TARGET_T1040RDB) || \
  36         defined(CONFIG_TARGET_T1040D4RDB) || \
  37         defined(CONFIG_TARGET_T1042RDB) || \
  38         defined(CONFIG_TARGET_T1042D4RDB) || \
  39         defined(CONFIG_TARGET_T1042RDB_PI) || \
  40         defined(CONFIG_ARCH_T1023) || \
  41         defined(CONFIG_ARCH_T1024)
  42 #ifndef CONFIG_SYS_RAMBOOT
  43 #define CONFIG_SYS_CPC_REINIT_F
  44 #endif
  45 #define CONFIG_KEY_REVOCATION
  46 #undef CONFIG_SYS_INIT_L3_ADDR
  47 #define CONFIG_SYS_INIT_L3_ADDR                 0xbff00000
  48 #endif
  49
  50 #if defined(CONFIG_RAMBOOT_PBL)
  51 #undef CONFIG_SYS_INIT_L3_ADDR
  52 #ifdef CONFIG_SYS_INIT_L3_VADDR
  53 #define CONFIG_SYS_INIT_L3_ADDR \
  54                         (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
  55                                         0xbff00000
  56 #else
  57 #define CONFIG_SYS_INIT_L3_ADDR         0xbff00000
  58 #endif
  59 #endif
  60
  61 #if defined(CONFIG_TARGET_C29XPCIE)
  62 #define CONFIG_KEY_REVOCATION
  63 #endif
  64
  65 #if defined(CONFIG_ARCH_P3041)  ||      \
  66         defined(CONFIG_ARCH_P4080) ||   \
  67         defined(CONFIG_ARCH_P5020) ||   \
  68         defined(CONFIG_ARCH_P5040) ||   \
  69         defined(CONFIG_ARCH_P2041)
  70         #define CONFIG_FSL_TRUST_ARCH_v1
  71 #endif
  72
  73 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
  74 /* The key used for verification of next level images
  75  * is picked up from an Extension Table which has
  76  * been verified by the ISBC (Internal Secure boot Code)
  77  * in boot ROM of the SoC.
  78  * The feature is only applicable in case of NOR boot and is
  79  * not applicable in case of RAMBOOT (NAND, SD, SPI).
  80  */
  81 #define CONFIG_FSL_ISBC_KEY_EXT
  82 #endif
  83 #endif /* #ifdef CONFIG_SECURE_BOOT */
  84
  85 #ifdef CONFIG_CHAIN_OF_TRUST
  86 #ifdef CONFIG_SPL_BUILD
  87 /*
  88  * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
  89  * due to space crunch on CPC and thus malloc will not work.
  90  */
  91 #define CONFIG_SPL_PPAACT_ADDR          0x2e000000
  92 #define CONFIG_SPL_SPAACT_ADDR          0x2f000000
  93 #define CONFIG_SPL_JR0_LIODN_S          454
  94 #define CONFIG_SPL_JR0_LIODN_NS         458
  95 /*
  96  * Define the key hash for U-Boot here if public/private key pair used to
  97  * sign U-boot are different from the SRK hash put in the fuse
  98  * Example of defining KEY_HASH is
  99  * #define CONFIG_SPL_UBOOT_KEY_HASH \
 100  *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
 101  * else leave it defined as NULL
 102  */
 103
 104 #define CONFIG_SPL_UBOOT_KEY_HASH       NULL
 105 #endif /* ifdef CONFIG_SPL_BUILD */
 106
 107 #define CONFIG_CMD_ESBC_VALIDATE
 108 #define CONFIG_CMD_BLOB
 109 #define CONFIG_FSL_SEC_MON
 110 #define CONFIG_SHA_PROG_HW_ACCEL
 111 #define CONFIG_RSA_FREESCALE_EXP
 112
 113 #ifndef CONFIG_FSL_CAAM
 114 #define CONFIG_FSL_CAAM
 115 #endif
 116
 117 #ifndef CONFIG_SPL_BUILD
 118 /*
 119  * fsl_setenv_chain_of_trust() must be called from
 120  * board_late_init()
 121  */
 122 #ifndef CONFIG_BOARD_LATE_INIT
 123 #define CONFIG_BOARD_LATE_INIT
 124 #endif
 125
 126 /* If Boot Script is not on NOR and is required to be copied on RAM */
 127 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 128 #define CONFIG_BS_HDR_ADDR_RAM          0x00010000
 129 #define CONFIG_BS_HDR_ADDR_DEVICE       0x00800000
 130 #define CONFIG_BS_HDR_SIZE              0x00002000
 131 #define CONFIG_BS_ADDR_RAM              0x00012000
 132 #define CONFIG_BS_ADDR_DEVICE           0x00802000
 133 #define CONFIG_BS_SIZE                  0x00001000
 134
 135 #define CONFIG_BOOTSCRIPT_HDR_ADDR      CONFIG_BS_HDR_ADDR_RAM
 136 #else
 137
 138 /* The bootscript header address is different for B4860 because the NOR
 139  * mapping is different on B4 due to reduced NOR size.
 140  */
 141 #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
 142 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xecc00000
 143 #elif defined(CONFIG_FSL_CORENET)
 144 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xe8e00000
 145 #elif defined(CONFIG_TARGET_BSC9132QDS)
 146 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0x88020000
 147 #elif defined(CONFIG_TARGET_C29XPCIE)
 148 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xec020000
 149 #else
 150 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xee020000
 151 #endif
 152
 153 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
 154
 155 #include <config_fsl_chain_trust.h>
 156 #endif /* #ifndef CONFIG_SPL_BUILD */
 157 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
 158 #endif