arch/powerpc/include/asm/immap_83xx.h

   1 /*
   2  * Copyright 2004-2009 Freescale Semiconductor, Inc.
   3  *
   4  * MPC83xx Internal Memory Map
   5  *
   6  * Contributors:
   7  *      Dave Liu <daveliu@freescale.com>
   8  *      Tanya Jiang <tanya.jiang@freescale.com>
   9  *      Mandy Lavi <mandy.lavi@freescale.com>
  10  *      Eran Liberty <liberty@freescale.com>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  *
  27  */
  28 #ifndef __IMMAP_83xx__
  29 #define __IMMAP_83xx__
  30
  31 #include <asm/types.h>
  32 #include <asm/fsl_i2c.h>
  33 #include <asm/mpc8xxx_spi.h>
  34 #include <asm/fsl_lbc.h>
  35 #include <asm/fsl_dma.h>
  36
  37 /*
  38  * Local Access Window
  39  */
  40 typedef struct law83xx {
  41         u32 bar;                /* LBIU local access window base address register */
  42         u32 ar;                 /* LBIU local access window attribute register */
  43 } law83xx_t;
  44
  45 /*
  46  * System configuration registers
  47  */
  48 typedef struct sysconf83xx {
  49         u32 immrbar;            /* Internal memory map base address register */
  50         u8 res0[0x04];
  51         u32 altcbar;            /* Alternate configuration base address register */
  52         u8 res1[0x14];
  53         law83xx_t lblaw[4];     /* LBIU local access window */
  54         u8 res2[0x20];
  55         law83xx_t pcilaw[2];    /* PCI local access window */
  56         u8 res3[0x10];
  57         law83xx_t pcielaw[2];   /* PCI Express local access window */
  58         u8 res4[0x10];
  59         law83xx_t ddrlaw[2];    /* DDR local access window */
  60         u8 res5[0x50];
  61         u32 sgprl;              /* System General Purpose Register Low */
  62         u32 sgprh;              /* System General Purpose Register High */
  63         u32 spridr;             /* System Part and Revision ID Register */
  64         u8 res6[0x04];
  65         u32 spcr;               /* System Priority Configuration Register */
  66         u32 sicrl;              /* System I/O Configuration Register Low */
  67         u32 sicrh;              /* System I/O Configuration Register High */
  68         u8 res7[0x04];
  69         u32 sidcr0;             /* System I/O Delay Configuration Register 0 */
  70         u32 sidcr1;             /* System I/O Delay Configuration Register 1 */
  71         u32 ddrcdr;             /* DDR Control Driver Register */
  72         u32 ddrdsr;             /* DDR Debug Status Register */
  73         u32 obir;               /* Output Buffer Impedance Register */
  74         u8 res8[0xC];
  75         u32 pecr1;              /* PCI Express control register 1 */
  76 #ifdef CONFIG_MPC8308
  77         u32 sdhccr;             /* eSDHC Control Registers for MPC8308 */
  78 #else
  79         u32 pecr2;              /* PCI Express control register 2 */
  80 #endif
  81         u8 res9[0xB8];
  82 } sysconf83xx_t;
  83
  84 /*
  85  * Watch Dog Timer (WDT) Registers
  86  */
  87 typedef struct wdt83xx {
  88         u8 res0[4];
  89         u32 swcrr;              /* System watchdog control register */
  90         u32 swcnr;              /* System watchdog count register */
  91         u8 res1[2];
  92         u16 swsrr;              /* System watchdog service register */
  93         u8 res2[0xF0];
  94 } wdt83xx_t;
  95
  96 /*
  97  * RTC/PIT Module Registers
  98  */
  99 typedef struct rtclk83xx {
 100         u32 cnr;                /* control register */
 101         u32 ldr;                /* load register */
 102         u32 psr;                /* prescale register */
 103         u32 ctr;                /* counter value field register */
 104         u32 evr;                /* event register */
 105         u32 alr;                /* alarm register */
 106         u8 res0[0xE8];
 107 } rtclk83xx_t;
 108
 109 /*
 110  * Global timer module
 111  */
 112 typedef struct gtm83xx {
 113         u8 cfr1;                /* Timer1/2 Configuration */
 114         u8 res0[3];
 115         u8 cfr2;                /* Timer3/4 Configuration */
 116         u8 res1[10];
 117         u16 mdr1;               /* Timer1 Mode Register */
 118         u16 mdr2;               /* Timer2 Mode Register */
 119         u16 rfr1;               /* Timer1 Reference Register */
 120         u16 rfr2;               /* Timer2 Reference Register */
 121         u16 cpr1;               /* Timer1 Capture Register */
 122         u16 cpr2;               /* Timer2 Capture Register */
 123         u16 cnr1;               /* Timer1 Counter Register */
 124         u16 cnr2;               /* Timer2 Counter Register */
 125         u16 mdr3;               /* Timer3 Mode Register */
 126         u16 mdr4;               /* Timer4 Mode Register */
 127         u16 rfr3;               /* Timer3 Reference Register */
 128         u16 rfr4;               /* Timer4 Reference Register */
 129         u16 cpr3;               /* Timer3 Capture Register */
 130         u16 cpr4;               /* Timer4 Capture Register */
 131         u16 cnr3;               /* Timer3 Counter Register */
 132         u16 cnr4;               /* Timer4 Counter Register */
 133         u16 evr1;               /* Timer1 Event Register */
 134         u16 evr2;               /* Timer2 Event Register */
 135         u16 evr3;               /* Timer3 Event Register */
 136         u16 evr4;               /* Timer4 Event Register */
 137         u16 psr1;               /* Timer1 Prescaler Register */
 138         u16 psr2;               /* Timer2 Prescaler Register */
 139         u16 psr3;               /* Timer3 Prescaler Register */
 140         u16 psr4;               /* Timer4 Prescaler Register */
 141         u8 res[0xC0];
 142 } gtm83xx_t;
 143
 144 /*
 145  * Integrated Programmable Interrupt Controller
 146  */
 147 typedef struct ipic83xx {
 148         u32 sicfr;              /* System Global Interrupt Configuration Register */
 149         u32 sivcr;              /* System Global Interrupt Vector Register */
 150         u32 sipnr_h;            /* System Internal Interrupt Pending Register - High */
 151         u32 sipnr_l;            /* System Internal Interrupt Pending Register - Low */
 152         u32 siprr_a;            /* System Internal Interrupt Group A Priority Register */
 153         u8 res0[8];
 154         u32 siprr_d;            /* System Internal Interrupt Group D Priority Register */
 155         u32 simsr_h;            /* System Internal Interrupt Mask Register - High */
 156         u32 simsr_l;            /* System Internal Interrupt Mask Register - Low */
 157         u8 res1[4];
 158         u32 sepnr;              /* System External Interrupt Pending Register */
 159         u32 smprr_a;            /* System Mixed Interrupt Group A Priority Register */
 160         u32 smprr_b;            /* System Mixed Interrupt Group B Priority Register */
 161         u32 semsr;              /* System External Interrupt Mask Register */
 162         u32 secnr;              /* System External Interrupt Control Register */
 163         u32 sersr;              /* System Error Status Register */
 164         u32 sermr;              /* System Error Mask Register */
 165         u32 sercr;              /* System Error Control Register */
 166         u8 res2[4];
 167         u32 sifcr_h;            /* System Internal Interrupt Force Register - High */
 168         u32 sifcr_l;            /* System Internal Interrupt Force Register - Low */
 169         u32 sefcr;              /* System External Interrupt Force Register */
 170         u32 serfr;              /* System Error Force Register */
 171         u32 scvcr;              /* System Critical Interrupt Vector Register */
 172         u32 smvcr;              /* System Management Interrupt Vector Register */
 173         u8 res3[0x98];
 174 } ipic83xx_t;
 175
 176 /*
 177  * System Arbiter Registers
 178  */
 179 typedef struct arbiter83xx {
 180         u32 acr;                /* Arbiter Configuration Register */
 181         u32 atr;                /* Arbiter Timers Register */
 182         u8 res[4];
 183         u32 aer;                /* Arbiter Event Register */
 184         u32 aidr;               /* Arbiter Interrupt Definition Register */
 185         u32 amr;                /* Arbiter Mask Register */
 186         u32 aeatr;              /* Arbiter Event Attributes Register */
 187         u32 aeadr;              /* Arbiter Event Address Register */
 188         u32 aerr;               /* Arbiter Event Response Register */
 189         u8 res1[0xDC];
 190 } arbiter83xx_t;
 191
 192 /*
 193  * Reset Module
 194  */
 195 typedef struct reset83xx {
 196         u32 rcwl;               /* Reset Configuration Word Low Register */
 197         u32 rcwh;               /* Reset Configuration Word High Register */
 198         u8 res0[8];
 199         u32 rsr;                /* Reset Status Register */
 200         u32 rmr;                /* Reset Mode Register */
 201         u32 rpr;                /* Reset protection Register */
 202         u32 rcr;                /* Reset Control Register */
 203         u32 rcer;               /* Reset Control Enable Register */
 204         u8 res1[0xDC];
 205 } reset83xx_t;
 206
 207 /*
 208  * Clock Module
 209  */
 210 typedef struct clk83xx {
 211         u32 spmr;               /* system PLL mode Register */
 212         u32 occr;               /* output clock control Register */
 213         u32 sccr;               /* system clock control Register */
 214         u8 res0[0xF4];
 215 } clk83xx_t;
 216
 217 /*
 218  * Power Management Control Module
 219  */
 220 typedef struct pmc83xx {
 221         u32 pmccr;              /* PMC Configuration Register */
 222         u32 pmcer;              /* PMC Event Register */
 223         u32 pmcmr;              /* PMC Mask Register */
 224         u32 pmccr1;             /* PMC Configuration Register 1 */
 225         u32 pmccr2;             /* PMC Configuration Register 2 */
 226         u8 res0[0xEC];
 227 } pmc83xx_t;
 228
 229 /*
 230  * General purpose I/O module
 231  */
 232 typedef struct gpio83xx {
 233         u32 dir;                /* direction register */
 234         u32 odr;                /* open drain register */
 235         u32 dat;                /* data register */
 236         u32 ier;                /* interrupt event register */
 237         u32 imr;                /* interrupt mask register */
 238         u32 icr;                /* external interrupt control register */
 239         u8 res0[0xE8];
 240 } gpio83xx_t;
 241
 242 /*
 243  * QE Ports Interrupts Registers
 244  */
 245 typedef struct qepi83xx {
 246         u8 res0[0xC];
 247         u32 qepier;             /* QE Ports Interrupt Event Register */
 248         u32 qepimr;             /* QE Ports Interrupt Mask Register */
 249         u32 qepicr;             /* QE Ports Interrupt Control Register */
 250         u8 res1[0xE8];
 251 } qepi83xx_t;
 252
 253 /*
 254  * QE Parallel I/O Ports
 255  */
 256 typedef struct gpio_n {
 257         u32 podr;               /* Open Drain Register */
 258         u32 pdat;               /* Data Register */
 259         u32 dir1;               /* direction register 1 */
 260         u32 dir2;               /* direction register 2 */
 261         u32 ppar1;              /* Pin Assignment Register 1 */
 262         u32 ppar2;              /* Pin Assignment Register 2 */
 263 } gpio_n_t;
 264
 265 typedef struct qegpio83xx {
 266         gpio_n_t ioport[0x7];
 267         u8 res0[0x358];
 268 } qepio83xx_t;
 269
 270 /*
 271  * QE Secondary Bus Access Windows
 272  */
 273 typedef struct qesba83xx {
 274         u32 lbmcsar;            /* Local bus memory controller start address */
 275         u32 sdmcsar;            /* Secondary DDR memory controller start address */
 276         u8 res0[0x38];
 277         u32 lbmcear;            /* Local bus memory controller end address */
 278         u32 sdmcear;            /* Secondary DDR memory controller end address */
 279         u8 res1[0x38];
 280         u32 lbmcar;             /* Local bus memory controller attributes */
 281         u32 sdmcar;             /* Secondary DDR memory controller attributes */
 282         u8 res2[0x378];
 283 } qesba83xx_t;
 284
 285 /*
 286  * DDR Memory Controller Memory Map
 287  */
 288 typedef struct ddr_cs_bnds {
 289         u32 csbnds;
 290         u8 res0[4];
 291 } ddr_cs_bnds_t;
 292
 293 typedef struct ddr83xx {
 294         ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
 295         u8 res0[0x60];
 296         u32 cs_config[4];       /* Chip Select x Configuration */
 297         u8 res1[0x70];
 298         u32 timing_cfg_3;       /* SDRAM Timing Configuration 3 */
 299         u32 timing_cfg_0;       /* SDRAM Timing Configuration 0 */
 300         u32 timing_cfg_1;       /* SDRAM Timing Configuration 1 */
 301         u32 timing_cfg_2;       /* SDRAM Timing Configuration 2 */
 302         u32 sdram_cfg;          /* SDRAM Control Configuration */
 303         u32 sdram_cfg2;         /* SDRAM Control Configuration 2 */
 304         u32 sdram_mode;         /* SDRAM Mode Configuration */
 305         u32 sdram_mode2;        /* SDRAM Mode Configuration 2 */
 306         u32 sdram_md_cntl;      /* SDRAM Mode Control */
 307         u32 sdram_interval;     /* SDRAM Interval Configuration */
 308         u32 ddr_data_init;      /* SDRAM Data Initialization */
 309         u8 res2[4];
 310         u32 sdram_clk_cntl;     /* SDRAM Clock Control */
 311         u8 res3[0x14];
 312         u32 ddr_init_addr;      /* DDR training initialization address */
 313         u32 ddr_init_ext_addr;  /* DDR training initialization extended address */
 314         u8 res4[0xAA8];
 315         u32 ddr_ip_rev1;        /* DDR IP block revision 1 */
 316         u32 ddr_ip_rev2;        /* DDR IP block revision 2 */
 317         u8 res5[0x200];
 318         u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
 319         u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
 320         u32 ecc_err_inject;     /* Memory Data Path Error Injection Mask ECC */
 321         u8 res6[0x14];
 322         u32 capture_data_hi;    /* Memory Data Path Read Capture High */
 323         u32 capture_data_lo;    /* Memory Data Path Read Capture Low */
 324         u32 capture_ecc;        /* Memory Data Path Read Capture ECC */
 325         u8 res7[0x14];
 326         u32 err_detect;         /* Memory Error Detect */
 327         u32 err_disable;        /* Memory Error Disable */
 328         u32 err_int_en;         /* Memory Error Interrupt Enable */
 329         u32 capture_attributes; /* Memory Error Attributes Capture */
 330         u32 capture_address;    /* Memory Error Address Capture */
 331         u32 capture_ext_address;/* Memory Error Extended Address Capture */
 332         u32 err_sbe;            /* Memory Single-Bit ECC Error Management */
 333         u8 res8[0xA4];
 334         u32 debug_reg;
 335         u8 res9[0xFC];
 336 } ddr83xx_t;
 337
 338 /*
 339  * DUART
 340  */
 341 typedef struct duart83xx {
 342         u8 urbr_ulcr_udlb;      /* combined register for URBR, UTHR and UDLB */
 343         u8 uier_udmb;           /* combined register for UIER and UDMB */
 344         u8 uiir_ufcr_uafr;      /* combined register for UIIR, UFCR and UAFR */
 345         u8 ulcr;                /* line control register */
 346         u8 umcr;                /* MODEM control register */
 347         u8 ulsr;                /* line status register */
 348         u8 umsr;                /* MODEM status register */
 349         u8 uscr;                /* scratch register */
 350         u8 res0[8];
 351         u8 udsr;                /* DMA status register */
 352         u8 res1[3];
 353         u8 res2[0xEC];
 354 } duart83xx_t;
 355
 356 /*
 357  * DMA/Messaging Unit
 358  */
 359 typedef struct dma83xx {
 360         u32 res0[0xC];          /* 0x0-0x29 reseverd */
 361         u32 omisr;              /* 0x30 Outbound message interrupt status register */
 362         u32 omimr;              /* 0x34 Outbound message interrupt mask register */
 363         u32 res1[0x6];          /* 0x38-0x49 reserved */
 364         u32 imr0;               /* 0x50 Inbound message register 0 */
 365         u32 imr1;               /* 0x54 Inbound message register 1 */
 366         u32 omr0;               /* 0x58 Outbound message register 0 */
 367         u32 omr1;               /* 0x5C Outbound message register 1 */
 368         u32 odr;                /* 0x60 Outbound doorbell register */
 369         u32 res2;               /* 0x64-0x67 reserved */
 370         u32 idr;                /* 0x68 Inbound doorbell register */
 371         u32 res3[0x5];          /* 0x6C-0x79 reserved */
 372         u32 imisr;              /* 0x80 Inbound message interrupt status register */
 373         u32 imimr;              /* 0x84 Inbound message interrupt mask register */
 374         u32 res4[0x1E];         /* 0x88-0x99 reserved */
 375         struct fsl_dma dma[4];
 376 } dma83xx_t;
 377
 378 /*
 379  * PCI Software Configuration Registers
 380  */
 381 typedef struct pciconf83xx {
 382         u32 config_address;
 383         u32 config_data;
 384         u32 int_ack;
 385         u8 res[116];
 386 } pciconf83xx_t;
 387
 388 /*
 389  * PCI Outbound Translation Register
 390  */
 391 typedef struct pci_outbound_window {
 392         u32 potar;
 393         u8 res0[4];
 394         u32 pobar;
 395         u8 res1[4];
 396         u32 pocmr;
 397         u8 res2[4];
 398 } pot83xx_t;
 399
 400 /*
 401  * Sequencer
 402  */
 403 typedef struct ios83xx {
 404         pot83xx_t pot[6];
 405         u8 res0[0x60];
 406         u32 pmcr;
 407         u8 res1[4];
 408         u32 dtcr;
 409         u8 res2[4];
 410 } ios83xx_t;
 411
 412 /*
 413  * PCI Controller Control and Status Registers
 414  */
 415 typedef struct pcictrl83xx {
 416         u32 esr;
 417         u32 ecdr;
 418         u32 eer;
 419         u32 eatcr;
 420         u32 eacr;
 421         u32 eeacr;
 422         u32 edlcr;
 423         u32 edhcr;
 424         u32 gcr;
 425         u32 ecr;
 426         u32 gsr;
 427         u8 res0[12];
 428         u32 pitar2;
 429         u8 res1[4];
 430         u32 pibar2;
 431         u32 piebar2;
 432         u32 piwar2;
 433         u8 res2[4];
 434         u32 pitar1;
 435         u8 res3[4];
 436         u32 pibar1;
 437         u32 piebar1;
 438         u32 piwar1;
 439         u8 res4[4];
 440         u32 pitar0;
 441         u8 res5[4];
 442         u32 pibar0;
 443         u8 res6[4];
 444         u32 piwar0;
 445         u8 res7[132];
 446 } pcictrl83xx_t;
 447
 448 /*
 449  * USB
 450  */
 451 typedef struct usb83xx {
 452         u8 fixme[0x1000];
 453 } usb83xx_t;
 454
 455 /*
 456  * TSEC
 457  */
 458 typedef struct tsec83xx {
 459         u8 fixme[0x1000];
 460 } tsec83xx_t;
 461
 462 /*
 463  * Security
 464  */
 465 typedef struct security83xx {
 466         u8 fixme[0x10000];
 467 } security83xx_t;
 468
 469 /*
 470  *  PCI Express
 471  */
 472 struct pex_inbound_window {
 473         u32 ar;
 474         u32 tar;
 475         u32 barl;
 476         u32 barh;
 477 };
 478
 479 struct pex_outbound_window {
 480         u32 ar;
 481         u32 bar;
 482         u32 tarl;
 483         u32 tarh;
 484 };
 485
 486 struct pex_csb_bridge {
 487         u32 pex_csb_ver;
 488         u32 pex_csb_cab;
 489         u32 pex_csb_ctrl;
 490         u8 res0[8];
 491         u32 pex_dms_dstmr;
 492         u8 res1[4];
 493         u32 pex_cbs_stat;
 494         u8 res2[0x20];
 495         u32 pex_csb_obctrl;
 496         u32 pex_csb_obstat;
 497         u8 res3[0x98];
 498         u32 pex_csb_ibctrl;
 499         u32 pex_csb_ibstat;
 500         u8 res4[0xb8];
 501         u32 pex_wdma_ctrl;
 502         u32 pex_wdma_addr;
 503         u32 pex_wdma_stat;
 504         u8 res5[0x94];
 505         u32 pex_rdma_ctrl;
 506         u32 pex_rdma_addr;
 507         u32 pex_rdma_stat;
 508         u8 res6[0xd4];
 509         u32 pex_ombcr;
 510         u32 pex_ombdr;
 511         u8 res7[0x38];
 512         u32 pex_imbcr;
 513         u32 pex_imbdr;
 514         u8 res8[0x38];
 515         u32 pex_int_enb;
 516         u32 pex_int_stat;
 517         u32 pex_int_apio_vec1;
 518         u32 pex_int_apio_vec2;
 519         u8 res9[0x10];
 520         u32 pex_int_ppio_vec1;
 521         u32 pex_int_ppio_vec2;
 522         u32 pex_int_wdma_vec1;
 523         u32 pex_int_wdma_vec2;
 524         u32 pex_int_rdma_vec1;
 525         u32 pex_int_rdma_vec2;
 526         u32 pex_int_misc_vec;
 527         u8 res10[4];
 528         u32 pex_int_axi_pio_enb;
 529         u32 pex_int_axi_wdma_enb;
 530         u32 pex_int_axi_rdma_enb;
 531         u32 pex_int_axi_misc_enb;
 532         u32 pex_int_axi_pio_stat;
 533         u32 pex_int_axi_wdma_stat;
 534         u32 pex_int_axi_rdma_stat;
 535         u32 pex_int_axi_misc_stat;
 536         u8 res11[0xa0];
 537         struct pex_outbound_window pex_outbound_win[4];
 538         u8 res12[0x100];
 539         u32 pex_epiwtar0;
 540         u32 pex_epiwtar1;
 541         u32 pex_epiwtar2;
 542         u32 pex_epiwtar3;
 543         u8 res13[0x70];
 544         struct pex_inbound_window pex_inbound_win[4];
 545 };
 546
 547 typedef struct pex83xx {
 548         u8 pex_cfg_header[0x404];
 549         u32 pex_ltssm_stat;
 550         u8 res0[0x30];
 551         u32 pex_ack_replay_timeout;
 552         u8 res1[4];
 553         u32 pex_gclk_ratio;
 554         u8 res2[0xc];
 555         u32 pex_pm_timer;
 556         u32 pex_pme_timeout;
 557         u8 res3[4];
 558         u32 pex_aspm_req_timer;
 559         u8 res4[0x18];
 560         u32 pex_ssvid_update;
 561         u8 res5[0x34];
 562         u32 pex_cfg_ready;
 563         u8 res6[0x24];
 564         u32 pex_bar_sizel;
 565         u8 res7[4];
 566         u32 pex_bar_sel;
 567         u8 res8[0x20];
 568         u32 pex_bar_pf;
 569         u8 res9[0x88];
 570         u32 pex_pme_to_ack_tor;
 571         u8 res10[0xc];
 572         u32 pex_ss_intr_mask;
 573         u8 res11[0x25c];
 574         struct pex_csb_bridge bridge;
 575         u8 res12[0x160];
 576 } pex83xx_t;
 577
 578 /*
 579  * SATA
 580  */
 581 typedef struct sata83xx {
 582         u8 fixme[0x1000];
 583 } sata83xx_t;
 584
 585 /*
 586  * eSDHC
 587  */
 588 typedef struct sdhc83xx {
 589         u8 fixme[0x1000];
 590 } sdhc83xx_t;
 591
 592 /*
 593  * SerDes
 594  */
 595 typedef struct serdes83xx {
 596         u32 srdscr0;
 597         u32 srdscr1;
 598         u32 srdscr2;
 599         u32 srdscr3;
 600         u32 srdscr4;
 601         u8 res0[0xc];
 602         u32 srdsrstctl;
 603         u8 res1[0xdc];
 604 } serdes83xx_t;
 605
 606 /*
 607  * On Chip ROM
 608  */
 609 typedef struct rom83xx {
 610         u8 mem[0x10000];
 611 } rom83xx_t;
 612
 613 /*
 614  * TDM
 615  */
 616 typedef struct tdm83xx {
 617         u8 fixme[0x200];
 618 } tdm83xx_t;
 619
 620 /*
 621  * TDM DMAC
 622  */
 623 typedef struct tdmdmac83xx {
 624         u8 fixme[0x2000];
 625 } tdmdmac83xx_t;
 626
 627 #if defined(CONFIG_MPC834x)
 628 typedef struct immap {
 629         sysconf83xx_t           sysconf;        /* System configuration */
 630         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 631         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 632         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 633         gtm83xx_t               gtm[2];         /* Global Timers Module */
 634         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 635         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 636         reset83xx_t             reset;          /* Reset Module */
 637         clk83xx_t               clk;            /* System Clock Module */
 638         pmc83xx_t               pmc;            /* Power Management Control Module */
 639         gpio83xx_t              gpio[2];        /* General purpose I/O module */
 640         u8                      res0[0x200];
 641         u8                      dll_ddr[0x100];
 642         u8                      dll_lbc[0x100];
 643         u8                      res1[0xE00];
 644         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 645         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 646         u8                      res2[0x1300];
 647         duart83xx_t             duart[2];       /* DUART */
 648         u8                      res3[0x900];
 649         fsl_lbc_t               im_lbc;         /* Local Bus Controller Regs */
 650         u8                      res4[0x1000];
 651         spi8xxx_t               spi;            /* Serial Peripheral Interface */
 652         dma83xx_t               dma;            /* DMA */
 653         pciconf83xx_t           pci_conf[2];    /* PCI Software Configuration Registers */
 654         ios83xx_t               ios;            /* Sequencer */
 655         pcictrl83xx_t           pci_ctrl[2];    /* PCI Controller Control and Status Registers */
 656         u8                      res5[0x19900];
 657         usb83xx_t               usb[2];
 658         tsec83xx_t              tsec[2];
 659         u8                      res6[0xA000];
 660         security83xx_t          security;
 661         u8                      res7[0xC0000];
 662 } immap_t;
 663
 664 #ifdef CONFIG_HAS_FSL_MPH_USB
 665 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x22000  /* use the MPH controller */
 666 #else
 667 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000  /* use the DR controller */
 668 #endif
 669
 670 #elif defined(CONFIG_MPC8313)
 671 typedef struct immap {
 672         sysconf83xx_t           sysconf;        /* System configuration */
 673         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 674         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 675         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 676         gtm83xx_t               gtm[2];         /* Global Timers Module */
 677         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 678         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 679         reset83xx_t             reset;          /* Reset Module */
 680         clk83xx_t               clk;            /* System Clock Module */
 681         pmc83xx_t               pmc;            /* Power Management Control Module */
 682         gpio83xx_t              gpio[1];        /* General purpose I/O module */
 683         u8                      res0[0x1300];
 684         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 685         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 686         u8                      res1[0x1300];
 687         duart83xx_t             duart[2];       /* DUART */
 688         u8                      res2[0x900];
 689         fsl_lbc_t               im_lbc;         /* Local Bus Controller Regs */
 690         u8                      res3[0x1000];
 691         spi8xxx_t               spi;            /* Serial Peripheral Interface */
 692         dma83xx_t               dma;            /* DMA */
 693         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 694         u8                      res4[0x80];
 695         ios83xx_t               ios;            /* Sequencer */
 696         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 697         u8                      res5[0x1aa00];
 698         usb83xx_t               usb[1];
 699         tsec83xx_t              tsec[2];
 700         u8                      res6[0xA000];
 701         security83xx_t          security;
 702         u8                      res7[0xC0000];
 703 } immap_t;
 704
 705 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 706 typedef struct immap {
 707         sysconf83xx_t           sysconf;        /* System configuration */
 708         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 709         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 710         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 711         gtm83xx_t               gtm[2];         /* Global Timers Module */
 712         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 713         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 714         reset83xx_t             reset;          /* Reset Module */
 715         clk83xx_t               clk;            /* System Clock Module */
 716         pmc83xx_t               pmc;            /* Power Management Control Module */
 717         gpio83xx_t              gpio[1];        /* General purpose I/O module */
 718         u8                      res0[0x1300];
 719         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 720         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 721         u8                      res1[0x1300];
 722         duart83xx_t             duart[2];       /* DUART */
 723         u8                      res2[0x900];
 724         fsl_lbc_t               im_lbc;         /* Local Bus Controller Regs */
 725         u8                      res3[0x1000];
 726         spi8xxx_t               spi;            /* Serial Peripheral Interface */
 727         dma83xx_t               dma;            /* DMA */
 728         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 729         u8                      res4[0x80];
 730         ios83xx_t               ios;            /* Sequencer */
 731         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 732         u8                      res5[0xa00];
 733         pex83xx_t               pciexp[2];      /* PCI Express Controller */
 734         u8                      res6[0xb000];
 735         tdm83xx_t               tdm;            /* TDM Controller */
 736         u8                      res7[0x1e00];
 737         sata83xx_t              sata[2];        /* SATA Controller */
 738         u8                      res8[0x9000];
 739         usb83xx_t               usb[1];         /* USB DR Controller */
 740         tsec83xx_t              tsec[2];
 741         u8                      res9[0x6000];
 742         tdmdmac83xx_t           tdmdmac;        /* TDM DMAC */
 743         u8                      res10[0x2000];
 744         security83xx_t          security;
 745         u8                      res11[0xA3000];
 746         serdes83xx_t            serdes[1];      /* SerDes Registers */
 747         u8                      res12[0x1CF00];
 748 } immap_t;
 749
 750 #elif defined(CONFIG_MPC837x)
 751 typedef struct immap {
 752         sysconf83xx_t           sysconf;        /* System configuration */
 753         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 754         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 755         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 756         gtm83xx_t               gtm[2];         /* Global Timers Module */
 757         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 758         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 759         reset83xx_t             reset;          /* Reset Module */
 760         clk83xx_t               clk;            /* System Clock Module */
 761         pmc83xx_t               pmc;            /* Power Management Control Module */
 762         gpio83xx_t              gpio[2];        /* General purpose I/O module */
 763         u8                      res0[0x1200];
 764         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 765         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 766         u8                      res1[0x1300];
 767         duart83xx_t             duart[2];       /* DUART */
 768         u8                      res2[0x900];
 769         fsl_lbc_t               im_lbc;         /* Local Bus Controller Regs */
 770         u8                      res3[0x1000];
 771         spi8xxx_t               spi;            /* Serial Peripheral Interface */
 772         dma83xx_t               dma;            /* DMA */
 773         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 774         u8                      res4[0x80];
 775         ios83xx_t               ios;            /* Sequencer */
 776         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 777         u8                      res5[0xa00];
 778         pex83xx_t               pciexp[2];      /* PCI Express Controller */
 779         u8                      res6[0xd000];
 780         sata83xx_t              sata[4];        /* SATA Controller */
 781         u8                      res7[0x7000];
 782         usb83xx_t               usb[1];         /* USB DR Controller */
 783         tsec83xx_t              tsec[2];
 784         u8                      res8[0x8000];
 785         sdhc83xx_t              sdhc;           /* SDHC Controller */
 786         u8                      res9[0x1000];
 787         security83xx_t          security;
 788         u8                      res10[0xA3000];
 789         serdes83xx_t            serdes[2];      /* SerDes Registers */
 790         u8                      res11[0xCE00];
 791         rom83xx_t               rom;            /* On Chip ROM */
 792 } immap_t;
 793
 794 #elif defined(CONFIG_MPC8360)
 795 typedef struct immap {
 796         sysconf83xx_t           sysconf;        /* System configuration */
 797         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 798         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 799         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 800         u8                      res0[0x200];
 801         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 802         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 803         reset83xx_t             reset;          /* Reset Module */
 804         clk83xx_t               clk;            /* System Clock Module */
 805         pmc83xx_t               pmc;            /* Power Management Control Module */
 806         qepi83xx_t              qepi;           /* QE Ports Interrupts Registers */
 807         u8                      res1[0x300];
 808         u8                      dll_ddr[0x100];
 809         u8                      dll_lbc[0x100];
 810         u8                      res2[0x200];
 811         qepio83xx_t             qepio;          /* QE Parallel I/O ports */
 812         qesba83xx_t             qesba;          /* QE Secondary Bus Access Windows */
 813         u8                      res3[0x400];
 814         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 815         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 816         u8                      res4[0x1300];
 817         duart83xx_t             duart[2];       /* DUART */
 818         u8                      res5[0x900];
 819         fsl_lbc_t               im_lbc;         /* Local Bus Controller Regs */
 820         u8                      res6[0x2000];
 821         dma83xx_t               dma;            /* DMA */
 822         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 823         u8                      res7[128];
 824         ios83xx_t               ios;            /* Sequencer (IOS) */
 825         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 826         u8                      res8[0x4A00];
 827         ddr83xx_t               ddr_secondary;  /* Secondary DDR Memory Controller Memory Map */
 828         u8                      res9[0x22000];
 829         security83xx_t          security;
 830         u8                      res10[0xC0000];
 831         u8                      qe[0x100000];   /* QE block */
 832 } immap_t;
 833
 834 #elif defined(CONFIG_MPC832x)
 835 typedef struct immap {
 836         sysconf83xx_t           sysconf;        /* System configuration */
 837         wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */
 838         rtclk83xx_t             rtc;            /* Real Time Clock Module Registers */
 839         rtclk83xx_t             pit;            /* Periodic Interval Timer */
 840         gtm83xx_t               gtm[2];         /* Global Timers Module */
 841         ipic83xx_t              ipic;           /* Integrated Programmable Interrupt Controller */
 842         arbiter83xx_t           arbiter;        /* System Arbiter Registers */
 843         reset83xx_t             reset;          /* Reset Module */
 844         clk83xx_t               clk;            /* System Clock Module */
 845         pmc83xx_t               pmc;            /* Power Management Control Module */
 846         qepi83xx_t              qepi;           /* QE Ports Interrupts Registers */
 847         u8                      res0[0x300];
 848         u8                      dll_ddr[0x100];
 849         u8                      dll_lbc[0x100];
 850         u8                      res1[0x200];
 851         qepio83xx_t             qepio;          /* QE Parallel I/O ports */
 852         u8                      res2[0x800];
 853         ddr83xx_t               ddr;            /* DDR Memory Controller Memory */
 854         fsl_i2c_t               i2c[2];         /* I2C Controllers */
 855         u8                      res3[0x1300];
 856         duart83xx_t             duart[2];       /* DUART */
 857         u8                      res4[0x900];
 858         fsl_lbc_t               im_lbc;         /* Local Bus Controller Regs */
 859         u8                      res5[0x2000];
 860         dma83xx_t               dma;            /* DMA */
 861         pciconf83xx_t           pci_conf[1];    /* PCI Software Configuration Registers */
 862         u8                      res6[128];
 863         ios83xx_t               ios;            /* Sequencer (IOS) */
 864         pcictrl83xx_t           pci_ctrl[1];    /* PCI Controller Control and Status Registers */
 865         u8                      res7[0x27A00];
 866         security83xx_t          security;
 867         u8                      res8[0xC0000];
 868         u8                      qe[0x100000];   /* QE block */
 869 } immap_t;
 870 #endif
 871
 872 #define CONFIG_SYS_MPC83xx_DMA_OFFSET   (0x8000)
 873 #define CONFIG_SYS_MPC83xx_DMA_ADDR     (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
 874 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
 875 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
 876
 877 #ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
 878 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000
 879 #endif
 880 #define CONFIG_SYS_MPC83xx_USB_ADDR \
 881                         (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
 882 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 883
 884 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 885 #define CONFIG_SYS_MDIO1_OFFSET         0x24000
 886
 887 #define TSEC_BASE_ADDR          (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 888 #define MDIO_BASE_ADDR          (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 889 #endif                          /* __IMMAP_83xx__ */