2 * MPC85xx Internal Memory Map
4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #ifndef __IMMAP_85xx__
29 #define __IMMAP_85xx__
31 #include <asm/types.h>
32 #include <asm/fsl_dma.h>
33 #include <asm/fsl_i2c.h>
34 #include <asm/fsl_ifc.h>
35 #include <asm/fsl_lbc.h>
36 #include <asm/fsl_fman.h>
38 typedef struct ccsr_local
{
39 u32 ccsrbarh
; /* CCSR Base Addr High */
40 u32 ccsrbarl
; /* CCSR Base Addr Low */
41 u32 ccsrar
; /* CCSR Attr */
42 #define CCSRAR_C 0x80000000 /* Commit */
44 u32 altcbarh
; /* Alternate Configuration Base Addr High */
45 u32 altcbarl
; /* Alternate Configuration Base Addr Low */
46 u32 altcar
; /* Alternate Configuration Attr */
48 u32 bstrh
; /* Boot space translation high */
49 u32 bstrl
; /* Boot space translation Low */
50 u32 bstrar
; /* Boot space translation attributes */
53 u32 lawbarh
; /* LAWn base addr high */
54 u32 lawbarl
; /* LAWn base addr low */
55 u32 lawar
; /* LAWn attributes */
61 /* Local-Access Registers & ECM Registers */
62 typedef struct ccsr_local_ecm
{
63 u32 ccsrbar
; /* CCSR Base Addr */
65 u32 altcbar
; /* Alternate Configuration Base Addr */
67 u32 altcar
; /* Alternate Configuration Attr */
69 u32 bptr
; /* Boot Page Translation */
71 u32 lawbar0
; /* Local Access Window 0 Base Addr */
73 u32 lawar0
; /* Local Access Window 0 Attrs */
75 u32 lawbar1
; /* Local Access Window 1 Base Addr */
77 u32 lawar1
; /* Local Access Window 1 Attrs */
79 u32 lawbar2
; /* Local Access Window 2 Base Addr */
81 u32 lawar2
; /* Local Access Window 2 Attrs */
83 u32 lawbar3
; /* Local Access Window 3 Base Addr */
85 u32 lawar3
; /* Local Access Window 3 Attrs */
87 u32 lawbar4
; /* Local Access Window 4 Base Addr */
89 u32 lawar4
; /* Local Access Window 4 Attrs */
91 u32 lawbar5
; /* Local Access Window 5 Base Addr */
93 u32 lawar5
; /* Local Access Window 5 Attrs */
95 u32 lawbar6
; /* Local Access Window 6 Base Addr */
97 u32 lawar6
; /* Local Access Window 6 Attrs */
99 u32 lawbar7
; /* Local Access Window 7 Base Addr */
101 u32 lawar7
; /* Local Access Window 7 Attrs */
103 u32 lawbar8
; /* Local Access Window 8 Base Addr */
105 u32 lawar8
; /* Local Access Window 8 Attrs */
107 u32 lawbar9
; /* Local Access Window 9 Base Addr */
109 u32 lawar9
; /* Local Access Window 9 Attrs */
111 u32 lawbar10
; /* Local Access Window 10 Base Addr */
113 u32 lawar10
; /* Local Access Window 10 Attrs */
115 u32 lawbar11
; /* Local Access Window 11 Base Addr */
117 u32 lawar11
; /* Local Access Window 11 Attrs */
119 u32 eebacr
; /* ECM CCB Addr Configuration */
121 u32 eebpcr
; /* ECM CCB Port Configuration */
123 u32 eedr
; /* ECM Error Detect */
125 u32 eeer
; /* ECM Error Enable */
126 u32 eeatr
; /* ECM Error Attrs Capture */
127 u32 eeadr
; /* ECM Error Addr Capture */
131 /* DDR memory controller registers */
132 typedef struct ccsr_ddr
{
133 u32 cs0_bnds
; /* Chip Select 0 Memory Bounds */
135 u32 cs1_bnds
; /* Chip Select 1 Memory Bounds */
137 u32 cs2_bnds
; /* Chip Select 2 Memory Bounds */
139 u32 cs3_bnds
; /* Chip Select 3 Memory Bounds */
141 u32 cs0_config
; /* Chip Select Configuration */
142 u32 cs1_config
; /* Chip Select Configuration */
143 u32 cs2_config
; /* Chip Select Configuration */
144 u32 cs3_config
; /* Chip Select Configuration */
146 u32 cs0_config_2
; /* Chip Select Configuration 2 */
147 u32 cs1_config_2
; /* Chip Select Configuration 2 */
148 u32 cs2_config_2
; /* Chip Select Configuration 2 */
149 u32 cs3_config_2
; /* Chip Select Configuration 2 */
151 u32 timing_cfg_3
; /* SDRAM Timing Configuration 3 */
152 u32 timing_cfg_0
; /* SDRAM Timing Configuration 0 */
153 u32 timing_cfg_1
; /* SDRAM Timing Configuration 1 */
154 u32 timing_cfg_2
; /* SDRAM Timing Configuration 2 */
155 u32 sdram_cfg
; /* SDRAM Control Configuration */
156 u32 sdram_cfg_2
; /* SDRAM Control Configuration 2 */
157 u32 sdram_mode
; /* SDRAM Mode Configuration */
158 u32 sdram_mode_2
; /* SDRAM Mode Configuration 2 */
159 u32 sdram_md_cntl
; /* SDRAM Mode Control */
160 u32 sdram_interval
; /* SDRAM Interval Configuration */
161 u32 sdram_data_init
; /* SDRAM Data initialization */
163 u32 sdram_clk_cntl
; /* SDRAM Clock Control */
165 u32 init_addr
; /* training init addr */
166 u32 init_ext_addr
; /* training init extended addr */
168 u32 timing_cfg_4
; /* SDRAM Timing Configuration 4 */
169 u32 timing_cfg_5
; /* SDRAM Timing Configuration 5 */
171 u32 ddr_zq_cntl
; /* ZQ calibration control*/
172 u32 ddr_wrlvl_cntl
; /* write leveling control*/
174 u32 ddr_sr_cntr
; /* self refresh counter */
175 u32 ddr_sdram_rcw_1
; /* Control Words 1 */
176 u32 ddr_sdram_rcw_2
; /* Control Words 2 */
178 u32 ddr_wrlvl_cntl_2
; /* write leveling control 2 */
179 u32 ddr_wrlvl_cntl_3
; /* write leveling control 3 */
181 u32 sdram_mode_3
; /* SDRAM Mode Configuration 3 */
182 u32 sdram_mode_4
; /* SDRAM Mode Configuration 4 */
183 u32 sdram_mode_5
; /* SDRAM Mode Configuration 5 */
184 u32 sdram_mode_6
; /* SDRAM Mode Configuration 6 */
185 u32 sdram_mode_7
; /* SDRAM Mode Configuration 7 */
186 u32 sdram_mode_8
; /* SDRAM Mode Configuration 8 */
188 u32 ddr_dsr1
; /* Debug Status 1 */
189 u32 ddr_dsr2
; /* Debug Status 2 */
190 u32 ddr_cdr1
; /* Control Driver 1 */
191 u32 ddr_cdr2
; /* Control Driver 2 */
193 u32 ip_rev1
; /* IP Block Revision 1 */
194 u32 ip_rev2
; /* IP Block Revision 2 */
195 u32 eor
; /* Enhanced Optimization Register */
197 u32 mtcr
; /* Memory Test Control Register */
199 u32 mtp1
; /* Memory Test Pattern 1 */
200 u32 mtp2
; /* Memory Test Pattern 2 */
201 u32 mtp3
; /* Memory Test Pattern 3 */
202 u32 mtp4
; /* Memory Test Pattern 4 */
203 u32 mtp5
; /* Memory Test Pattern 5 */
204 u32 mtp6
; /* Memory Test Pattern 6 */
205 u32 mtp7
; /* Memory Test Pattern 7 */
206 u32 mtp8
; /* Memory Test Pattern 8 */
207 u32 mtp9
; /* Memory Test Pattern 9 */
208 u32 mtp10
; /* Memory Test Pattern 10 */
210 u32 data_err_inject_hi
; /* Data Path Err Injection Mask High */
211 u32 data_err_inject_lo
; /* Data Path Err Injection Mask Low */
212 u32 ecc_err_inject
; /* Data Path Err Injection Mask ECC */
214 u32 capture_data_hi
; /* Data Path Read Capture High */
215 u32 capture_data_lo
; /* Data Path Read Capture Low */
216 u32 capture_ecc
; /* Data Path Read Capture ECC */
218 u32 err_detect
; /* Error Detect */
219 u32 err_disable
; /* Error Disable */
221 u32 capture_attributes
; /* Error Attrs Capture */
222 u32 capture_address
; /* Error Addr Capture */
223 u32 capture_ext_address
; /* Error Extended Addr Capture */
224 u32 err_sbe
; /* Single-Bit ECC Error Management */
226 u32 debug
[32]; /* debug_1 to debug_32 */
230 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
231 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
234 typedef struct ccsr_i2c
{
235 struct fsl_i2c i2c
[1];
236 u8 res
[4096 - 1 * sizeof(struct fsl_i2c
)];
239 #if defined(CONFIG_MPC8540) \
240 || defined(CONFIG_MPC8541) \
241 || defined(CONFIG_MPC8548) \
242 || defined(CONFIG_MPC8555)
243 /* DUART Registers */
244 typedef struct ccsr_duart
{
246 /* URBR1, UTHR1, UDLB1 with the same addr */
247 u8 urbr1_uthr1_udlb1
;
248 /* UIER1, UDMB1 with the same addr01 */
250 /* UIIR1, UFCR1, UAFR1 with the same addr */
251 u8 uiir1_ufcr1_uafr1
;
252 u8 ulcr1
; /* UART1 Line Control */
253 u8 umcr1
; /* UART1 Modem Control */
254 u8 ulsr1
; /* UART1 Line Status */
255 u8 umsr1
; /* UART1 Modem Status */
256 u8 uscr1
; /* UART1 Scratch */
258 u8 udsr1
; /* UART1 DMA Status */
260 /* URBR2, UTHR2, UDLB2 with the same addr */
261 u8 urbr2_uthr2_udlb2
;
262 /* UIER2, UDMB2 with the same addr */
264 /* UIIR2, UFCR2, UAFR2 with the same addr */
265 u8 uiir2_ufcr2_uafr2
;
266 u8 ulcr2
; /* UART2 Line Control */
267 u8 umcr2
; /* UART2 Modem Control */
268 u8 ulsr2
; /* UART2 Line Status */
269 u8 umsr2
; /* UART2 Modem Status */
270 u8 uscr2
; /* UART2 Scratch */
272 u8 udsr2
; /* UART2 DMA Status */
275 #else /* MPC8560 uses UART on its CPM */
276 typedef struct ccsr_duart
{
282 typedef struct ccsr_espi
{
283 u32 mode
; /* eSPI mode */
284 u32 event
; /* eSPI event */
285 u32 mask
; /* eSPI mask */
286 u32 com
; /* eSPI command */
287 u32 tx
; /* eSPI transmit FIFO access */
288 u32 rx
; /* eSPI receive FIFO access */
289 u8 res1
[8]; /* reserved */
290 u32 csmode
[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
291 u8 res2
[4048]; /* fill up to 0x1000 */
295 typedef struct ccsr_pcix
{
296 u32 cfg_addr
; /* PCIX Configuration Addr */
297 u32 cfg_data
; /* PCIX Configuration Data */
298 u32 int_ack
; /* PCIX IRQ Acknowledge */
300 u32 potar0
; /* PCIX Outbound Transaction Addr 0 */
301 u32 potear0
; /* PCIX Outbound Translation Extended Addr 0 */
302 u32 powbar0
; /* PCIX Outbound Window Base Addr 0 */
303 u32 powbear0
; /* PCIX Outbound Window Base Extended Addr 0 */
304 u32 powar0
; /* PCIX Outbound Window Attrs 0 */
306 u32 potar1
; /* PCIX Outbound Transaction Addr 1 */
307 u32 potear1
; /* PCIX Outbound Translation Extended Addr 1 */
308 u32 powbar1
; /* PCIX Outbound Window Base Addr 1 */
309 u32 powbear1
; /* PCIX Outbound Window Base Extended Addr 1 */
310 u32 powar1
; /* PCIX Outbound Window Attrs 1 */
312 u32 potar2
; /* PCIX Outbound Transaction Addr 2 */
313 u32 potear2
; /* PCIX Outbound Translation Extended Addr 2 */
314 u32 powbar2
; /* PCIX Outbound Window Base Addr 2 */
315 u32 powbear2
; /* PCIX Outbound Window Base Extended Addr 2 */
316 u32 powar2
; /* PCIX Outbound Window Attrs 2 */
318 u32 potar3
; /* PCIX Outbound Transaction Addr 3 */
319 u32 potear3
; /* PCIX Outbound Translation Extended Addr 3 */
320 u32 powbar3
; /* PCIX Outbound Window Base Addr 3 */
321 u32 powbear3
; /* PCIX Outbound Window Base Extended Addr 3 */
322 u32 powar3
; /* PCIX Outbound Window Attrs 3 */
324 u32 potar4
; /* PCIX Outbound Transaction Addr 4 */
325 u32 potear4
; /* PCIX Outbound Translation Extended Addr 4 */
326 u32 powbar4
; /* PCIX Outbound Window Base Addr 4 */
327 u32 powbear4
; /* PCIX Outbound Window Base Extended Addr 4 */
328 u32 powar4
; /* PCIX Outbound Window Attrs 4 */
330 u32 pitar3
; /* PCIX Inbound Translation Addr 3 */
331 u32 pitear3
; /* PCIX Inbound Translation Extended Addr 3 */
332 u32 piwbar3
; /* PCIX Inbound Window Base Addr 3 */
333 u32 piwbear3
; /* PCIX Inbound Window Base Extended Addr 3 */
334 u32 piwar3
; /* PCIX Inbound Window Attrs 3 */
336 u32 pitar2
; /* PCIX Inbound Translation Addr 2 */
337 u32 pitear2
; /* PCIX Inbound Translation Extended Addr 2 */
338 u32 piwbar2
; /* PCIX Inbound Window Base Addr 2 */
339 u32 piwbear2
; /* PCIX Inbound Window Base Extended Addr 2 */
340 u32 piwar2
; /* PCIX Inbound Window Attrs 2 */
342 u32 pitar1
; /* PCIX Inbound Translation Addr 1 */
343 u32 pitear1
; /* PCIX Inbound Translation Extended Addr 1 */
344 u32 piwbar1
; /* PCIX Inbound Window Base Addr 1 */
346 u32 piwar1
; /* PCIX Inbound Window Attrs 1 */
348 u32 pedr
; /* PCIX Error Detect */
349 u32 pecdr
; /* PCIX Error Capture Disable */
350 u32 peer
; /* PCIX Error Enable */
351 u32 peattrcr
; /* PCIX Error Attrs Capture */
352 u32 peaddrcr
; /* PCIX Error Addr Capture */
353 u32 peextaddrcr
; /* PCIX Error Extended Addr Capture */
354 u32 pedlcr
; /* PCIX Error Data Low Capture */
355 u32 pedhcr
; /* PCIX Error Error Data High Capture */
356 u32 gas_timr
; /* PCIX Gasket Timer */
360 #define PCIX_COMMAND 0x62
361 #define POWAR_EN 0x80000000
362 #define POWAR_IO_READ 0x00080000
363 #define POWAR_MEM_READ 0x00040000
364 #define POWAR_IO_WRITE 0x00008000
365 #define POWAR_MEM_WRITE 0x00004000
366 #define POWAR_MEM_512M 0x0000001c
367 #define POWAR_IO_1M 0x00000013
369 #define PIWAR_EN 0x80000000
370 #define PIWAR_PF 0x20000000
371 #define PIWAR_LOCAL 0x00f00000
372 #define PIWAR_READ_SNOOP 0x00050000
373 #define PIWAR_WRITE_SNOOP 0x00005000
374 #define PIWAR_MEM_2G 0x0000001e
376 typedef struct ccsr_gpio
{
385 /* L2 Cache Registers */
386 typedef struct ccsr_l2cache
{
387 u32 l2ctl
; /* L2 configuration 0 */
389 u32 l2cewar0
; /* L2 cache external write addr 0 */
391 u32 l2cewcr0
; /* L2 cache external write control 0 */
393 u32 l2cewar1
; /* L2 cache external write addr 1 */
395 u32 l2cewcr1
; /* L2 cache external write control 1 */
397 u32 l2cewar2
; /* L2 cache external write addr 2 */
399 u32 l2cewcr2
; /* L2 cache external write control 2 */
401 u32 l2cewar3
; /* L2 cache external write addr 3 */
403 u32 l2cewcr3
; /* L2 cache external write control 3 */
405 u32 l2srbar0
; /* L2 memory-mapped SRAM base addr 0 */
407 u32 l2srbar1
; /* L2 memory-mapped SRAM base addr 1 */
409 u32 l2errinjhi
; /* L2 error injection mask high */
410 u32 l2errinjlo
; /* L2 error injection mask low */
411 u32 l2errinjctl
; /* L2 error injection tag/ECC control */
413 u32 l2captdatahi
; /* L2 error data high capture */
414 u32 l2captdatalo
; /* L2 error data low capture */
415 u32 l2captecc
; /* L2 error ECC capture */
417 u32 l2errdet
; /* L2 error detect */
418 u32 l2errdis
; /* L2 error disable */
419 u32 l2errinten
; /* L2 error interrupt enable */
420 u32 l2errattr
; /* L2 error attributes capture */
421 u32 l2erraddr
; /* L2 error addr capture */
423 u32 l2errctl
; /* L2 error control */
427 #define MPC85xx_L2CTL_L2E 0x80000000
428 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
429 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
430 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
433 typedef struct ccsr_dma
{
435 struct fsl_dma dma
[4];
436 u32 dgsr
; /* DMA General Status */
441 typedef struct ccsr_tsec
{
443 u32 ievent
; /* IRQ Event */
444 u32 imask
; /* IRQ Mask */
445 u32 edis
; /* Error Disabled */
447 u32 ecntrl
; /* Ethernet Control */
448 u32 minflr
; /* Minimum Frame Len */
449 u32 ptv
; /* Pause Time Value */
450 u32 dmactrl
; /* DMA Control */
451 u32 tbipa
; /* TBI PHY Addr */
453 u32 fifo_tx_thr
; /* FIFO transmit threshold */
455 u32 fifo_tx_starve
; /* FIFO transmit starve */
456 u32 fifo_tx_starve_shutoff
; /* FIFO transmit starve shutoff */
458 u32 tctrl
; /* TX Control */
459 u32 tstat
; /* TX Status */
461 u32 tbdlen
; /* TX Buffer Desc Data Len */
463 u32 ctbptrh
; /* Current TX Buffer Desc Ptr High */
464 u32 ctbptr
; /* Current TX Buffer Desc Ptr */
466 u32 tbptrh
; /* TX Buffer Desc Ptr High */
467 u32 tbptr
; /* TX Buffer Desc Ptr Low */
469 u32 tbaseh
; /* TX Desc Base Addr High */
470 u32 tbase
; /* TX Desc Base Addr */
472 u32 ostbd
; /* Out-of-Sequence(OOS) TX Buffer Desc */
473 u32 ostbdp
; /* OOS TX Data Buffer Ptr */
474 u32 os32tbdp
; /* OOS 32 Bytes TX Data Buffer Ptr Low */
475 u32 os32iptrh
; /* OOS 32 Bytes TX Insert Ptr High */
476 u32 os32iptrl
; /* OOS 32 Bytes TX Insert Ptr Low */
477 u32 os32tbdr
; /* OOS 32 Bytes TX Reserved */
478 u32 os32iil
; /* OOS 32 Bytes TX Insert Idx/Len */
480 u32 rctrl
; /* RX Control */
481 u32 rstat
; /* RX Status */
483 u32 rbdlen
; /* RxBD Data Len */
485 u32 crbptrh
; /* Current RX Buffer Desc Ptr High */
486 u32 crbptr
; /* Current RX Buffer Desc Ptr */
488 u32 mrblr
; /* Maximum RX Buffer Len */
489 u32 mrblr2r3
; /* Maximum RX Buffer Len R2R3 */
491 u32 rbptrh
; /* RX Buffer Desc Ptr High 0 */
492 u32 rbptr
; /* RX Buffer Desc Ptr */
493 u32 rbptrh1
; /* RX Buffer Desc Ptr High 1 */
494 u32 rbptrl1
; /* RX Buffer Desc Ptr Low 1 */
495 u32 rbptrh2
; /* RX Buffer Desc Ptr High 2 */
496 u32 rbptrl2
; /* RX Buffer Desc Ptr Low 2 */
497 u32 rbptrh3
; /* RX Buffer Desc Ptr High 3 */
498 u32 rbptrl3
; /* RX Buffer Desc Ptr Low 3 */
500 u32 rbaseh
; /* RX Desc Base Addr High 0 */
501 u32 rbase
; /* RX Desc Base Addr */
502 u32 rbaseh1
; /* RX Desc Base Addr High 1 */
503 u32 rbasel1
; /* RX Desc Base Addr Low 1 */
504 u32 rbaseh2
; /* RX Desc Base Addr High 2 */
505 u32 rbasel2
; /* RX Desc Base Addr Low 2 */
506 u32 rbaseh3
; /* RX Desc Base Addr High 3 */
507 u32 rbasel3
; /* RX Desc Base Addr Low 3 */
509 u32 maccfg1
; /* MAC Configuration 1 */
510 u32 maccfg2
; /* MAC Configuration 2 */
511 u32 ipgifg
; /* Inter Packet Gap/Inter Frame Gap */
512 u32 hafdup
; /* Half Duplex */
513 u32 maxfrm
; /* Maximum Frame Len */
515 u32 miimcfg
; /* MII Management Configuration */
516 u32 miimcom
; /* MII Management Cmd */
517 u32 miimadd
; /* MII Management Addr */
518 u32 miimcon
; /* MII Management Control */
519 u32 miimstat
; /* MII Management Status */
520 u32 miimind
; /* MII Management Indicator */
522 u32 ifstat
; /* Interface Status */
523 u32 macstnaddr1
; /* Station Addr Part 1 */
524 u32 macstnaddr2
; /* Station Addr Part 2 */
526 u32 tr64
; /* TX & RX 64-byte Frame Counter */
527 u32 tr127
; /* TX & RX 65-127 byte Frame Counter */
528 u32 tr255
; /* TX & RX 128-255 byte Frame Counter */
529 u32 tr511
; /* TX & RX 256-511 byte Frame Counter */
530 u32 tr1k
; /* TX & RX 512-1023 byte Frame Counter */
531 u32 trmax
; /* TX & RX 1024-1518 byte Frame Counter */
532 u32 trmgv
; /* TX & RX 1519-1522 byte Good VLAN Frame */
533 u32 rbyt
; /* RX Byte Counter */
534 u32 rpkt
; /* RX Packet Counter */
535 u32 rfcs
; /* RX FCS Error Counter */
536 u32 rmca
; /* RX Multicast Packet Counter */
537 u32 rbca
; /* RX Broadcast Packet Counter */
538 u32 rxcf
; /* RX Control Frame Packet Counter */
539 u32 rxpf
; /* RX Pause Frame Packet Counter */
540 u32 rxuo
; /* RX Unknown OP Code Counter */
541 u32 raln
; /* RX Alignment Error Counter */
542 u32 rflr
; /* RX Frame Len Error Counter */
543 u32 rcde
; /* RX Code Error Counter */
544 u32 rcse
; /* RX Carrier Sense Error Counter */
545 u32 rund
; /* RX Undersize Packet Counter */
546 u32 rovr
; /* RX Oversize Packet Counter */
547 u32 rfrg
; /* RX Fragments Counter */
548 u32 rjbr
; /* RX Jabber Counter */
549 u32 rdrp
; /* RX Drop Counter */
550 u32 tbyt
; /* TX Byte Counter Counter */
551 u32 tpkt
; /* TX Packet Counter */
552 u32 tmca
; /* TX Multicast Packet Counter */
553 u32 tbca
; /* TX Broadcast Packet Counter */
554 u32 txpf
; /* TX Pause Control Frame Counter */
555 u32 tdfr
; /* TX Deferral Packet Counter */
556 u32 tedf
; /* TX Excessive Deferral Packet Counter */
557 u32 tscl
; /* TX Single Collision Packet Counter */
558 u32 tmcl
; /* TX Multiple Collision Packet Counter */
559 u32 tlcl
; /* TX Late Collision Packet Counter */
560 u32 txcl
; /* TX Excessive Collision Packet Counter */
561 u32 tncl
; /* TX Total Collision Counter */
563 u32 tdrp
; /* TX Drop Frame Counter */
564 u32 tjbr
; /* TX Jabber Frame Counter */
565 u32 tfcs
; /* TX FCS Error Counter */
566 u32 txcf
; /* TX Control Frame Counter */
567 u32 tovr
; /* TX Oversize Frame Counter */
568 u32 tund
; /* TX Undersize Frame Counter */
569 u32 tfrg
; /* TX Fragments Frame Counter */
570 u32 car1
; /* Carry One */
571 u32 car2
; /* Carry Two */
572 u32 cam1
; /* Carry Mask One */
573 u32 cam2
; /* Carry Mask Two */
575 u32 iaddr0
; /* Indivdual addr 0 */
576 u32 iaddr1
; /* Indivdual addr 1 */
577 u32 iaddr2
; /* Indivdual addr 2 */
578 u32 iaddr3
; /* Indivdual addr 3 */
579 u32 iaddr4
; /* Indivdual addr 4 */
580 u32 iaddr5
; /* Indivdual addr 5 */
581 u32 iaddr6
; /* Indivdual addr 6 */
582 u32 iaddr7
; /* Indivdual addr 7 */
584 u32 gaddr0
; /* Global addr 0 */
585 u32 gaddr1
; /* Global addr 1 */
586 u32 gaddr2
; /* Global addr 2 */
587 u32 gaddr3
; /* Global addr 3 */
588 u32 gaddr4
; /* Global addr 4 */
589 u32 gaddr5
; /* Global addr 5 */
590 u32 gaddr6
; /* Global addr 6 */
591 u32 gaddr7
; /* Global addr 7 */
593 u32 pmd0
; /* Pattern Match Data */
595 u32 pmask0
; /* Pattern Mask */
597 u32 pcntrl0
; /* Pattern Match Control */
599 u32 pattrb0
; /* Pattern Match Attrs */
600 u32 pattrbeli0
; /* Pattern Match Attrs Extract Len & Idx */
601 u32 pmd1
; /* Pattern Match Data */
603 u32 pmask1
; /* Pattern Mask */
605 u32 pcntrl1
; /* Pattern Match Control */
607 u32 pattrb1
; /* Pattern Match Attrs */
608 u32 pattrbeli1
; /* Pattern Match Attrs Extract Len & Idx */
609 u32 pmd2
; /* Pattern Match Data */
611 u32 pmask2
; /* Pattern Mask */
613 u32 pcntrl2
; /* Pattern Match Control */
615 u32 pattrb2
; /* Pattern Match Attrs */
616 u32 pattrbeli2
; /* Pattern Match Attrs Extract Len & Idx */
617 u32 pmd3
; /* Pattern Match Data */
619 u32 pmask3
; /* Pattern Mask */
621 u32 pcntrl3
; /* Pattern Match Control */
623 u32 pattrb3
; /* Pattern Match Attrs */
624 u32 pattrbeli3
; /* Pattern Match Attrs Extract Len & Idx */
625 u32 pmd4
; /* Pattern Match Data */
627 u32 pmask4
; /* Pattern Mask */
629 u32 pcntrl4
; /* Pattern Match Control */
631 u32 pattrb4
; /* Pattern Match Attrs */
632 u32 pattrbeli4
; /* Pattern Match Attrs Extract Len & Idx */
633 u32 pmd5
; /* Pattern Match Data */
635 u32 pmask5
; /* Pattern Mask */
637 u32 pcntrl5
; /* Pattern Match Control */
639 u32 pattrb5
; /* Pattern Match Attrs */
640 u32 pattrbeli5
; /* Pattern Match Attrs Extract Len & Idx */
641 u32 pmd6
; /* Pattern Match Data */
643 u32 pmask6
; /* Pattern Mask */
645 u32 pcntrl6
; /* Pattern Match Control */
647 u32 pattrb6
; /* Pattern Match Attrs */
648 u32 pattrbeli6
; /* Pattern Match Attrs Extract Len & Idx */
649 u32 pmd7
; /* Pattern Match Data */
651 u32 pmask7
; /* Pattern Mask */
653 u32 pcntrl7
; /* Pattern Match Control */
655 u32 pattrb7
; /* Pattern Match Attrs */
656 u32 pattrbeli7
; /* Pattern Match Attrs Extract Len & Idx */
657 u32 pmd8
; /* Pattern Match Data */
659 u32 pmask8
; /* Pattern Mask */
661 u32 pcntrl8
; /* Pattern Match Control */
663 u32 pattrb8
; /* Pattern Match Attrs */
664 u32 pattrbeli8
; /* Pattern Match Attrs Extract Len & Idx */
665 u32 pmd9
; /* Pattern Match Data */
667 u32 pmask9
; /* Pattern Mask */
669 u32 pcntrl9
; /* Pattern Match Control */
671 u32 pattrb9
; /* Pattern Match Attrs */
672 u32 pattrbeli9
; /* Pattern Match Attrs Extract Len & Idx */
673 u32 pmd10
; /* Pattern Match Data */
675 u32 pmask10
; /* Pattern Mask */
677 u32 pcntrl10
; /* Pattern Match Control */
679 u32 pattrb10
; /* Pattern Match Attrs */
680 u32 pattrbeli10
; /* Pattern Match Attrs Extract Len & Idx */
681 u32 pmd11
; /* Pattern Match Data */
683 u32 pmask11
; /* Pattern Mask */
685 u32 pcntrl11
; /* Pattern Match Control */
687 u32 pattrb11
; /* Pattern Match Attrs */
688 u32 pattrbeli11
; /* Pattern Match Attrs Extract Len & Idx */
689 u32 pmd12
; /* Pattern Match Data */
691 u32 pmask12
; /* Pattern Mask */
693 u32 pcntrl12
; /* Pattern Match Control */
695 u32 pattrb12
; /* Pattern Match Attrs */
696 u32 pattrbeli12
; /* Pattern Match Attrs Extract Len & Idx */
697 u32 pmd13
; /* Pattern Match Data */
699 u32 pmask13
; /* Pattern Mask */
701 u32 pcntrl13
; /* Pattern Match Control */
703 u32 pattrb13
; /* Pattern Match Attrs */
704 u32 pattrbeli13
; /* Pattern Match Attrs Extract Len & Idx */
705 u32 pmd14
; /* Pattern Match Data */
707 u32 pmask14
; /* Pattern Mask */
709 u32 pcntrl14
; /* Pattern Match Control */
711 u32 pattrb14
; /* Pattern Match Attrs */
712 u32 pattrbeli14
; /* Pattern Match Attrs Extract Len & Idx */
713 u32 pmd15
; /* Pattern Match Data */
715 u32 pmask15
; /* Pattern Mask */
717 u32 pcntrl15
; /* Pattern Match Control */
719 u32 pattrb15
; /* Pattern Match Attrs */
720 u32 pattrbeli15
; /* Pattern Match Attrs Extract Len & Idx */
722 u32 attr
; /* Attrs */
723 u32 attreli
; /* Attrs Extract Len & Idx */
728 typedef struct ccsr_pic
{
730 u32 ipidr0
; /* Interprocessor IRQ Dispatch 0 */
732 u32 ipidr1
; /* Interprocessor IRQ Dispatch 1 */
734 u32 ipidr2
; /* Interprocessor IRQ Dispatch 2 */
736 u32 ipidr3
; /* Interprocessor IRQ Dispatch 3 */
738 u32 ctpr
; /* Current Task Priority */
740 u32 whoami
; /* Who Am I */
742 u32 iack
; /* IRQ Acknowledge */
744 u32 eoi
; /* End Of IRQ */
746 u32 frr
; /* Feature Reporting */
748 u32 gcr
; /* Global Configuration */
749 #define MPC85xx_PICGCR_RST 0x80000000
750 #define MPC85xx_PICGCR_M 0x20000000
752 u32 vir
; /* Vendor Identification */
754 u32 pir
; /* Processor Initialization */
756 u32 ipivpr0
; /* IPI Vector/Priority 0 */
758 u32 ipivpr1
; /* IPI Vector/Priority 1 */
760 u32 ipivpr2
; /* IPI Vector/Priority 2 */
762 u32 ipivpr3
; /* IPI Vector/Priority 3 */
764 u32 svr
; /* Spurious Vector */
766 u32 tfrr
; /* Timer Frequency Reporting */
768 u32 gtccr0
; /* Global Timer Current Count 0 */
770 u32 gtbcr0
; /* Global Timer Base Count 0 */
772 u32 gtvpr0
; /* Global Timer Vector/Priority 0 */
774 u32 gtdr0
; /* Global Timer Destination 0 */
776 u32 gtccr1
; /* Global Timer Current Count 1 */
778 u32 gtbcr1
; /* Global Timer Base Count 1 */
780 u32 gtvpr1
; /* Global Timer Vector/Priority 1 */
782 u32 gtdr1
; /* Global Timer Destination 1 */
784 u32 gtccr2
; /* Global Timer Current Count 2 */
786 u32 gtbcr2
; /* Global Timer Base Count 2 */
788 u32 gtvpr2
; /* Global Timer Vector/Priority 2 */
790 u32 gtdr2
; /* Global Timer Destination 2 */
792 u32 gtccr3
; /* Global Timer Current Count 3 */
794 u32 gtbcr3
; /* Global Timer Base Count 3 */
796 u32 gtvpr3
; /* Global Timer Vector/Priority 3 */
798 u32 gtdr3
; /* Global Timer Destination 3 */
800 u32 tcr
; /* Timer Control */
802 u32 irqsr0
; /* IRQ_OUT Summary 0 */
804 u32 irqsr1
; /* IRQ_OUT Summary 1 */
806 u32 cisr0
; /* Critical IRQ Summary 0 */
808 u32 cisr1
; /* Critical IRQ Summary 1 */
810 u32 msgr0
; /* Message 0 */
812 u32 msgr1
; /* Message 1 */
814 u32 msgr2
; /* Message 2 */
816 u32 msgr3
; /* Message 3 */
818 u32 mer
; /* Message Enable */
820 u32 msr
; /* Message Status */
822 u32 eivpr0
; /* External IRQ Vector/Priority 0 */
824 u32 eidr0
; /* External IRQ Destination 0 */
826 u32 eivpr1
; /* External IRQ Vector/Priority 1 */
828 u32 eidr1
; /* External IRQ Destination 1 */
830 u32 eivpr2
; /* External IRQ Vector/Priority 2 */
832 u32 eidr2
; /* External IRQ Destination 2 */
834 u32 eivpr3
; /* External IRQ Vector/Priority 3 */
836 u32 eidr3
; /* External IRQ Destination 3 */
838 u32 eivpr4
; /* External IRQ Vector/Priority 4 */
840 u32 eidr4
; /* External IRQ Destination 4 */
842 u32 eivpr5
; /* External IRQ Vector/Priority 5 */
844 u32 eidr5
; /* External IRQ Destination 5 */
846 u32 eivpr6
; /* External IRQ Vector/Priority 6 */
848 u32 eidr6
; /* External IRQ Destination 6 */
850 u32 eivpr7
; /* External IRQ Vector/Priority 7 */
852 u32 eidr7
; /* External IRQ Destination 7 */
854 u32 eivpr8
; /* External IRQ Vector/Priority 8 */
856 u32 eidr8
; /* External IRQ Destination 8 */
858 u32 eivpr9
; /* External IRQ Vector/Priority 9 */
860 u32 eidr9
; /* External IRQ Destination 9 */
862 u32 eivpr10
; /* External IRQ Vector/Priority 10 */
864 u32 eidr10
; /* External IRQ Destination 10 */
866 u32 eivpr11
; /* External IRQ Vector/Priority 11 */
868 u32 eidr11
; /* External IRQ Destination 11 */
870 u32 iivpr0
; /* Internal IRQ Vector/Priority 0 */
872 u32 iidr0
; /* Internal IRQ Destination 0 */
874 u32 iivpr1
; /* Internal IRQ Vector/Priority 1 */
876 u32 iidr1
; /* Internal IRQ Destination 1 */
878 u32 iivpr2
; /* Internal IRQ Vector/Priority 2 */
880 u32 iidr2
; /* Internal IRQ Destination 2 */
882 u32 iivpr3
; /* Internal IRQ Vector/Priority 3 */
884 u32 iidr3
; /* Internal IRQ Destination 3 */
886 u32 iivpr4
; /* Internal IRQ Vector/Priority 4 */
888 u32 iidr4
; /* Internal IRQ Destination 4 */
890 u32 iivpr5
; /* Internal IRQ Vector/Priority 5 */
892 u32 iidr5
; /* Internal IRQ Destination 5 */
894 u32 iivpr6
; /* Internal IRQ Vector/Priority 6 */
896 u32 iidr6
; /* Internal IRQ Destination 6 */
898 u32 iivpr7
; /* Internal IRQ Vector/Priority 7 */
900 u32 iidr7
; /* Internal IRQ Destination 7 */
902 u32 iivpr8
; /* Internal IRQ Vector/Priority 8 */
904 u32 iidr8
; /* Internal IRQ Destination 8 */
906 u32 iivpr9
; /* Internal IRQ Vector/Priority 9 */
908 u32 iidr9
; /* Internal IRQ Destination 9 */
910 u32 iivpr10
; /* Internal IRQ Vector/Priority 10 */
912 u32 iidr10
; /* Internal IRQ Destination 10 */
914 u32 iivpr11
; /* Internal IRQ Vector/Priority 11 */
916 u32 iidr11
; /* Internal IRQ Destination 11 */
918 u32 iivpr12
; /* Internal IRQ Vector/Priority 12 */
920 u32 iidr12
; /* Internal IRQ Destination 12 */
922 u32 iivpr13
; /* Internal IRQ Vector/Priority 13 */
924 u32 iidr13
; /* Internal IRQ Destination 13 */
926 u32 iivpr14
; /* Internal IRQ Vector/Priority 14 */
928 u32 iidr14
; /* Internal IRQ Destination 14 */
930 u32 iivpr15
; /* Internal IRQ Vector/Priority 15 */
932 u32 iidr15
; /* Internal IRQ Destination 15 */
934 u32 iivpr16
; /* Internal IRQ Vector/Priority 16 */
936 u32 iidr16
; /* Internal IRQ Destination 16 */
938 u32 iivpr17
; /* Internal IRQ Vector/Priority 17 */
940 u32 iidr17
; /* Internal IRQ Destination 17 */
942 u32 iivpr18
; /* Internal IRQ Vector/Priority 18 */
944 u32 iidr18
; /* Internal IRQ Destination 18 */
946 u32 iivpr19
; /* Internal IRQ Vector/Priority 19 */
948 u32 iidr19
; /* Internal IRQ Destination 19 */
950 u32 iivpr20
; /* Internal IRQ Vector/Priority 20 */
952 u32 iidr20
; /* Internal IRQ Destination 20 */
954 u32 iivpr21
; /* Internal IRQ Vector/Priority 21 */
956 u32 iidr21
; /* Internal IRQ Destination 21 */
958 u32 iivpr22
; /* Internal IRQ Vector/Priority 22 */
960 u32 iidr22
; /* Internal IRQ Destination 22 */
962 u32 iivpr23
; /* Internal IRQ Vector/Priority 23 */
964 u32 iidr23
; /* Internal IRQ Destination 23 */
966 u32 iivpr24
; /* Internal IRQ Vector/Priority 24 */
968 u32 iidr24
; /* Internal IRQ Destination 24 */
970 u32 iivpr25
; /* Internal IRQ Vector/Priority 25 */
972 u32 iidr25
; /* Internal IRQ Destination 25 */
974 u32 iivpr26
; /* Internal IRQ Vector/Priority 26 */
976 u32 iidr26
; /* Internal IRQ Destination 26 */
978 u32 iivpr27
; /* Internal IRQ Vector/Priority 27 */
980 u32 iidr27
; /* Internal IRQ Destination 27 */
982 u32 iivpr28
; /* Internal IRQ Vector/Priority 28 */
984 u32 iidr28
; /* Internal IRQ Destination 28 */
986 u32 iivpr29
; /* Internal IRQ Vector/Priority 29 */
988 u32 iidr29
; /* Internal IRQ Destination 29 */
990 u32 iivpr30
; /* Internal IRQ Vector/Priority 30 */
992 u32 iidr30
; /* Internal IRQ Destination 30 */
994 u32 iivpr31
; /* Internal IRQ Vector/Priority 31 */
996 u32 iidr31
; /* Internal IRQ Destination 31 */
998 u32 mivpr0
; /* Messaging IRQ Vector/Priority 0 */
1000 u32 midr0
; /* Messaging IRQ Destination 0 */
1002 u32 mivpr1
; /* Messaging IRQ Vector/Priority 1 */
1004 u32 midr1
; /* Messaging IRQ Destination 1 */
1006 u32 mivpr2
; /* Messaging IRQ Vector/Priority 2 */
1008 u32 midr2
; /* Messaging IRQ Destination 2 */
1010 u32 mivpr3
; /* Messaging IRQ Vector/Priority 3 */
1012 u32 midr3
; /* Messaging IRQ Destination 3 */
1014 u32 ipi0dr0
; /* Processor 0 Interprocessor IRQ Dispatch 0 */
1016 u32 ipi0dr1
; /* Processor 0 Interprocessor IRQ Dispatch 1 */
1018 u32 ipi0dr2
; /* Processor 0 Interprocessor IRQ Dispatch 2 */
1020 u32 ipi0dr3
; /* Processor 0 Interprocessor IRQ Dispatch 3 */
1022 u32 ctpr0
; /* Current Task Priority for Processor 0 */
1024 u32 whoami0
; /* Who Am I for Processor 0 */
1026 u32 iack0
; /* IRQ Acknowledge for Processor 0 */
1028 u32 eoi0
; /* End Of IRQ for Processor 0 */
1034 typedef struct ccsr_cpm
{
1042 typedef struct ccsr_cpm_siu
{
1054 /* IRQ Controller */
1055 typedef struct ccsr_cpm_intctl
{
1070 } ccsr_cpm_intctl_t
;
1072 /* input/output port */
1073 typedef struct ccsr_cpm_iop
{
1101 typedef struct ccsr_cpm_timer
{
1130 typedef struct ccsr_cpm_sdma
{
1138 typedef struct ccsr_cpm_fcc1
{
1155 typedef struct ccsr_cpm_fcc2
{
1172 typedef struct ccsr_cpm_fcc3
{
1189 typedef struct ccsr_cpm_fcc1_ext
{
1197 } ccsr_cpm_fcc1_ext_t
;
1200 typedef struct ccsr_cpm_fcc2_ext
{
1207 } ccsr_cpm_fcc2_ext_t
;
1210 typedef struct ccsr_cpm_fcc3_ext
{
1213 } ccsr_cpm_fcc3_ext_t
;
1216 typedef struct ccsr_cpm_tmp1
{
1221 typedef struct ccsr_cpm_brg2
{
1230 typedef struct ccsr_cpm_i2c
{
1246 typedef struct ccsr_cpm_cp
{
1260 typedef struct ccsr_cpm_brg1
{
1268 typedef struct ccsr_cpm_scc
{
1283 typedef struct ccsr_cpm_tmp2
{
1288 typedef struct ccsr_cpm_spi
{
1300 typedef struct ccsr_cpm_mux
{
1313 typedef struct ccsr_cpm_tmp3
{
1317 typedef struct ccsr_cpm_iram
{
1322 typedef struct ccsr_cpm
{
1323 /* Some references are into the unique & known dpram spaces,
1324 * others are from the generic base.
1326 #define im_dprambase im_dpram1
1327 u8 im_dpram1
[16*1024];
1329 u8 im_dpram2
[16*1024];
1331 ccsr_cpm_siu_t im_cpm_siu
; /* SIU Configuration */
1332 ccsr_cpm_intctl_t im_cpm_intctl
; /* IRQ Controller */
1333 ccsr_cpm_iop_t im_cpm_iop
; /* IO Port control/status */
1334 ccsr_cpm_timer_t im_cpm_timer
; /* CPM timers */
1335 ccsr_cpm_sdma_t im_cpm_sdma
; /* SDMA control/status */
1336 ccsr_cpm_fcc1_t im_cpm_fcc1
;
1337 ccsr_cpm_fcc2_t im_cpm_fcc2
;
1338 ccsr_cpm_fcc3_t im_cpm_fcc3
;
1339 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext
;
1340 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext
;
1341 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext
;
1342 ccsr_cpm_tmp1_t im_cpm_tmp1
;
1343 ccsr_cpm_brg2_t im_cpm_brg2
;
1344 ccsr_cpm_i2c_t im_cpm_i2c
;
1345 ccsr_cpm_cp_t im_cpm_cp
;
1346 ccsr_cpm_brg1_t im_cpm_brg1
;
1347 ccsr_cpm_scc_t im_cpm_scc
[4];
1348 ccsr_cpm_tmp2_t im_cpm_tmp2
;
1349 ccsr_cpm_spi_t im_cpm_spi
;
1350 ccsr_cpm_mux_t im_cpm_mux
;
1351 ccsr_cpm_tmp3_t im_cpm_tmp3
;
1352 ccsr_cpm_iram_t im_cpm_iram
;
1356 /* RapidIO Registers */
1357 typedef struct ccsr_rio
{
1358 u32 didcar
; /* Device Identity Capability */
1359 u32 dicar
; /* Device Information Capability */
1360 u32 aidcar
; /* Assembly Identity Capability */
1361 u32 aicar
; /* Assembly Information Capability */
1362 u32 pefcar
; /* Processing Element Features Capability */
1363 u32 spicar
; /* Switch Port Information Capability */
1364 u32 socar
; /* Source Operations Capability */
1365 u32 docar
; /* Destination Operations Capability */
1367 u32 msr
; /* Mailbox Cmd And Status */
1368 u32 pwdcsr
; /* Port-Write & Doorbell Cmd And Status */
1370 u32 pellccsr
; /* Processing Element Logic Layer CCSR */
1372 u32 lcsbacsr
; /* Local Cfg Space Base Addr Cmd & Status */
1373 u32 bdidcsr
; /* Base Device ID Cmd & Status */
1375 u32 hbdidlcsr
; /* Host Base Device ID Lock Cmd & Status */
1376 u32 ctcsr
; /* Component Tag Cmd & Status */
1378 u32 pmbh0csr
; /* Port Maint. Block Hdr 0 Cmd & Status */
1380 u32 pltoccsr
; /* Port Link Time-out Ctrl Cmd & Status */
1381 u32 prtoccsr
; /* Port Response Time-out Ctrl Cmd & Status */
1383 u32 pgccsr
; /* Port General Cmd & Status */
1384 u32 plmreqcsr
; /* Port Link Maint. Request Cmd & Status */
1385 u32 plmrespcsr
; /* Port Link Maint. Response Cmd & Status */
1386 u32 plascsr
; /* Port Local Ackid Status Cmd & Status */
1388 u32 pescsr
; /* Port Error & Status Cmd & Status */
1389 u32 pccsr
; /* Port Control Cmd & Status */
1391 u32 cr
; /* Port Control Cmd & Status */
1393 u32 pcr
; /* Port Configuration */
1394 u32 peir
; /* Port Error Injection */
1396 u32 rowtar0
; /* RIO Outbound Window Translation Addr 0 */
1398 u32 rowar0
; /* RIO Outbound Attrs 0 */
1400 u32 rowtar1
; /* RIO Outbound Window Translation Addr 1 */
1402 u32 rowbar1
; /* RIO Outbound Window Base Addr 1 */
1404 u32 rowar1
; /* RIO Outbound Attrs 1 */
1406 u32 rowtar2
; /* RIO Outbound Window Translation Addr 2 */
1408 u32 rowbar2
; /* RIO Outbound Window Base Addr 2 */
1410 u32 rowar2
; /* RIO Outbound Attrs 2 */
1412 u32 rowtar3
; /* RIO Outbound Window Translation Addr 3 */
1414 u32 rowbar3
; /* RIO Outbound Window Base Addr 3 */
1416 u32 rowar3
; /* RIO Outbound Attrs 3 */
1418 u32 rowtar4
; /* RIO Outbound Window Translation Addr 4 */
1420 u32 rowbar4
; /* RIO Outbound Window Base Addr 4 */
1422 u32 rowar4
; /* RIO Outbound Attrs 4 */
1424 u32 rowtar5
; /* RIO Outbound Window Translation Addr 5 */
1426 u32 rowbar5
; /* RIO Outbound Window Base Addr 5 */
1428 u32 rowar5
; /* RIO Outbound Attrs 5 */
1430 u32 rowtar6
; /* RIO Outbound Window Translation Addr 6 */
1432 u32 rowbar6
; /* RIO Outbound Window Base Addr 6 */
1434 u32 rowar6
; /* RIO Outbound Attrs 6 */
1436 u32 rowtar7
; /* RIO Outbound Window Translation Addr 7 */
1438 u32 rowbar7
; /* RIO Outbound Window Base Addr 7 */
1440 u32 rowar7
; /* RIO Outbound Attrs 7 */
1442 u32 rowtar8
; /* RIO Outbound Window Translation Addr 8 */
1444 u32 rowbar8
; /* RIO Outbound Window Base Addr 8 */
1446 u32 rowar8
; /* RIO Outbound Attrs 8 */
1448 u32 riwtar4
; /* RIO Inbound Window Translation Addr 4 */
1450 u32 riwbar4
; /* RIO Inbound Window Base Addr 4 */
1452 u32 riwar4
; /* RIO Inbound Attrs 4 */
1454 u32 riwtar3
; /* RIO Inbound Window Translation Addr 3 */
1456 u32 riwbar3
; /* RIO Inbound Window Base Addr 3 */
1458 u32 riwar3
; /* RIO Inbound Attrs 3 */
1460 u32 riwtar2
; /* RIO Inbound Window Translation Addr 2 */
1462 u32 riwbar2
; /* RIO Inbound Window Base Addr 2 */
1464 u32 riwar2
; /* RIO Inbound Attrs 2 */
1466 u32 riwtar1
; /* RIO Inbound Window Translation Addr 1 */
1468 u32 riwbar1
; /* RIO Inbound Window Base Addr 1 */
1470 u32 riwar1
; /* RIO Inbound Attrs 1 */
1472 u32 riwtar0
; /* RIO Inbound Window Translation Addr 0 */
1474 u32 riwar0
; /* RIO Inbound Attrs 0 */
1476 u32 pnfedr
; /* Port Notification/Fatal Error Detect */
1477 u32 pnfedir
; /* Port Notification/Fatal Error Detect */
1478 u32 pnfeier
; /* Port Notification/Fatal Error IRQ Enable */
1479 u32 pecr
; /* Port Error Control */
1480 u32 pepcsr0
; /* Port Error Packet/Control Symbol 0 */
1481 u32 pepr1
; /* Port Error Packet 1 */
1482 u32 pepr2
; /* Port Error Packet 2 */
1484 u32 predr
; /* Port Recoverable Error Detect */
1486 u32 pertr
; /* Port Error Recovery Threshold */
1487 u32 prtr
; /* Port Retry Threshold */
1489 u32 omr
; /* Outbound Mode */
1490 u32 osr
; /* Outbound Status */
1491 u32 eodqtpar
; /* Extended Outbound Desc Queue Tail Ptr Addr */
1492 u32 odqtpar
; /* Outbound Desc Queue Tail Ptr Addr */
1493 u32 eosar
; /* Extended Outbound Unit Source Addr */
1494 u32 osar
; /* Outbound Unit Source Addr */
1495 u32 odpr
; /* Outbound Destination Port */
1496 u32 odatr
; /* Outbound Destination Attrs */
1497 u32 odcr
; /* Outbound Doubleword Count */
1498 u32 eodqhpar
; /* Extended Outbound Desc Queue Head Ptr Addr */
1499 u32 odqhpar
; /* Outbound Desc Queue Head Ptr Addr */
1501 u32 imr
; /* Outbound Mode */
1502 u32 isr
; /* Inbound Status */
1503 u32 eidqtpar
; /* Extended Inbound Desc Queue Tail Ptr Addr */
1504 u32 idqtpar
; /* Inbound Desc Queue Tail Ptr Addr */
1505 u32 eifqhpar
; /* Extended Inbound Frame Queue Head Ptr Addr */
1506 u32 ifqhpar
; /* Inbound Frame Queue Head Ptr Addr */
1508 u32 dmr
; /* Doorbell Mode */
1509 u32 dsr
; /* Doorbell Status */
1510 u32 edqtpar
; /* Extended Doorbell Queue Tail Ptr Addr */
1511 u32 dqtpar
; /* Doorbell Queue Tail Ptr Addr */
1512 u32 edqhpar
; /* Extended Doorbell Queue Head Ptr Addr */
1513 u32 dqhpar
; /* Doorbell Queue Head Ptr Addr */
1515 u32 pwmr
; /* Port-Write Mode */
1516 u32 pwsr
; /* Port-Write Status */
1517 u32 epwqbar
; /* Extended Port-Write Queue Base Addr */
1518 u32 pwqbar
; /* Port-Write Queue Base Addr */
1522 /* Quick Engine Block Pin Muxing Registers */
1523 typedef struct par_io
{
1533 #ifdef CONFIG_SYS_FSL_CPC
1535 * Define a single offset that is the start of all the CPC register
1536 * blocks - if there is more than one CPC, we expect these to be
1537 * contiguous 4k regions
1540 typedef struct cpc_corenet
{
1541 u32 cpccsr0
; /* Config/status reg */
1543 u32 cpccfg0
; /* Configuration register */
1545 u32 cpcewcr0
; /* External Write reg 0 */
1546 u32 cpcewabr0
; /* External write base reg 0 */
1548 u32 cpcewcr1
; /* External Write reg 1 */
1549 u32 cpcewabr1
; /* External write base reg 1 */
1551 u32 cpcsrcr1
; /* SRAM control reg 1 */
1552 u32 cpcsrcr0
; /* SRAM control reg 0 */
1555 u32 id
; /* partition ID */
1557 u32 alloc
; /* partition allocation */
1558 u32 way
; /* partition way */
1559 } partition_regs
[16];
1561 u32 cpcerrinjhi
; /* Error injection high */
1562 u32 cpcerrinjlo
; /* Error injection lo */
1563 u32 cpcerrinjctl
; /* Error injection control */
1565 u32 cpccaptdatahi
; /* capture data high */
1566 u32 cpccaptdatalo
; /* capture data low */
1567 u32 cpcaptecc
; /* capture ECC */
1569 u32 cpcerrdet
; /* error detect */
1570 u32 cpcerrdis
; /* error disable */
1571 u32 cpcerrinten
; /* errir interrupt enable */
1572 u32 cpcerrattr
; /* error attribute */
1573 u32 cpcerreaddr
; /* error extended address */
1574 u32 cpcerraddr
; /* error address */
1575 u32 cpcerrctl
; /* error control */
1576 u32 res9
[41]; /* pad out to 4k */
1577 u32 cpchdbcr0
; /* hardware debug control register 0 */
1578 u32 res10
[63]; /* pad out to 4k */
1581 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1582 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1583 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1584 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1585 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1586 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1587 #define CPC_CFG0_SZ_MASK 0x00003fff
1588 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1589 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1590 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1591 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1592 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1593 & CPC_SRCR1_SRBARU_MASK)
1594 #define CPC_SRCR0_SRBARL_MASK 0xffff8000
1595 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1596 #define CPC_SRCR0_INTLVEN 0x00000100
1597 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1598 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1599 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1600 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1601 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1602 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1603 #define CPC_SRCR0_SRAMEN 0x00000001
1604 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1605 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1606 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1607 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1608 #endif /* CONFIG_SYS_FSL_CPC */
1610 /* Global Utilities Block */
1611 #ifdef CONFIG_FSL_CORENET
1612 typedef struct ccsr_gur
{
1613 u32 porsr1
; /* POR status */
1615 u32 gpporcr1
; /* General-purpose POR configuration */
1617 u32 gpiocr
; /* GPIO control */
1619 u32 gpoutdr
; /* General-purpose output data */
1621 u32 gpindr
; /* General-purpose input data */
1623 u32 alt_pmuxcr
; /* Alt function signal multiplex control */
1625 u32 devdisr
; /* Device disable control */
1626 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1627 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1628 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1629 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1630 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1631 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1632 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1633 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1634 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1635 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1636 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1637 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1638 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1639 #define FSL_CORENET_DEVDISR_SATA1 0x00004000
1640 #define FSL_CORENET_DEVDISR_SATA2 0x00002000
1641 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1642 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1643 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1644 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1645 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1646 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1647 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1648 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1649 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1650 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1651 u32 devdisr2
; /* Device disable control 2 */
1652 #define FSL_CORENET_DEVDISR2_PME 0x80000000
1653 #define FSL_CORENET_DEVDISR2_SEC 0x40000000
1654 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1655 #define FSL_CORENET_DEVDISR2_FM1 0x02000000
1656 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1657 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1658 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1659 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1660 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1661 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1662 #define FSL_CORENET_DEVDISR2_FM2 0x00020000
1663 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1664 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1665 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1666 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1667 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1668 #define FSL_CORENET_NUM_DEVDISR 2
1670 u32 powmgtcsr
; /* Power management status & control */
1672 u32 coredisru
; /* uppper portion for support of 64 cores */
1673 u32 coredisrl
; /* lower portion for support of 64 cores */
1675 u32 pvr
; /* Processor version */
1676 u32 svr
; /* System version */
1678 u32 rstcr
; /* Reset control */
1679 u32 rstrqpblsr
; /* Reset request preboot loader status */
1681 u32 rstrqmr1
; /* Reset request mask */
1683 u32 rstrqsr1
; /* Reset request status */
1686 u32 rstrqwdtmrl
; /* Reset request WDT mask */
1688 u32 rstrqwdtsrl
; /* Reset request WDT status */
1690 u32 brrl
; /* Boot release */
1692 u32 rcwsr
[16]; /* Reset control word status */
1693 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1694 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1695 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1696 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1697 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1698 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
1699 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1700 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1701 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1702 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1703 #if defined(CONFIG_PPC_P4080)
1704 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1705 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1706 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1707 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1708 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1709 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1711 #if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
1712 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
1713 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1714 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1715 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1716 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1717 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1718 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1719 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1722 u32 scratchrw
[4]; /* Scratch Read/Write */
1724 u32 scratchw1r
[4]; /* Scratch Read (Write once) */
1726 u32 scrtsr
[8]; /* Core reset status */
1728 u32 pex1liodnr
; /* PCI Express 1 LIODN */
1729 u32 pex2liodnr
; /* PCI Express 2 LIODN */
1730 u32 pex3liodnr
; /* PCI Express 3 LIODN */
1731 u32 pex4liodnr
; /* PCI Express 4 LIODN */
1732 u32 rio1liodnr
; /* RIO 1 LIODN */
1733 u32 rio2liodnr
; /* RIO 2 LIODN */
1734 u32 rio3liodnr
; /* RIO 3 LIODN */
1735 u32 rio4liodnr
; /* RIO 4 LIODN */
1736 u32 usb1liodnr
; /* USB 1 LIODN */
1737 u32 usb2liodnr
; /* USB 2 LIODN */
1738 u32 usb3liodnr
; /* USB 3 LIODN */
1739 u32 usb4liodnr
; /* USB 4 LIODN */
1740 u32 sdmmc1liodnr
; /* SD/MMC 1 LIODN */
1741 u32 sdmmc2liodnr
; /* SD/MMC 2 LIODN */
1742 u32 sdmmc3liodnr
; /* SD/MMC 3 LIODN */
1743 u32 sdmmc4liodnr
; /* SD/MMC 4 LIODN */
1744 u32 rio1maintliodnr
;/* RIO 1 Maintenance LIODN */
1745 u32 rio2maintliodnr
;/* RIO 2 Maintenance LIODN */
1746 u32 rio3maintliodnr
;/* RIO 3 Maintenance LIODN */
1747 u32 rio4maintliodnr
;/* RIO 4 Maintenance LIODN */
1748 u32 sata1liodnr
; /* SATA 1 LIODN */
1749 u32 sata2liodnr
; /* SATA 2 LIODN */
1750 u32 sata3liodnr
; /* SATA 3 LIODN */
1751 u32 sata4liodnr
; /* SATA 4 LIODN */
1753 u32 dma1liodnr
; /* DMA 1 LIODN */
1754 u32 dma2liodnr
; /* DMA 2 LIODN */
1755 u32 dma3liodnr
; /* DMA 3 LIODN */
1756 u32 dma4liodnr
; /* DMA 4 LIODN */
1759 u32 pblsr
; /* Preboot loader status */
1760 u32 pamubypenr
; /* PAMU bypass enable */
1761 u32 dmacr1
; /* DMA control */
1763 u32 gensr1
; /* General status */
1765 u32 gencr1
; /* General control */
1768 u32 cgensrl
; /* Core general status */
1771 u32 cgencrl
; /* Core general control */
1773 u32 sriopstecr
; /* SRIO prescaler timer enable control */
1774 u32 dcsrcr
; /* DCSR Control register */
1776 u32 pmuxcr
; /* Pin multiplexing control */
1778 u32 iovselsr
; /* I/O voltage selection status */
1780 u32 ddrclkdr
; /* DDR clock disable */
1782 u32 elbcclkdr
; /* eLBC clock disable */
1784 u32 sdhcpcr
; /* eSDHC polarity configuration */
1788 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1789 #define FSL_CORENET_DCSR_SZ_4M 0x0
1790 #define FSL_CORENET_DCSR_SZ_1G 0x3
1793 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1794 * everything after has RMan thus msg unit LIODN is used for maintenance
1796 #define rmuliodnr rio1maintliodnr
1798 typedef struct ccsr_clk
{
1799 u32 clkc0csr
; /* Core 0 Clock control/status */
1801 u32 clkc1csr
; /* Core 1 Clock control/status */
1803 u32 clkc2csr
; /* Core 2 Clock control/status */
1805 u32 clkc3csr
; /* Core 3 Clock control/status */
1807 u32 clkc4csr
; /* Core 4 Clock control/status */
1809 u32 clkc5csr
; /* Core 5 Clock control/status */
1811 u32 clkc6csr
; /* Core 6 Clock control/status */
1813 u32 clkc7csr
; /* Core 7 Clock control/status */
1815 u32 pllc1gsr
; /* Cluster PLL 1 General Status */
1817 u32 pllc2gsr
; /* Cluster PLL 2 General Status */
1819 u32 pllc3gsr
; /* Cluster PLL 3 General Status */
1821 u32 pllc4gsr
; /* Cluster PLL 4 General Status */
1823 u32 pllpgsr
; /* Platform PLL General Status */
1825 u32 plldgsr
; /* DDR PLL General Status */
1829 typedef struct ccsr_rcpm
{
1831 u32 cdozsrl
; /* Core Doze Status */
1833 u32 cdozcrl
; /* Core Doze Control */
1835 u32 cnapsrl
; /* Core Nap Status */
1837 u32 cnapcrl
; /* Core Nap Control */
1839 u32 cdozpsrl
; /* Core Doze Previous Status */
1841 u32 cdozpcrl
; /* Core Doze Previous Control */
1843 u32 cwaitsrl
; /* Core Wait Status */
1845 u32 powmgtcsr
; /* Power Mangement Control & Status */
1847 u32 ippdexpcr0
; /* IP Powerdown Exception Control 0 */
1850 u32 cpmimrl
; /* Core PM IRQ Masking */
1852 u32 cpmcimrl
; /* Core PM Critical IRQ Masking */
1854 u32 cpmmcimrl
; /* Core PM Machine Check IRQ Masking */
1856 u32 cpmnmimrl
; /* Core PM NMI Masking */
1858 u32 ctbenrl
; /* Core Time Base Enable */
1860 u32 ctbclkselrl
; /* Core Time Base Clock Select */
1862 u32 ctbhltcrl
; /* Core Time Base Halt Control */
1867 typedef struct ccsr_gur
{
1868 u32 porpllsr
; /* POR PLL ratio status */
1869 #ifdef CONFIG_MPC8536
1870 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
1871 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
1873 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
1874 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
1876 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
1877 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
1878 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
1879 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
1880 u32 porbmsr
; /* POR boot mode status */
1881 #define MPC85xx_PORBMSR_HA 0x00070000
1882 #define MPC85xx_PORBMSR_HA_SHIFT 16
1883 u32 porimpscr
; /* POR I/O impedance status & control */
1884 u32 pordevsr
; /* POR I/O device status regsiter */
1885 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
1886 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
1887 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
1888 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
1890 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
1891 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
1893 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
1894 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
1895 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
1896 #define MPC85xx_PORDEVSR_PCI1 0x00800000
1897 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
1898 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
1899 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
1900 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
1901 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
1902 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
1904 #if defined(CONFIG_P1010)
1905 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
1906 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
1908 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
1909 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
1910 #endif /* if defined(CONFIG_P1010) */
1912 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
1913 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
1914 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
1915 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
1916 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
1917 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
1918 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
1919 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
1920 u32 pordbgmsr
; /* POR debug mode status */
1921 u32 pordevsr2
; /* POR I/O device status 2 */
1922 /* The 8544 RM says this is bit 26, but it's really bit 24 */
1923 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
1925 u32 gpporcr
; /* General-purpose POR configuration */
1927 u32 gpiocr
; /* GPIO control */
1929 #if defined(CONFIG_MPC8569)
1930 u32 plppar1
; /* Platform port pin assignment 1 */
1931 u32 plppar2
; /* Platform port pin assignment 2 */
1932 u32 plpdir1
; /* Platform port pin direction 1 */
1933 u32 plpdir2
; /* Platform port pin direction 2 */
1935 u32 gpoutdr
; /* General-purpose output data */
1938 u32 gpindr
; /* General-purpose input data */
1940 u32 pmuxcr
; /* Alt. function signal multiplex control */
1941 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
1942 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
1943 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
1944 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
1945 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
1946 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
1947 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
1948 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
1949 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
1950 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
1951 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
1952 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
1953 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
1954 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
1955 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
1956 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
1957 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
1958 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
1959 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
1960 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
1961 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
1962 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
1963 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
1964 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
1965 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
1966 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
1967 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
1968 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
1969 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
1970 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
1971 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
1972 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
1973 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
1974 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
1975 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
1976 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
1977 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
1978 #define MPC85xx_PMUXCR_SPI_RES 0x00000030
1979 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
1980 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
1981 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
1982 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
1983 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
1984 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
1985 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
1987 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
1988 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000
1990 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
1991 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
1992 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
1993 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
1994 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
1995 #define MPC85xx_PMUXCR_QE0 0x00008000
1996 #define MPC85xx_PMUXCR_QE1 0x00004000
1997 #define MPC85xx_PMUXCR_QE2 0x00002000
1998 #define MPC85xx_PMUXCR_QE3 0x00001000
1999 #define MPC85xx_PMUXCR_QE4 0x00000800
2000 #define MPC85xx_PMUXCR_QE5 0x00000400
2001 #define MPC85xx_PMUXCR_QE6 0x00000200
2002 #define MPC85xx_PMUXCR_QE7 0x00000100
2003 #define MPC85xx_PMUXCR_QE8 0x00000080
2004 #define MPC85xx_PMUXCR_QE9 0x00000040
2005 #define MPC85xx_PMUXCR_QE10 0x00000020
2006 #define MPC85xx_PMUXCR_QE11 0x00000010
2007 #define MPC85xx_PMUXCR_QE12 0x00000008
2009 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2010 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2011 #define MPC85xx_PMUXCR_TDM 0x00014800
2012 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2013 #define MPC85xx_PMUXCR_SPI 0x00000000
2015 u32 pmuxcr2
; /* Alt. function signal multiplex control 2 */
2016 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2017 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2018 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2019 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2020 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2021 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2022 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2023 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2024 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2025 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2026 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2027 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2028 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2029 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2030 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2031 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2032 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2033 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2034 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2035 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2036 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2037 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2038 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2039 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2041 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2042 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2043 #define MPC85xx_PMUXCR2_USB 0x00150000
2046 u32 devdisr
; /* Device disable control */
2047 #define MPC85xx_DEVDISR_PCI1 0x80000000
2048 #define MPC85xx_DEVDISR_PCI2 0x40000000
2049 #define MPC85xx_DEVDISR_PCIE 0x20000000
2050 #define MPC85xx_DEVDISR_LBC 0x08000000
2051 #define MPC85xx_DEVDISR_PCIE2 0x04000000
2052 #define MPC85xx_DEVDISR_PCIE3 0x02000000
2053 #define MPC85xx_DEVDISR_SEC 0x01000000
2054 #define MPC85xx_DEVDISR_SRIO 0x00080000
2055 #define MPC85xx_DEVDISR_RMSG 0x00040000
2056 #define MPC85xx_DEVDISR_DDR 0x00010000
2057 #define MPC85xx_DEVDISR_CPU 0x00008000
2058 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2059 #define MPC85xx_DEVDISR_TB 0x00004000
2060 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2061 #define MPC85xx_DEVDISR_CPU1 0x00002000
2062 #define MPC85xx_DEVDISR_TB1 0x00001000
2063 #define MPC85xx_DEVDISR_DMA 0x00000400
2064 #define MPC85xx_DEVDISR_TSEC1 0x00000080
2065 #define MPC85xx_DEVDISR_TSEC2 0x00000040
2066 #define MPC85xx_DEVDISR_TSEC3 0x00000020
2067 #define MPC85xx_DEVDISR_TSEC4 0x00000010
2068 #define MPC85xx_DEVDISR_I2C 0x00000004
2069 #define MPC85xx_DEVDISR_DUART 0x00000002
2071 u32 powmgtcsr
; /* Power management status & control */
2073 u32 mcpsumr
; /* Machine check summary */
2075 u32 pvr
; /* Processor version */
2076 u32 svr
; /* System version */
2078 u32 rstcr
; /* Reset control */
2079 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
2081 par_io_t qe_par_io
[7];
2083 #elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
2084 defined(CONFIG_P1021) || defined(CONFIG_P1025)
2088 par_io_t qe_par_io
[3];
2093 u32 clkdvdr
; /* Clock Divide register */
2095 u32 clkocr
; /* Clock out select */
2097 u32 ddrdllcr
; /* DDR DLL control */
2099 u32 lbcdllcr
; /* LBC DLL control */
2101 u32 lbiuiplldcr0
; /* LBIU PLL Debug Reg 0 */
2102 u32 lbiuiplldcr1
; /* LBIU PLL Debug Reg 1 */
2103 u32 ddrioovcr
; /* DDR IO Override Control */
2104 u32 tsec12ioovcr
; /* eTSEC 1/2 IO override control */
2105 u32 tsec34ioovcr
; /* eTSEC 3/4 IO override control */
2107 u32 sdhcdcr
; /* SDHC debug control register */
2112 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2114 typedef struct serdes_corenet
{
2116 u32 rstctl
; /* Reset Control Register */
2117 #define SRDS_RSTCTL_RST 0x80000000
2118 #define SRDS_RSTCTL_RSTDONE 0x40000000
2119 #define SRDS_RSTCTL_RSTERR 0x20000000
2120 #define SRDS_RSTCTL_SDPD 0x00000020
2121 u32 pllcr0
; /* PLL Control Register 0 */
2122 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000
2123 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2124 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2125 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2126 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2127 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2128 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2129 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2130 u32 pllcr1
; /* PLL Control Register 1 */
2131 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2135 u32 srdstcalcr
; /* TX Calibration Control */
2137 u32 srdsrcalcr
; /* RX Calibration Control */
2139 u32 srdsgr0
; /* General Register 0 */
2141 u32 srdspccr0
; /* Protocol Converter Config 0 */
2142 u32 srdspccr1
; /* Protocol Converter Config 1 */
2143 u32 srdspccr2
; /* Protocol Converter Config 2 */
2144 #define SRDS_PCCR2_RST_XGMII1 0x00800000
2145 #define SRDS_PCCR2_RST_XGMII2 0x00400000
2148 u32 gcr0
; /* General Control Register 0 */
2149 #define SRDS_GCR0_RRST 0x00400000
2150 #define SRDS_GCR0_1STLANE 0x00010000
2151 u32 gcr1
; /* General Control Register 1 */
2152 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2153 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2154 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2155 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2156 #define SRDS_GCR1_OPAD_CTL 0x04000000
2158 u32 tecr0
; /* TX Equalization Control Reg 0 */
2159 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2160 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2162 u32 ttlcr0
; /* Transition Tracking Loop Ctrl 0 */
2163 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2164 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2165 #define SRDS_TTLCR0_PM_DIS 0x00004000
2172 FSL_SRDS_B1_LANE_A
= 0,
2173 FSL_SRDS_B1_LANE_B
= 1,
2174 FSL_SRDS_B1_LANE_C
= 2,
2175 FSL_SRDS_B1_LANE_D
= 3,
2176 FSL_SRDS_B1_LANE_E
= 4,
2177 FSL_SRDS_B1_LANE_F
= 5,
2178 FSL_SRDS_B1_LANE_G
= 6,
2179 FSL_SRDS_B1_LANE_H
= 7,
2180 FSL_SRDS_B1_LANE_I
= 8,
2181 FSL_SRDS_B1_LANE_J
= 9,
2182 FSL_SRDS_B2_LANE_A
= 16,
2183 FSL_SRDS_B2_LANE_B
= 17,
2184 FSL_SRDS_B2_LANE_C
= 18,
2185 FSL_SRDS_B2_LANE_D
= 19,
2186 FSL_SRDS_B3_LANE_A
= 20,
2187 FSL_SRDS_B3_LANE_B
= 21,
2188 FSL_SRDS_B3_LANE_C
= 22,
2189 FSL_SRDS_B3_LANE_D
= 23,
2192 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2193 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2194 typedef struct ccsr_sec
{
2196 u32 mcfgr
; /* Master CFG Register */
2199 u32 ms
; /* Job Ring LIODN Register, MS */
2200 u32 ls
; /* Job Ring LIODN Register, LS */
2204 u32 ms
; /* RTIC LIODN Register, MS */
2205 u32 ls
; /* RTIC LIODN Register, LS */
2208 u32 decorr
; /* DECO Request Register */
2210 u32 ms
; /* DECO LIODN Register, MS */
2211 u32 ls
; /* DECO LIODN Register, LS */
2214 u32 dar
; /* DECO Avail Register */
2215 u32 drr
; /* DECO Reset Register */
2217 u32 crnr_ms
; /* CHA Revision Number Register, MS */
2218 u32 crnr_ls
; /* CHA Revision Number Register, LS */
2219 u32 ctpr_ms
; /* Compile Time Parameters Register, MS */
2220 u32 ctpr_ls
; /* Compile Time Parameters Register, LS */
2222 u32 far_ms
; /* Fault Address Register, MS */
2223 u32 far_ls
; /* Fault Address Register, LS */
2224 u32 falr
; /* Fault Address LIODN Register */
2225 u32 fadr
; /* Fault Address Detail Register */
2227 u32 csta
; /* CAAM Status Register */
2229 u32 rvid
; /* Run Time Integrity Checking Version ID Reg.*/
2230 u32 ccbvid
; /* CHA Cluster Block Version ID Register */
2231 u32 chavid_ms
; /* CHA Version ID Register, MS */
2232 u32 chavid_ls
; /* CHA Version ID Register, LS */
2233 u32 chanum_ms
; /* CHA Number Register, MS */
2234 u32 chanum_ls
; /* CHA Number Register, LS */
2235 u32 secvid_ms
; /* SEC Version ID Register, MS */
2236 u32 secvid_ls
; /* SEC Version ID Register, LS */
2238 u32 qilcr_ms
; /* Queue Interface LIODN CFG Register, MS */
2239 u32 qilcr_ls
; /* Queue Interface LIODN CFG Register, LS */
2243 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
2244 #define SEC_CTPR_MS_QI 0x02000000
2245 #define SEC_RVID_MA 0x0f000000
2246 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2247 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
2248 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2249 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
2252 typedef struct ccsr_qman
{
2254 u32 qcsp_lio_cfg
; /* 0x0 - SW Portal n LIO cfg */
2255 u32 qcsp_io_cfg
; /* 0x4 - SW Portal n IO cfg */
2257 u32 qcsp_dd_cfg
; /* 0xc - SW Portal n Dynamic Debug cfg */
2260 /* Not actually reserved, but irrelevant to u-boot */
2261 u8 res
[0xbf8 - 0x200];
2264 u32 fqd_bare
; /* FQD Extended Base Addr Register */
2265 u32 fqd_bar
; /* FQD Base Addr Register */
2267 u32 fqd_ar
; /* FQD Attributes Register */
2269 u32 pfdr_bare
; /* PFDR Extended Base Addr Register */
2270 u32 pfdr_bar
; /* PFDR Base Addr Register */
2272 u32 pfdr_ar
; /* PFDR Attributes Register */
2274 u32 qcsp_bare
; /* QCSP Extended Base Addr Register */
2275 u32 qcsp_bar
; /* QCSP Base Addr Register */
2277 u32 ci_sched_cfg
; /* Initiator Scheduling Configuration */
2278 u32 srcidr
; /* Source ID Register */
2279 u32 liodnr
; /* LIODN Register */
2281 u32 ci_rlm_cfg
; /* Initiator Read Latency Monitor Cfg */
2282 u32 ci_rlm_avg
; /* Initiator Read Latency Monitor Avg */
2286 typedef struct ccsr_bman
{
2287 /* Not actually reserved, but irrelevant to u-boot */
2291 u32 fbpr_bare
; /* FBPR Extended Base Addr Register */
2292 u32 fbpr_bar
; /* FBPR Base Addr Register */
2294 u32 fbpr_ar
; /* FBPR Attributes Register */
2296 u32 srcidr
; /* Source ID Register */
2297 u32 liodnr
; /* LIODN Register */
2301 typedef struct ccsr_pme
{
2303 u32 liodnbr
; /* LIODN Base Register */
2305 u32 srcidr
; /* Source ID Register */
2307 u32 liodnr
; /* LIODN Register */
2309 u32 pm_ip_rev_1
; /* PME IP Block Revision Reg 1*/
2310 u32 pm_ip_rev_2
; /* PME IP Block Revision Reg 1*/
2314 typedef struct ccsr_usb_phy
{
2316 u32 usb_enable_override
;
2319 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
2321 #ifdef CONFIG_FSL_CORENET
2322 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2323 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
2324 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
2325 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2326 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2327 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2328 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2329 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2330 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2331 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2332 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2333 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2334 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2335 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2336 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2337 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2338 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2339 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2340 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2341 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2342 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
2343 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2344 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2345 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2346 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2347 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2348 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2349 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2350 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2351 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2352 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2353 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2354 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2355 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2356 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2357 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2358 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2359 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2360 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2361 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2362 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2363 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2364 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2365 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2367 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2368 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
2369 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2370 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
2371 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2372 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2373 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2374 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2375 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2376 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2377 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2378 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
2379 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2381 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2383 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2384 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2385 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2386 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2387 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2388 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2389 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
2390 #ifdef CONFIG_TSECV2
2391 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2393 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
2395 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
2396 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2397 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2398 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2399 #define CONFIG_SYS_SNVS_OFFSET 0xE6000
2400 #define CONFIG_SYS_SFP_OFFSET 0xE7000
2401 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2402 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2403 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2404 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2405 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2406 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2407 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
2410 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2411 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2413 #define CONFIG_SYS_FSL_CPC_ADDR \
2414 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
2415 #define CONFIG_SYS_FSL_QMAN_ADDR \
2416 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2417 #define CONFIG_SYS_FSL_BMAN_ADDR \
2418 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
2419 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
2420 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
2421 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
2422 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2423 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
2424 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2425 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
2426 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2427 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
2428 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2429 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
2430 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
2431 #define CONFIG_SYS_MPC85xx_DDR_ADDR \
2432 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
2433 #define CONFIG_SYS_MPC85xx_DDR2_ADDR \
2434 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
2435 #define CONFIG_SYS_LBC_ADDR \
2436 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
2437 #define CONFIG_SYS_IFC_ADDR \
2438 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
2439 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2440 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
2441 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
2442 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
2443 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
2444 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
2445 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
2446 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
2447 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
2448 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
2449 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
2450 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
2451 #define CONFIG_SYS_MPC85xx_L2_ADDR \
2452 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
2453 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
2454 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
2455 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
2456 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
2457 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
2458 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
2459 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
2460 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
2461 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
2462 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
2463 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
2464 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
2465 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
2466 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
2467 #define CONFIG_SYS_MPC85xx_USB_ADDR \
2468 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
2469 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
2470 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
2471 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
2472 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
2473 #define CONFIG_SYS_FSL_SEC_ADDR \
2474 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
2475 #define CONFIG_SYS_FSL_FM1_ADDR \
2476 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
2477 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
2478 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
2479 #define CONFIG_SYS_FSL_FM2_ADDR \
2480 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
2482 #define CONFIG_SYS_PCI1_ADDR \
2483 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
2484 #define CONFIG_SYS_PCI2_ADDR \
2485 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
2486 #define CONFIG_SYS_PCIE1_ADDR \
2487 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
2488 #define CONFIG_SYS_PCIE2_ADDR \
2489 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
2490 #define CONFIG_SYS_PCIE3_ADDR \
2491 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
2492 #define CONFIG_SYS_PCIE4_ADDR \
2493 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
2495 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
2496 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
2498 #endif /*__IMMAP_85xx__*/