2 * MPC85xx Internal Memory Map
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
9 * SPDX-License-Identifier: GPL-2.0+
12 #ifndef __IMMAP_85xx__
13 #define __IMMAP_85xx__
15 #include <asm/types.h>
16 #include <asm/fsl_dma.h>
17 #include <asm/fsl_i2c.h>
18 #include <asm/fsl_ifc.h>
19 #include <asm/fsl_lbc.h>
20 #include <asm/fsl_fman.h>
22 typedef struct ccsr_local
{
23 u32 ccsrbarh
; /* CCSR Base Addr High */
24 u32 ccsrbarl
; /* CCSR Base Addr Low */
25 u32 ccsrar
; /* CCSR Attr */
26 #define CCSRAR_C 0x80000000 /* Commit */
28 u32 altcbarh
; /* Alternate Configuration Base Addr High */
29 u32 altcbarl
; /* Alternate Configuration Base Addr Low */
30 u32 altcar
; /* Alternate Configuration Attr */
32 u32 bstrh
; /* Boot space translation high */
33 u32 bstrl
; /* Boot space translation Low */
34 u32 bstrar
; /* Boot space translation attributes */
37 u32 lawbarh
; /* LAWn base addr high */
38 u32 lawbarl
; /* LAWn base addr low */
39 u32 lawar
; /* LAWn attributes */
45 /* Local-Access Registers & ECM Registers */
46 typedef struct ccsr_local_ecm
{
47 u32 ccsrbar
; /* CCSR Base Addr */
49 u32 altcbar
; /* Alternate Configuration Base Addr */
51 u32 altcar
; /* Alternate Configuration Attr */
53 u32 bptr
; /* Boot Page Translation */
55 u32 lawbar0
; /* Local Access Window 0 Base Addr */
57 u32 lawar0
; /* Local Access Window 0 Attrs */
59 u32 lawbar1
; /* Local Access Window 1 Base Addr */
61 u32 lawar1
; /* Local Access Window 1 Attrs */
63 u32 lawbar2
; /* Local Access Window 2 Base Addr */
65 u32 lawar2
; /* Local Access Window 2 Attrs */
67 u32 lawbar3
; /* Local Access Window 3 Base Addr */
69 u32 lawar3
; /* Local Access Window 3 Attrs */
71 u32 lawbar4
; /* Local Access Window 4 Base Addr */
73 u32 lawar4
; /* Local Access Window 4 Attrs */
75 u32 lawbar5
; /* Local Access Window 5 Base Addr */
77 u32 lawar5
; /* Local Access Window 5 Attrs */
79 u32 lawbar6
; /* Local Access Window 6 Base Addr */
81 u32 lawar6
; /* Local Access Window 6 Attrs */
83 u32 lawbar7
; /* Local Access Window 7 Base Addr */
85 u32 lawar7
; /* Local Access Window 7 Attrs */
87 u32 lawbar8
; /* Local Access Window 8 Base Addr */
89 u32 lawar8
; /* Local Access Window 8 Attrs */
91 u32 lawbar9
; /* Local Access Window 9 Base Addr */
93 u32 lawar9
; /* Local Access Window 9 Attrs */
95 u32 lawbar10
; /* Local Access Window 10 Base Addr */
97 u32 lawar10
; /* Local Access Window 10 Attrs */
99 u32 lawbar11
; /* Local Access Window 11 Base Addr */
101 u32 lawar11
; /* Local Access Window 11 Attrs */
103 u32 eebacr
; /* ECM CCB Addr Configuration */
105 u32 eebpcr
; /* ECM CCB Port Configuration */
107 u32 eedr
; /* ECM Error Detect */
109 u32 eeer
; /* ECM Error Enable */
110 u32 eeatr
; /* ECM Error Attrs Capture */
111 u32 eeadr
; /* ECM Error Addr Capture */
115 /* DDR memory controller registers */
116 typedef struct ccsr_ddr
{
117 u32 cs0_bnds
; /* Chip Select 0 Memory Bounds */
119 u32 cs1_bnds
; /* Chip Select 1 Memory Bounds */
121 u32 cs2_bnds
; /* Chip Select 2 Memory Bounds */
123 u32 cs3_bnds
; /* Chip Select 3 Memory Bounds */
125 u32 cs0_config
; /* Chip Select Configuration */
126 u32 cs1_config
; /* Chip Select Configuration */
127 u32 cs2_config
; /* Chip Select Configuration */
128 u32 cs3_config
; /* Chip Select Configuration */
130 u32 cs0_config_2
; /* Chip Select Configuration 2 */
131 u32 cs1_config_2
; /* Chip Select Configuration 2 */
132 u32 cs2_config_2
; /* Chip Select Configuration 2 */
133 u32 cs3_config_2
; /* Chip Select Configuration 2 */
135 u32 timing_cfg_3
; /* SDRAM Timing Configuration 3 */
136 u32 timing_cfg_0
; /* SDRAM Timing Configuration 0 */
137 u32 timing_cfg_1
; /* SDRAM Timing Configuration 1 */
138 u32 timing_cfg_2
; /* SDRAM Timing Configuration 2 */
139 u32 sdram_cfg
; /* SDRAM Control Configuration */
140 u32 sdram_cfg_2
; /* SDRAM Control Configuration 2 */
141 u32 sdram_mode
; /* SDRAM Mode Configuration */
142 u32 sdram_mode_2
; /* SDRAM Mode Configuration 2 */
143 u32 sdram_md_cntl
; /* SDRAM Mode Control */
144 u32 sdram_interval
; /* SDRAM Interval Configuration */
145 u32 sdram_data_init
; /* SDRAM Data initialization */
147 u32 sdram_clk_cntl
; /* SDRAM Clock Control */
149 u32 init_addr
; /* training init addr */
150 u32 init_ext_addr
; /* training init extended addr */
152 u32 timing_cfg_4
; /* SDRAM Timing Configuration 4 */
153 u32 timing_cfg_5
; /* SDRAM Timing Configuration 5 */
155 u32 ddr_zq_cntl
; /* ZQ calibration control*/
156 u32 ddr_wrlvl_cntl
; /* write leveling control*/
158 u32 ddr_sr_cntr
; /* self refresh counter */
159 u32 ddr_sdram_rcw_1
; /* Control Words 1 */
160 u32 ddr_sdram_rcw_2
; /* Control Words 2 */
162 u32 ddr_wrlvl_cntl_2
; /* write leveling control 2 */
163 u32 ddr_wrlvl_cntl_3
; /* write leveling control 3 */
165 u32 sdram_mode_3
; /* SDRAM Mode Configuration 3 */
166 u32 sdram_mode_4
; /* SDRAM Mode Configuration 4 */
167 u32 sdram_mode_5
; /* SDRAM Mode Configuration 5 */
168 u32 sdram_mode_6
; /* SDRAM Mode Configuration 6 */
169 u32 sdram_mode_7
; /* SDRAM Mode Configuration 7 */
170 u32 sdram_mode_8
; /* SDRAM Mode Configuration 8 */
172 u32 ddr_dsr1
; /* Debug Status 1 */
173 u32 ddr_dsr2
; /* Debug Status 2 */
174 u32 ddr_cdr1
; /* Control Driver 1 */
175 u32 ddr_cdr2
; /* Control Driver 2 */
177 u32 ip_rev1
; /* IP Block Revision 1 */
178 u32 ip_rev2
; /* IP Block Revision 2 */
179 u32 eor
; /* Enhanced Optimization Register */
181 u32 mtcr
; /* Memory Test Control Register */
183 u32 mtp1
; /* Memory Test Pattern 1 */
184 u32 mtp2
; /* Memory Test Pattern 2 */
185 u32 mtp3
; /* Memory Test Pattern 3 */
186 u32 mtp4
; /* Memory Test Pattern 4 */
187 u32 mtp5
; /* Memory Test Pattern 5 */
188 u32 mtp6
; /* Memory Test Pattern 6 */
189 u32 mtp7
; /* Memory Test Pattern 7 */
190 u32 mtp8
; /* Memory Test Pattern 8 */
191 u32 mtp9
; /* Memory Test Pattern 9 */
192 u32 mtp10
; /* Memory Test Pattern 10 */
194 u32 data_err_inject_hi
; /* Data Path Err Injection Mask High */
195 u32 data_err_inject_lo
; /* Data Path Err Injection Mask Low */
196 u32 ecc_err_inject
; /* Data Path Err Injection Mask ECC */
198 u32 capture_data_hi
; /* Data Path Read Capture High */
199 u32 capture_data_lo
; /* Data Path Read Capture Low */
200 u32 capture_ecc
; /* Data Path Read Capture ECC */
202 u32 err_detect
; /* Error Detect */
203 u32 err_disable
; /* Error Disable */
205 u32 capture_attributes
; /* Error Attrs Capture */
206 u32 capture_address
; /* Error Addr Capture */
207 u32 capture_ext_address
; /* Error Extended Addr Capture */
208 u32 err_sbe
; /* Single-Bit ECC Error Management */
210 u32 debug
[32]; /* debug_1 to debug_32 */
214 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
215 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
218 typedef struct ccsr_i2c
{
219 struct fsl_i2c i2c
[1];
220 u8 res
[4096 - 1 * sizeof(struct fsl_i2c
)];
223 #if defined(CONFIG_MPC8540) \
224 || defined(CONFIG_MPC8541) \
225 || defined(CONFIG_MPC8548) \
226 || defined(CONFIG_MPC8555)
227 /* DUART Registers */
228 typedef struct ccsr_duart
{
230 /* URBR1, UTHR1, UDLB1 with the same addr */
231 u8 urbr1_uthr1_udlb1
;
232 /* UIER1, UDMB1 with the same addr01 */
234 /* UIIR1, UFCR1, UAFR1 with the same addr */
235 u8 uiir1_ufcr1_uafr1
;
236 u8 ulcr1
; /* UART1 Line Control */
237 u8 umcr1
; /* UART1 Modem Control */
238 u8 ulsr1
; /* UART1 Line Status */
239 u8 umsr1
; /* UART1 Modem Status */
240 u8 uscr1
; /* UART1 Scratch */
242 u8 udsr1
; /* UART1 DMA Status */
244 /* URBR2, UTHR2, UDLB2 with the same addr */
245 u8 urbr2_uthr2_udlb2
;
246 /* UIER2, UDMB2 with the same addr */
248 /* UIIR2, UFCR2, UAFR2 with the same addr */
249 u8 uiir2_ufcr2_uafr2
;
250 u8 ulcr2
; /* UART2 Line Control */
251 u8 umcr2
; /* UART2 Modem Control */
252 u8 ulsr2
; /* UART2 Line Status */
253 u8 umsr2
; /* UART2 Modem Status */
254 u8 uscr2
; /* UART2 Scratch */
256 u8 udsr2
; /* UART2 DMA Status */
259 #else /* MPC8560 uses UART on its CPM */
260 typedef struct ccsr_duart
{
266 typedef struct ccsr_espi
{
267 u32 mode
; /* eSPI mode */
268 u32 event
; /* eSPI event */
269 u32 mask
; /* eSPI mask */
270 u32 com
; /* eSPI command */
271 u32 tx
; /* eSPI transmit FIFO access */
272 u32 rx
; /* eSPI receive FIFO access */
273 u8 res1
[8]; /* reserved */
274 u32 csmode
[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
275 u8 res2
[4048]; /* fill up to 0x1000 */
279 typedef struct ccsr_pcix
{
280 u32 cfg_addr
; /* PCIX Configuration Addr */
281 u32 cfg_data
; /* PCIX Configuration Data */
282 u32 int_ack
; /* PCIX IRQ Acknowledge */
284 u32 liodn_base
; /* PCIX LIODN base register */
286 u32 potar0
; /* PCIX Outbound Transaction Addr 0 */
287 u32 potear0
; /* PCIX Outbound Translation Extended Addr 0 */
288 u32 powbar0
; /* PCIX Outbound Window Base Addr 0 */
289 u32 powbear0
; /* PCIX Outbound Window Base Extended Addr 0 */
290 u32 powar0
; /* PCIX Outbound Window Attrs 0 */
292 u32 potar1
; /* PCIX Outbound Transaction Addr 1 */
293 u32 potear1
; /* PCIX Outbound Translation Extended Addr 1 */
294 u32 powbar1
; /* PCIX Outbound Window Base Addr 1 */
295 u32 powbear1
; /* PCIX Outbound Window Base Extended Addr 1 */
296 u32 powar1
; /* PCIX Outbound Window Attrs 1 */
298 u32 potar2
; /* PCIX Outbound Transaction Addr 2 */
299 u32 potear2
; /* PCIX Outbound Translation Extended Addr 2 */
300 u32 powbar2
; /* PCIX Outbound Window Base Addr 2 */
301 u32 powbear2
; /* PCIX Outbound Window Base Extended Addr 2 */
302 u32 powar2
; /* PCIX Outbound Window Attrs 2 */
304 u32 potar3
; /* PCIX Outbound Transaction Addr 3 */
305 u32 potear3
; /* PCIX Outbound Translation Extended Addr 3 */
306 u32 powbar3
; /* PCIX Outbound Window Base Addr 3 */
307 u32 powbear3
; /* PCIX Outbound Window Base Extended Addr 3 */
308 u32 powar3
; /* PCIX Outbound Window Attrs 3 */
310 u32 potar4
; /* PCIX Outbound Transaction Addr 4 */
311 u32 potear4
; /* PCIX Outbound Translation Extended Addr 4 */
312 u32 powbar4
; /* PCIX Outbound Window Base Addr 4 */
313 u32 powbear4
; /* PCIX Outbound Window Base Extended Addr 4 */
314 u32 powar4
; /* PCIX Outbound Window Attrs 4 */
316 u32 pitar3
; /* PCIX Inbound Translation Addr 3 */
317 u32 pitear3
; /* PCIX Inbound Translation Extended Addr 3 */
318 u32 piwbar3
; /* PCIX Inbound Window Base Addr 3 */
319 u32 piwbear3
; /* PCIX Inbound Window Base Extended Addr 3 */
320 u32 piwar3
; /* PCIX Inbound Window Attrs 3 */
322 u32 pitar2
; /* PCIX Inbound Translation Addr 2 */
323 u32 pitear2
; /* PCIX Inbound Translation Extended Addr 2 */
324 u32 piwbar2
; /* PCIX Inbound Window Base Addr 2 */
325 u32 piwbear2
; /* PCIX Inbound Window Base Extended Addr 2 */
326 u32 piwar2
; /* PCIX Inbound Window Attrs 2 */
328 u32 pitar1
; /* PCIX Inbound Translation Addr 1 */
329 u32 pitear1
; /* PCIX Inbound Translation Extended Addr 1 */
330 u32 piwbar1
; /* PCIX Inbound Window Base Addr 1 */
332 u32 piwar1
; /* PCIX Inbound Window Attrs 1 */
334 u32 pedr
; /* PCIX Error Detect */
335 u32 pecdr
; /* PCIX Error Capture Disable */
336 u32 peer
; /* PCIX Error Enable */
337 u32 peattrcr
; /* PCIX Error Attrs Capture */
338 u32 peaddrcr
; /* PCIX Error Addr Capture */
339 u32 peextaddrcr
; /* PCIX Error Extended Addr Capture */
340 u32 pedlcr
; /* PCIX Error Data Low Capture */
341 u32 pedhcr
; /* PCIX Error Error Data High Capture */
342 u32 gas_timr
; /* PCIX Gasket Timer */
346 #define PCIX_COMMAND 0x62
347 #define POWAR_EN 0x80000000
348 #define POWAR_IO_READ 0x00080000
349 #define POWAR_MEM_READ 0x00040000
350 #define POWAR_IO_WRITE 0x00008000
351 #define POWAR_MEM_WRITE 0x00004000
352 #define POWAR_MEM_512M 0x0000001c
353 #define POWAR_IO_1M 0x00000013
355 #define PIWAR_EN 0x80000000
356 #define PIWAR_PF 0x20000000
357 #define PIWAR_LOCAL 0x00f00000
358 #define PIWAR_READ_SNOOP 0x00050000
359 #define PIWAR_WRITE_SNOOP 0x00005000
360 #define PIWAR_MEM_2G 0x0000001e
362 typedef struct ccsr_gpio
{
371 /* L2 Cache Registers */
372 typedef struct ccsr_l2cache
{
373 u32 l2ctl
; /* L2 configuration 0 */
375 u32 l2cewar0
; /* L2 cache external write addr 0 */
377 u32 l2cewcr0
; /* L2 cache external write control 0 */
379 u32 l2cewar1
; /* L2 cache external write addr 1 */
381 u32 l2cewcr1
; /* L2 cache external write control 1 */
383 u32 l2cewar2
; /* L2 cache external write addr 2 */
385 u32 l2cewcr2
; /* L2 cache external write control 2 */
387 u32 l2cewar3
; /* L2 cache external write addr 3 */
389 u32 l2cewcr3
; /* L2 cache external write control 3 */
391 u32 l2srbar0
; /* L2 memory-mapped SRAM base addr 0 */
393 u32 l2srbar1
; /* L2 memory-mapped SRAM base addr 1 */
395 u32 l2errinjhi
; /* L2 error injection mask high */
396 u32 l2errinjlo
; /* L2 error injection mask low */
397 u32 l2errinjctl
; /* L2 error injection tag/ECC control */
399 u32 l2captdatahi
; /* L2 error data high capture */
400 u32 l2captdatalo
; /* L2 error data low capture */
401 u32 l2captecc
; /* L2 error ECC capture */
403 u32 l2errdet
; /* L2 error detect */
404 u32 l2errdis
; /* L2 error disable */
405 u32 l2errinten
; /* L2 error interrupt enable */
406 u32 l2errattr
; /* L2 error attributes capture */
407 u32 l2erraddr
; /* L2 error addr capture */
409 u32 l2errctl
; /* L2 error control */
413 #define MPC85xx_L2CTL_L2E 0x80000000
414 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
415 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
416 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
419 typedef struct ccsr_dma
{
421 struct fsl_dma dma
[4];
422 u32 dgsr
; /* DMA General Status */
427 typedef struct ccsr_tsec
{
429 u32 ievent
; /* IRQ Event */
430 u32 imask
; /* IRQ Mask */
431 u32 edis
; /* Error Disabled */
433 u32 ecntrl
; /* Ethernet Control */
434 u32 minflr
; /* Minimum Frame Len */
435 u32 ptv
; /* Pause Time Value */
436 u32 dmactrl
; /* DMA Control */
437 u32 tbipa
; /* TBI PHY Addr */
439 u32 fifo_tx_thr
; /* FIFO transmit threshold */
441 u32 fifo_tx_starve
; /* FIFO transmit starve */
442 u32 fifo_tx_starve_shutoff
; /* FIFO transmit starve shutoff */
444 u32 tctrl
; /* TX Control */
445 u32 tstat
; /* TX Status */
447 u32 tbdlen
; /* TX Buffer Desc Data Len */
449 u32 ctbptrh
; /* Current TX Buffer Desc Ptr High */
450 u32 ctbptr
; /* Current TX Buffer Desc Ptr */
452 u32 tbptrh
; /* TX Buffer Desc Ptr High */
453 u32 tbptr
; /* TX Buffer Desc Ptr Low */
455 u32 tbaseh
; /* TX Desc Base Addr High */
456 u32 tbase
; /* TX Desc Base Addr */
458 u32 ostbd
; /* Out-of-Sequence(OOS) TX Buffer Desc */
459 u32 ostbdp
; /* OOS TX Data Buffer Ptr */
460 u32 os32tbdp
; /* OOS 32 Bytes TX Data Buffer Ptr Low */
461 u32 os32iptrh
; /* OOS 32 Bytes TX Insert Ptr High */
462 u32 os32iptrl
; /* OOS 32 Bytes TX Insert Ptr Low */
463 u32 os32tbdr
; /* OOS 32 Bytes TX Reserved */
464 u32 os32iil
; /* OOS 32 Bytes TX Insert Idx/Len */
466 u32 rctrl
; /* RX Control */
467 u32 rstat
; /* RX Status */
469 u32 rbdlen
; /* RxBD Data Len */
471 u32 crbptrh
; /* Current RX Buffer Desc Ptr High */
472 u32 crbptr
; /* Current RX Buffer Desc Ptr */
474 u32 mrblr
; /* Maximum RX Buffer Len */
475 u32 mrblr2r3
; /* Maximum RX Buffer Len R2R3 */
477 u32 rbptrh
; /* RX Buffer Desc Ptr High 0 */
478 u32 rbptr
; /* RX Buffer Desc Ptr */
479 u32 rbptrh1
; /* RX Buffer Desc Ptr High 1 */
480 u32 rbptrl1
; /* RX Buffer Desc Ptr Low 1 */
481 u32 rbptrh2
; /* RX Buffer Desc Ptr High 2 */
482 u32 rbptrl2
; /* RX Buffer Desc Ptr Low 2 */
483 u32 rbptrh3
; /* RX Buffer Desc Ptr High 3 */
484 u32 rbptrl3
; /* RX Buffer Desc Ptr Low 3 */
486 u32 rbaseh
; /* RX Desc Base Addr High 0 */
487 u32 rbase
; /* RX Desc Base Addr */
488 u32 rbaseh1
; /* RX Desc Base Addr High 1 */
489 u32 rbasel1
; /* RX Desc Base Addr Low 1 */
490 u32 rbaseh2
; /* RX Desc Base Addr High 2 */
491 u32 rbasel2
; /* RX Desc Base Addr Low 2 */
492 u32 rbaseh3
; /* RX Desc Base Addr High 3 */
493 u32 rbasel3
; /* RX Desc Base Addr Low 3 */
495 u32 maccfg1
; /* MAC Configuration 1 */
496 u32 maccfg2
; /* MAC Configuration 2 */
497 u32 ipgifg
; /* Inter Packet Gap/Inter Frame Gap */
498 u32 hafdup
; /* Half Duplex */
499 u32 maxfrm
; /* Maximum Frame Len */
501 u32 miimcfg
; /* MII Management Configuration */
502 u32 miimcom
; /* MII Management Cmd */
503 u32 miimadd
; /* MII Management Addr */
504 u32 miimcon
; /* MII Management Control */
505 u32 miimstat
; /* MII Management Status */
506 u32 miimind
; /* MII Management Indicator */
508 u32 ifstat
; /* Interface Status */
509 u32 macstnaddr1
; /* Station Addr Part 1 */
510 u32 macstnaddr2
; /* Station Addr Part 2 */
512 u32 tr64
; /* TX & RX 64-byte Frame Counter */
513 u32 tr127
; /* TX & RX 65-127 byte Frame Counter */
514 u32 tr255
; /* TX & RX 128-255 byte Frame Counter */
515 u32 tr511
; /* TX & RX 256-511 byte Frame Counter */
516 u32 tr1k
; /* TX & RX 512-1023 byte Frame Counter */
517 u32 trmax
; /* TX & RX 1024-1518 byte Frame Counter */
518 u32 trmgv
; /* TX & RX 1519-1522 byte Good VLAN Frame */
519 u32 rbyt
; /* RX Byte Counter */
520 u32 rpkt
; /* RX Packet Counter */
521 u32 rfcs
; /* RX FCS Error Counter */
522 u32 rmca
; /* RX Multicast Packet Counter */
523 u32 rbca
; /* RX Broadcast Packet Counter */
524 u32 rxcf
; /* RX Control Frame Packet Counter */
525 u32 rxpf
; /* RX Pause Frame Packet Counter */
526 u32 rxuo
; /* RX Unknown OP Code Counter */
527 u32 raln
; /* RX Alignment Error Counter */
528 u32 rflr
; /* RX Frame Len Error Counter */
529 u32 rcde
; /* RX Code Error Counter */
530 u32 rcse
; /* RX Carrier Sense Error Counter */
531 u32 rund
; /* RX Undersize Packet Counter */
532 u32 rovr
; /* RX Oversize Packet Counter */
533 u32 rfrg
; /* RX Fragments Counter */
534 u32 rjbr
; /* RX Jabber Counter */
535 u32 rdrp
; /* RX Drop Counter */
536 u32 tbyt
; /* TX Byte Counter Counter */
537 u32 tpkt
; /* TX Packet Counter */
538 u32 tmca
; /* TX Multicast Packet Counter */
539 u32 tbca
; /* TX Broadcast Packet Counter */
540 u32 txpf
; /* TX Pause Control Frame Counter */
541 u32 tdfr
; /* TX Deferral Packet Counter */
542 u32 tedf
; /* TX Excessive Deferral Packet Counter */
543 u32 tscl
; /* TX Single Collision Packet Counter */
544 u32 tmcl
; /* TX Multiple Collision Packet Counter */
545 u32 tlcl
; /* TX Late Collision Packet Counter */
546 u32 txcl
; /* TX Excessive Collision Packet Counter */
547 u32 tncl
; /* TX Total Collision Counter */
549 u32 tdrp
; /* TX Drop Frame Counter */
550 u32 tjbr
; /* TX Jabber Frame Counter */
551 u32 tfcs
; /* TX FCS Error Counter */
552 u32 txcf
; /* TX Control Frame Counter */
553 u32 tovr
; /* TX Oversize Frame Counter */
554 u32 tund
; /* TX Undersize Frame Counter */
555 u32 tfrg
; /* TX Fragments Frame Counter */
556 u32 car1
; /* Carry One */
557 u32 car2
; /* Carry Two */
558 u32 cam1
; /* Carry Mask One */
559 u32 cam2
; /* Carry Mask Two */
561 u32 iaddr0
; /* Indivdual addr 0 */
562 u32 iaddr1
; /* Indivdual addr 1 */
563 u32 iaddr2
; /* Indivdual addr 2 */
564 u32 iaddr3
; /* Indivdual addr 3 */
565 u32 iaddr4
; /* Indivdual addr 4 */
566 u32 iaddr5
; /* Indivdual addr 5 */
567 u32 iaddr6
; /* Indivdual addr 6 */
568 u32 iaddr7
; /* Indivdual addr 7 */
570 u32 gaddr0
; /* Global addr 0 */
571 u32 gaddr1
; /* Global addr 1 */
572 u32 gaddr2
; /* Global addr 2 */
573 u32 gaddr3
; /* Global addr 3 */
574 u32 gaddr4
; /* Global addr 4 */
575 u32 gaddr5
; /* Global addr 5 */
576 u32 gaddr6
; /* Global addr 6 */
577 u32 gaddr7
; /* Global addr 7 */
579 u32 pmd0
; /* Pattern Match Data */
581 u32 pmask0
; /* Pattern Mask */
583 u32 pcntrl0
; /* Pattern Match Control */
585 u32 pattrb0
; /* Pattern Match Attrs */
586 u32 pattrbeli0
; /* Pattern Match Attrs Extract Len & Idx */
587 u32 pmd1
; /* Pattern Match Data */
589 u32 pmask1
; /* Pattern Mask */
591 u32 pcntrl1
; /* Pattern Match Control */
593 u32 pattrb1
; /* Pattern Match Attrs */
594 u32 pattrbeli1
; /* Pattern Match Attrs Extract Len & Idx */
595 u32 pmd2
; /* Pattern Match Data */
597 u32 pmask2
; /* Pattern Mask */
599 u32 pcntrl2
; /* Pattern Match Control */
601 u32 pattrb2
; /* Pattern Match Attrs */
602 u32 pattrbeli2
; /* Pattern Match Attrs Extract Len & Idx */
603 u32 pmd3
; /* Pattern Match Data */
605 u32 pmask3
; /* Pattern Mask */
607 u32 pcntrl3
; /* Pattern Match Control */
609 u32 pattrb3
; /* Pattern Match Attrs */
610 u32 pattrbeli3
; /* Pattern Match Attrs Extract Len & Idx */
611 u32 pmd4
; /* Pattern Match Data */
613 u32 pmask4
; /* Pattern Mask */
615 u32 pcntrl4
; /* Pattern Match Control */
617 u32 pattrb4
; /* Pattern Match Attrs */
618 u32 pattrbeli4
; /* Pattern Match Attrs Extract Len & Idx */
619 u32 pmd5
; /* Pattern Match Data */
621 u32 pmask5
; /* Pattern Mask */
623 u32 pcntrl5
; /* Pattern Match Control */
625 u32 pattrb5
; /* Pattern Match Attrs */
626 u32 pattrbeli5
; /* Pattern Match Attrs Extract Len & Idx */
627 u32 pmd6
; /* Pattern Match Data */
629 u32 pmask6
; /* Pattern Mask */
631 u32 pcntrl6
; /* Pattern Match Control */
633 u32 pattrb6
; /* Pattern Match Attrs */
634 u32 pattrbeli6
; /* Pattern Match Attrs Extract Len & Idx */
635 u32 pmd7
; /* Pattern Match Data */
637 u32 pmask7
; /* Pattern Mask */
639 u32 pcntrl7
; /* Pattern Match Control */
641 u32 pattrb7
; /* Pattern Match Attrs */
642 u32 pattrbeli7
; /* Pattern Match Attrs Extract Len & Idx */
643 u32 pmd8
; /* Pattern Match Data */
645 u32 pmask8
; /* Pattern Mask */
647 u32 pcntrl8
; /* Pattern Match Control */
649 u32 pattrb8
; /* Pattern Match Attrs */
650 u32 pattrbeli8
; /* Pattern Match Attrs Extract Len & Idx */
651 u32 pmd9
; /* Pattern Match Data */
653 u32 pmask9
; /* Pattern Mask */
655 u32 pcntrl9
; /* Pattern Match Control */
657 u32 pattrb9
; /* Pattern Match Attrs */
658 u32 pattrbeli9
; /* Pattern Match Attrs Extract Len & Idx */
659 u32 pmd10
; /* Pattern Match Data */
661 u32 pmask10
; /* Pattern Mask */
663 u32 pcntrl10
; /* Pattern Match Control */
665 u32 pattrb10
; /* Pattern Match Attrs */
666 u32 pattrbeli10
; /* Pattern Match Attrs Extract Len & Idx */
667 u32 pmd11
; /* Pattern Match Data */
669 u32 pmask11
; /* Pattern Mask */
671 u32 pcntrl11
; /* Pattern Match Control */
673 u32 pattrb11
; /* Pattern Match Attrs */
674 u32 pattrbeli11
; /* Pattern Match Attrs Extract Len & Idx */
675 u32 pmd12
; /* Pattern Match Data */
677 u32 pmask12
; /* Pattern Mask */
679 u32 pcntrl12
; /* Pattern Match Control */
681 u32 pattrb12
; /* Pattern Match Attrs */
682 u32 pattrbeli12
; /* Pattern Match Attrs Extract Len & Idx */
683 u32 pmd13
; /* Pattern Match Data */
685 u32 pmask13
; /* Pattern Mask */
687 u32 pcntrl13
; /* Pattern Match Control */
689 u32 pattrb13
; /* Pattern Match Attrs */
690 u32 pattrbeli13
; /* Pattern Match Attrs Extract Len & Idx */
691 u32 pmd14
; /* Pattern Match Data */
693 u32 pmask14
; /* Pattern Mask */
695 u32 pcntrl14
; /* Pattern Match Control */
697 u32 pattrb14
; /* Pattern Match Attrs */
698 u32 pattrbeli14
; /* Pattern Match Attrs Extract Len & Idx */
699 u32 pmd15
; /* Pattern Match Data */
701 u32 pmask15
; /* Pattern Mask */
703 u32 pcntrl15
; /* Pattern Match Control */
705 u32 pattrb15
; /* Pattern Match Attrs */
706 u32 pattrbeli15
; /* Pattern Match Attrs Extract Len & Idx */
708 u32 attr
; /* Attrs */
709 u32 attreli
; /* Attrs Extract Len & Idx */
714 typedef struct ccsr_pic
{
716 u32 ipidr0
; /* Interprocessor IRQ Dispatch 0 */
718 u32 ipidr1
; /* Interprocessor IRQ Dispatch 1 */
720 u32 ipidr2
; /* Interprocessor IRQ Dispatch 2 */
722 u32 ipidr3
; /* Interprocessor IRQ Dispatch 3 */
724 u32 ctpr
; /* Current Task Priority */
726 u32 whoami
; /* Who Am I */
728 u32 iack
; /* IRQ Acknowledge */
730 u32 eoi
; /* End Of IRQ */
732 u32 frr
; /* Feature Reporting */
734 u32 gcr
; /* Global Configuration */
735 #define MPC85xx_PICGCR_RST 0x80000000
736 #define MPC85xx_PICGCR_M 0x20000000
738 u32 vir
; /* Vendor Identification */
740 u32 pir
; /* Processor Initialization */
742 u32 ipivpr0
; /* IPI Vector/Priority 0 */
744 u32 ipivpr1
; /* IPI Vector/Priority 1 */
746 u32 ipivpr2
; /* IPI Vector/Priority 2 */
748 u32 ipivpr3
; /* IPI Vector/Priority 3 */
750 u32 svr
; /* Spurious Vector */
752 u32 tfrr
; /* Timer Frequency Reporting */
754 u32 gtccr0
; /* Global Timer Current Count 0 */
756 u32 gtbcr0
; /* Global Timer Base Count 0 */
758 u32 gtvpr0
; /* Global Timer Vector/Priority 0 */
760 u32 gtdr0
; /* Global Timer Destination 0 */
762 u32 gtccr1
; /* Global Timer Current Count 1 */
764 u32 gtbcr1
; /* Global Timer Base Count 1 */
766 u32 gtvpr1
; /* Global Timer Vector/Priority 1 */
768 u32 gtdr1
; /* Global Timer Destination 1 */
770 u32 gtccr2
; /* Global Timer Current Count 2 */
772 u32 gtbcr2
; /* Global Timer Base Count 2 */
774 u32 gtvpr2
; /* Global Timer Vector/Priority 2 */
776 u32 gtdr2
; /* Global Timer Destination 2 */
778 u32 gtccr3
; /* Global Timer Current Count 3 */
780 u32 gtbcr3
; /* Global Timer Base Count 3 */
782 u32 gtvpr3
; /* Global Timer Vector/Priority 3 */
784 u32 gtdr3
; /* Global Timer Destination 3 */
786 u32 tcr
; /* Timer Control */
788 u32 irqsr0
; /* IRQ_OUT Summary 0 */
790 u32 irqsr1
; /* IRQ_OUT Summary 1 */
792 u32 cisr0
; /* Critical IRQ Summary 0 */
794 u32 cisr1
; /* Critical IRQ Summary 1 */
796 u32 msgr0
; /* Message 0 */
798 u32 msgr1
; /* Message 1 */
800 u32 msgr2
; /* Message 2 */
802 u32 msgr3
; /* Message 3 */
804 u32 mer
; /* Message Enable */
806 u32 msr
; /* Message Status */
808 u32 eivpr0
; /* External IRQ Vector/Priority 0 */
810 u32 eidr0
; /* External IRQ Destination 0 */
812 u32 eivpr1
; /* External IRQ Vector/Priority 1 */
814 u32 eidr1
; /* External IRQ Destination 1 */
816 u32 eivpr2
; /* External IRQ Vector/Priority 2 */
818 u32 eidr2
; /* External IRQ Destination 2 */
820 u32 eivpr3
; /* External IRQ Vector/Priority 3 */
822 u32 eidr3
; /* External IRQ Destination 3 */
824 u32 eivpr4
; /* External IRQ Vector/Priority 4 */
826 u32 eidr4
; /* External IRQ Destination 4 */
828 u32 eivpr5
; /* External IRQ Vector/Priority 5 */
830 u32 eidr5
; /* External IRQ Destination 5 */
832 u32 eivpr6
; /* External IRQ Vector/Priority 6 */
834 u32 eidr6
; /* External IRQ Destination 6 */
836 u32 eivpr7
; /* External IRQ Vector/Priority 7 */
838 u32 eidr7
; /* External IRQ Destination 7 */
840 u32 eivpr8
; /* External IRQ Vector/Priority 8 */
842 u32 eidr8
; /* External IRQ Destination 8 */
844 u32 eivpr9
; /* External IRQ Vector/Priority 9 */
846 u32 eidr9
; /* External IRQ Destination 9 */
848 u32 eivpr10
; /* External IRQ Vector/Priority 10 */
850 u32 eidr10
; /* External IRQ Destination 10 */
852 u32 eivpr11
; /* External IRQ Vector/Priority 11 */
854 u32 eidr11
; /* External IRQ Destination 11 */
856 u32 iivpr0
; /* Internal IRQ Vector/Priority 0 */
858 u32 iidr0
; /* Internal IRQ Destination 0 */
860 u32 iivpr1
; /* Internal IRQ Vector/Priority 1 */
862 u32 iidr1
; /* Internal IRQ Destination 1 */
864 u32 iivpr2
; /* Internal IRQ Vector/Priority 2 */
866 u32 iidr2
; /* Internal IRQ Destination 2 */
868 u32 iivpr3
; /* Internal IRQ Vector/Priority 3 */
870 u32 iidr3
; /* Internal IRQ Destination 3 */
872 u32 iivpr4
; /* Internal IRQ Vector/Priority 4 */
874 u32 iidr4
; /* Internal IRQ Destination 4 */
876 u32 iivpr5
; /* Internal IRQ Vector/Priority 5 */
878 u32 iidr5
; /* Internal IRQ Destination 5 */
880 u32 iivpr6
; /* Internal IRQ Vector/Priority 6 */
882 u32 iidr6
; /* Internal IRQ Destination 6 */
884 u32 iivpr7
; /* Internal IRQ Vector/Priority 7 */
886 u32 iidr7
; /* Internal IRQ Destination 7 */
888 u32 iivpr8
; /* Internal IRQ Vector/Priority 8 */
890 u32 iidr8
; /* Internal IRQ Destination 8 */
892 u32 iivpr9
; /* Internal IRQ Vector/Priority 9 */
894 u32 iidr9
; /* Internal IRQ Destination 9 */
896 u32 iivpr10
; /* Internal IRQ Vector/Priority 10 */
898 u32 iidr10
; /* Internal IRQ Destination 10 */
900 u32 iivpr11
; /* Internal IRQ Vector/Priority 11 */
902 u32 iidr11
; /* Internal IRQ Destination 11 */
904 u32 iivpr12
; /* Internal IRQ Vector/Priority 12 */
906 u32 iidr12
; /* Internal IRQ Destination 12 */
908 u32 iivpr13
; /* Internal IRQ Vector/Priority 13 */
910 u32 iidr13
; /* Internal IRQ Destination 13 */
912 u32 iivpr14
; /* Internal IRQ Vector/Priority 14 */
914 u32 iidr14
; /* Internal IRQ Destination 14 */
916 u32 iivpr15
; /* Internal IRQ Vector/Priority 15 */
918 u32 iidr15
; /* Internal IRQ Destination 15 */
920 u32 iivpr16
; /* Internal IRQ Vector/Priority 16 */
922 u32 iidr16
; /* Internal IRQ Destination 16 */
924 u32 iivpr17
; /* Internal IRQ Vector/Priority 17 */
926 u32 iidr17
; /* Internal IRQ Destination 17 */
928 u32 iivpr18
; /* Internal IRQ Vector/Priority 18 */
930 u32 iidr18
; /* Internal IRQ Destination 18 */
932 u32 iivpr19
; /* Internal IRQ Vector/Priority 19 */
934 u32 iidr19
; /* Internal IRQ Destination 19 */
936 u32 iivpr20
; /* Internal IRQ Vector/Priority 20 */
938 u32 iidr20
; /* Internal IRQ Destination 20 */
940 u32 iivpr21
; /* Internal IRQ Vector/Priority 21 */
942 u32 iidr21
; /* Internal IRQ Destination 21 */
944 u32 iivpr22
; /* Internal IRQ Vector/Priority 22 */
946 u32 iidr22
; /* Internal IRQ Destination 22 */
948 u32 iivpr23
; /* Internal IRQ Vector/Priority 23 */
950 u32 iidr23
; /* Internal IRQ Destination 23 */
952 u32 iivpr24
; /* Internal IRQ Vector/Priority 24 */
954 u32 iidr24
; /* Internal IRQ Destination 24 */
956 u32 iivpr25
; /* Internal IRQ Vector/Priority 25 */
958 u32 iidr25
; /* Internal IRQ Destination 25 */
960 u32 iivpr26
; /* Internal IRQ Vector/Priority 26 */
962 u32 iidr26
; /* Internal IRQ Destination 26 */
964 u32 iivpr27
; /* Internal IRQ Vector/Priority 27 */
966 u32 iidr27
; /* Internal IRQ Destination 27 */
968 u32 iivpr28
; /* Internal IRQ Vector/Priority 28 */
970 u32 iidr28
; /* Internal IRQ Destination 28 */
972 u32 iivpr29
; /* Internal IRQ Vector/Priority 29 */
974 u32 iidr29
; /* Internal IRQ Destination 29 */
976 u32 iivpr30
; /* Internal IRQ Vector/Priority 30 */
978 u32 iidr30
; /* Internal IRQ Destination 30 */
980 u32 iivpr31
; /* Internal IRQ Vector/Priority 31 */
982 u32 iidr31
; /* Internal IRQ Destination 31 */
984 u32 mivpr0
; /* Messaging IRQ Vector/Priority 0 */
986 u32 midr0
; /* Messaging IRQ Destination 0 */
988 u32 mivpr1
; /* Messaging IRQ Vector/Priority 1 */
990 u32 midr1
; /* Messaging IRQ Destination 1 */
992 u32 mivpr2
; /* Messaging IRQ Vector/Priority 2 */
994 u32 midr2
; /* Messaging IRQ Destination 2 */
996 u32 mivpr3
; /* Messaging IRQ Vector/Priority 3 */
998 u32 midr3
; /* Messaging IRQ Destination 3 */
1000 u32 ipi0dr0
; /* Processor 0 Interprocessor IRQ Dispatch 0 */
1002 u32 ipi0dr1
; /* Processor 0 Interprocessor IRQ Dispatch 1 */
1004 u32 ipi0dr2
; /* Processor 0 Interprocessor IRQ Dispatch 2 */
1006 u32 ipi0dr3
; /* Processor 0 Interprocessor IRQ Dispatch 3 */
1008 u32 ctpr0
; /* Current Task Priority for Processor 0 */
1010 u32 whoami0
; /* Who Am I for Processor 0 */
1012 u32 iack0
; /* IRQ Acknowledge for Processor 0 */
1014 u32 eoi0
; /* End Of IRQ for Processor 0 */
1020 typedef struct ccsr_cpm
{
1028 typedef struct ccsr_cpm_siu
{
1040 /* IRQ Controller */
1041 typedef struct ccsr_cpm_intctl
{
1056 } ccsr_cpm_intctl_t
;
1058 /* input/output port */
1059 typedef struct ccsr_cpm_iop
{
1087 typedef struct ccsr_cpm_timer
{
1116 typedef struct ccsr_cpm_sdma
{
1124 typedef struct ccsr_cpm_fcc1
{
1141 typedef struct ccsr_cpm_fcc2
{
1158 typedef struct ccsr_cpm_fcc3
{
1175 typedef struct ccsr_cpm_fcc1_ext
{
1183 } ccsr_cpm_fcc1_ext_t
;
1186 typedef struct ccsr_cpm_fcc2_ext
{
1193 } ccsr_cpm_fcc2_ext_t
;
1196 typedef struct ccsr_cpm_fcc3_ext
{
1199 } ccsr_cpm_fcc3_ext_t
;
1202 typedef struct ccsr_cpm_tmp1
{
1207 typedef struct ccsr_cpm_brg2
{
1216 typedef struct ccsr_cpm_i2c
{
1232 typedef struct ccsr_cpm_cp
{
1246 typedef struct ccsr_cpm_brg1
{
1254 typedef struct ccsr_cpm_scc
{
1269 typedef struct ccsr_cpm_tmp2
{
1274 typedef struct ccsr_cpm_spi
{
1286 typedef struct ccsr_cpm_mux
{
1299 typedef struct ccsr_cpm_tmp3
{
1303 typedef struct ccsr_cpm_iram
{
1308 typedef struct ccsr_cpm
{
1309 /* Some references are into the unique & known dpram spaces,
1310 * others are from the generic base.
1312 #define im_dprambase im_dpram1
1313 u8 im_dpram1
[16*1024];
1315 u8 im_dpram2
[16*1024];
1317 ccsr_cpm_siu_t im_cpm_siu
; /* SIU Configuration */
1318 ccsr_cpm_intctl_t im_cpm_intctl
; /* IRQ Controller */
1319 ccsr_cpm_iop_t im_cpm_iop
; /* IO Port control/status */
1320 ccsr_cpm_timer_t im_cpm_timer
; /* CPM timers */
1321 ccsr_cpm_sdma_t im_cpm_sdma
; /* SDMA control/status */
1322 ccsr_cpm_fcc1_t im_cpm_fcc1
;
1323 ccsr_cpm_fcc2_t im_cpm_fcc2
;
1324 ccsr_cpm_fcc3_t im_cpm_fcc3
;
1325 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext
;
1326 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext
;
1327 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext
;
1328 ccsr_cpm_tmp1_t im_cpm_tmp1
;
1329 ccsr_cpm_brg2_t im_cpm_brg2
;
1330 ccsr_cpm_i2c_t im_cpm_i2c
;
1331 ccsr_cpm_cp_t im_cpm_cp
;
1332 ccsr_cpm_brg1_t im_cpm_brg1
;
1333 ccsr_cpm_scc_t im_cpm_scc
[4];
1334 ccsr_cpm_tmp2_t im_cpm_tmp2
;
1335 ccsr_cpm_spi_t im_cpm_spi
;
1336 ccsr_cpm_mux_t im_cpm_mux
;
1337 ccsr_cpm_tmp3_t im_cpm_tmp3
;
1338 ccsr_cpm_iram_t im_cpm_iram
;
1342 #ifdef CONFIG_SYS_SRIO
1343 /* Architectural regsiters */
1345 u32 didcar
; /* Device Identity CAR */
1346 u32 dicar
; /* Device Information CAR */
1347 u32 aidcar
; /* Assembly Identity CAR */
1348 u32 aicar
; /* Assembly Information CAR */
1349 u32 pefcar
; /* Processing Element Features CAR */
1351 u32 socar
; /* Source Operations CAR */
1352 u32 docar
; /* Destination Operations CAR */
1354 u32 mcsr
; /* Mailbox CSR */
1355 u32 pwdcsr
; /* Port-Write and Doorbell CSR */
1357 u32 pellccsr
; /* Processing Element Logic Layer CCSR */
1359 u32 lcsbacsr
; /* Local Configuration Space BACSR */
1360 u32 bdidcsr
; /* Base Device ID CSR */
1362 u32 hbdidlcsr
; /* Host Base Device ID Lock CSR */
1363 u32 ctcsr
; /* Component Tag CSR */
1366 /* Extended Features Space: 1x/4x LP-Serial Port registers */
1367 struct rio_lp_serial_port
{
1368 u32 plmreqcsr
; /* Port Link Maintenance Request CSR */
1369 u32 plmrespcsr
; /* Port Link Maintenance Response CS */
1370 u32 plascsr
; /* Port Local Ackid Status CSR */
1372 u32 pescsr
; /* Port Error and Status CSR */
1373 u32 pccsr
; /* Port Control CSR */
1376 /* Extended Features Space: 1x/4x LP-Serial registers */
1377 struct rio_lp_serial
{
1378 u32 pmbh0csr
; /* Port Maintenance Block Header 0 CSR */
1380 u32 pltoccsr
; /* Port Link Time-out CCSR */
1381 u32 prtoccsr
; /* Port Response Time-out CCSR */
1383 u32 pgccsr
; /* Port General CSR */
1384 struct rio_lp_serial_port port
[CONFIG_SYS_FSL_SRIO_MAX_PORTS
];
1387 /* Logical error reporting registers */
1388 struct rio_logical_err
{
1389 u32 erbh
; /* Error Reporting Block Header Register */
1391 u32 ltledcsr
; /* Logical/Transport layer error DCSR */
1392 u32 ltleecsr
; /* Logical/Transport layer error ECSR */
1394 u32 ltlaccsr
; /* Logical/Transport layer ACCSR */
1395 u32 ltldidccsr
; /* Logical/Transport layer DID CCSR */
1396 u32 ltlcccsr
; /* Logical/Transport layer control CCSR */
1399 /* Physical error reporting port registers */
1400 struct rio_phys_err_port
{
1401 u32 edcsr
; /* Port error detect CSR */
1402 u32 erecsr
; /* Port error rate enable CSR */
1403 u32 ecacsr
; /* Port error capture attributes CSR */
1404 u32 pcseccsr0
; /* Port packet/control symbol ECCSR 0 */
1405 u32 peccsr
[3]; /* Port error capture CSR */
1407 u32 ercsr
; /* Port error rate CSR */
1408 u32 ertcsr
; /* Port error rate threshold CSR */
1412 /* Physical error reporting registers */
1413 struct rio_phys_err
{
1414 struct rio_phys_err_port port
[CONFIG_SYS_FSL_SRIO_MAX_PORTS
];
1417 /* Implementation Space: General Port-Common */
1418 struct rio_impl_common
{
1420 u32 llcr
; /* Logical Layer Configuration Register */
1422 u32 epwisr
; /* Error / Port-Write Interrupt SR */
1424 u32 lretcr
; /* Logical Retry Error Threshold CR */
1426 u32 pretcr
; /* Physical Retry Erorr Threshold CR */
1430 /* Implementation Space: Port Specific */
1431 struct rio_impl_port_spec
{
1432 u32 adidcsr
; /* Port Alt. Device ID CSR */
1434 u32 ptaacr
; /* Port Pass-Through/Accept-All CR */
1437 u32 iecsr
; /* Port Implementation Error CSR */
1439 u32 pcr
; /* Port Phsyical Configuration Register */
1441 u32 slcsr
; /* Port Serial Link CSR */
1443 u32 sleicr
; /* Port Serial Link Error Injection */
1444 u32 a0txcr
; /* Port Arbitration 0 Tx CR */
1445 u32 a1txcr
; /* Port Arbitration 1 Tx CR */
1446 u32 a2txcr
; /* Port Arbitration 2 Tx CR */
1447 u32 mreqtxbacr
[3]; /* Port Request Tx Buffer ACR */
1448 u32 mrspfctxbacr
; /* Port Response/Flow Control Tx Buffer ACR */
1451 /* Implementation Space: register */
1452 struct rio_implement
{
1453 struct rio_impl_common com
;
1454 struct rio_impl_port_spec port
[CONFIG_SYS_FSL_SRIO_MAX_PORTS
];
1457 /* Revision Control Register */
1458 struct rio_rev_ctrl
{
1459 u32 ipbrr
[2]; /* IP Block Revision Register */
1462 struct rio_atmu_row
{
1463 u32 rowtar
; /* RapidIO Outbound Window TAR */
1464 u32 rowtear
; /* RapidIO Outbound Window TEAR */
1467 u32 rowar
; /* RapidIO Outbound Attributes Register */
1468 u32 rowsr
[3]; /* Port RapidIO outbound window segment register */
1471 struct rio_atmu_riw
{
1472 u32 riwtar
; /* RapidIO Inbound Window Translation AR */
1474 u32 riwbar
; /* RapidIO Inbound Window Base AR */
1476 u32 riwar
; /* RapidIO Inbound Attributes Register */
1480 /* ATMU window registers */
1481 struct rio_atmu_win
{
1482 struct rio_atmu_row outbw
[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
];
1484 struct rio_atmu_riw inbw
[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM
];
1488 struct rio_atmu_win port
[CONFIG_SYS_FSL_SRIO_MAX_PORTS
];
1491 #ifdef CONFIG_SYS_FSL_RMU
1493 u32 omr
; /* Outbound Mode Register */
1494 u32 osr
; /* Outbound Status Register */
1495 u32 eodqdpar
; /* Extended Outbound DQ DPAR */
1496 u32 odqdpar
; /* Outbound Descriptor Queue DPAR */
1497 u32 eosar
; /* Extended Outbound Unit Source AR */
1498 u32 osar
; /* Outbound Unit Source AR */
1499 u32 odpr
; /* Outbound Destination Port Register */
1500 u32 odatr
; /* Outbound Destination Attributes Register */
1501 u32 odcr
; /* Outbound Doubleword Count Register */
1502 u32 eodqepar
; /* Extended Outbound DQ EPAR */
1503 u32 odqepar
; /* Outbound Descriptor Queue EPAR */
1504 u32 oretr
; /* Outbound Retry Error Threshold Register */
1505 u32 omgr
; /* Outbound Multicast Group Register */
1506 u32 omlr
; /* Outbound Multicast List Register */
1508 u32 imr
; /* Outbound Mode Register */
1509 u32 isr
; /* Inbound Status Register */
1510 u32 eidqdpar
; /* Extended Inbound Descriptor Queue DPAR */
1511 u32 idqdpar
; /* Inbound Descriptor Queue DPAR */
1512 u32 eifqepar
; /* Extended Inbound Frame Queue EPAR */
1513 u32 ifqepar
; /* Inbound Frame Queue EPAR */
1514 u32 imirir
; /* Inbound Maximum Interrutp RIR */
1516 u32 eihqepar
; /* Extended inbound message header queue EPAR */
1517 u32 ihqepar
; /* Inbound message header queue EPAR */
1522 u32 odmr
; /* Outbound Doorbell Mode Register */
1523 u32 odsr
; /* Outbound Doorbell Status Register */
1525 u32 oddpr
; /* Outbound Doorbell Destination Port */
1526 u32 oddatr
; /* Outbound Doorbell Destination AR */
1528 u32 oddretr
; /* Outbound Doorbell Retry Threshold CR */
1530 u32 idmr
; /* Inbound Doorbell Mode Register */
1531 u32 idsr
; /* Inbound Doorbell Status Register */
1532 u32 iedqdpar
; /* Extended Inbound Doorbell Queue DPAR */
1533 u32 iqdpar
; /* Inbound Doorbell Queue DPAR */
1534 u32 iedqepar
; /* Extended Inbound Doorbell Queue EPAR */
1535 u32 idqepar
; /* Inbound Doorbell Queue EPAR */
1536 u32 idmirir
; /* Inbound Doorbell Max Interrupt RIR */
1540 u32 pwmr
; /* Port-Write Mode Register */
1541 u32 pwsr
; /* Port-Write Status Register */
1542 u32 epwqbar
; /* Extended Port-Write Queue BAR */
1543 u32 pwqbar
; /* Port-Write Queue Base Address Register */
1547 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1559 /* RapidIO Registers */
1561 struct rio_arch arch
;
1563 struct rio_lp_serial lp_serial
;
1565 struct rio_logical_err logical_err
;
1567 struct rio_phys_err phys_err
;
1569 struct rio_implement impl
;
1571 struct rio_rev_ctrl rev
;
1572 struct rio_atmu atmu
;
1573 #ifdef CONFIG_SYS_FSL_RMU
1575 struct rio_msg msg
[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM
];
1577 struct rio_dbell dbell
;
1581 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1583 struct rio_liodn liodn
[CONFIG_SYS_FSL_SRIO_MAX_PORTS
];
1588 /* Quick Engine Block Pin Muxing Registers */
1589 typedef struct par_io
{
1599 #ifdef CONFIG_SYS_FSL_CPC
1601 * Define a single offset that is the start of all the CPC register
1602 * blocks - if there is more than one CPC, we expect these to be
1603 * contiguous 4k regions
1606 typedef struct cpc_corenet
{
1607 u32 cpccsr0
; /* Config/status reg */
1609 u32 cpccfg0
; /* Configuration register */
1611 u32 cpcewcr0
; /* External Write reg 0 */
1612 u32 cpcewabr0
; /* External write base reg 0 */
1614 u32 cpcewcr1
; /* External Write reg 1 */
1615 u32 cpcewabr1
; /* External write base reg 1 */
1617 u32 cpcsrcr1
; /* SRAM control reg 1 */
1618 u32 cpcsrcr0
; /* SRAM control reg 0 */
1621 u32 id
; /* partition ID */
1623 u32 alloc
; /* partition allocation */
1624 u32 way
; /* partition way */
1625 } partition_regs
[16];
1627 u32 cpcerrinjhi
; /* Error injection high */
1628 u32 cpcerrinjlo
; /* Error injection lo */
1629 u32 cpcerrinjctl
; /* Error injection control */
1631 u32 cpccaptdatahi
; /* capture data high */
1632 u32 cpccaptdatalo
; /* capture data low */
1633 u32 cpcaptecc
; /* capture ECC */
1635 u32 cpcerrdet
; /* error detect */
1636 u32 cpcerrdis
; /* error disable */
1637 u32 cpcerrinten
; /* errir interrupt enable */
1638 u32 cpcerrattr
; /* error attribute */
1639 u32 cpcerreaddr
; /* error extended address */
1640 u32 cpcerraddr
; /* error address */
1641 u32 cpcerrctl
; /* error control */
1642 u32 res9
[41]; /* pad out to 4k */
1643 u32 cpchdbcr0
; /* hardware debug control register 0 */
1644 u32 res10
[63]; /* pad out to 4k */
1647 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1648 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1649 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1650 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1651 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1652 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1653 #define CPC_CFG0_SZ_MASK 0x00003fff
1654 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1655 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1656 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1657 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1658 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1659 & CPC_SRCR1_SRBARU_MASK)
1660 #define CPC_SRCR0_SRBARL_MASK 0xffff8000
1661 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1662 #define CPC_SRCR0_INTLVEN 0x00000100
1663 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1664 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1665 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1666 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1667 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1668 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1669 #define CPC_SRCR0_SRAMEN 0x00000001
1670 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1671 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1672 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1673 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1674 #endif /* CONFIG_SYS_FSL_CPC */
1676 /* Global Utilities Block */
1677 #ifdef CONFIG_FSL_CORENET
1678 typedef struct ccsr_gur
{
1679 u32 porsr1
; /* POR status 1 */
1680 u32 porsr2
; /* POR status 2 */
1681 u8 res_008
[0x20-0x8];
1682 u32 gpporcr1
; /* General-purpose POR configuration */
1683 u32 gpporcr2
; /* General-purpose POR configuration 2 */
1684 u32 dcfg_fusesr
; /* Fuse status register */
1685 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1686 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1687 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1688 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1689 u8 res_02c
[0x70-0x2c];
1690 u32 devdisr
; /* Device disable control */
1691 u32 devdisr2
; /* Device disable control 2 */
1692 u32 devdisr3
; /* Device disable control 3 */
1693 u32 devdisr4
; /* Device disable control 4 */
1694 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1695 u32 devdisr5
; /* Device disable control 5 */
1696 #define FSL_CORENET_DEVDISR_PBL 0x80000000
1697 #define FSL_CORENET_DEVDISR_PMAN 0x40000000
1698 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1699 #define FSL_CORENET_DEVDISR_DMA1 0x00800000
1700 #define FSL_CORENET_DEVDISR_DMA2 0x00400000
1701 #define FSL_CORENET_DEVDISR_USB1 0x00080000
1702 #define FSL_CORENET_DEVDISR_USB2 0x00040000
1703 #define FSL_CORENET_DEVDISR_SATA1 0x00008000
1704 #define FSL_CORENET_DEVDISR_SATA2 0x00004000
1705 #define FSL_CORENET_DEVDISR_PME 0x00000800
1706 #define FSL_CORENET_DEVDISR_SEC 0x00000200
1707 #define FSL_CORENET_DEVDISR_RMU 0x00000080
1708 #define FSL_CORENET_DEVDISR_DCE 0x00000040
1709 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1710 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1711 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1712 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1713 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1714 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1715 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1716 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1717 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1718 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1719 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1720 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1721 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1722 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1723 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1724 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1725 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1726 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1727 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1728 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1729 #define FSL_CORENET_DEVDISR2_FM1 0x00000080
1730 #define FSL_CORENET_DEVDISR2_FM2 0x00000040
1731 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1732 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1733 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1734 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1735 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1736 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1737 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1738 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1739 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1740 #define FSL_CORENET_DEVDISR3_LA1 0x00008000
1741 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1742 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1743 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1744 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1745 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1746 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1747 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1748 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1749 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1750 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1751 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1752 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1753 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1754 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1755 #define FSL_CORENET_DEVDISR5_IFC 0x00800000
1756 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1757 #define FSL_CORENET_DEVDISR5_DBG 0x00200000
1758 #define FSL_CORENET_DEVDISR5_NAL 0x00100000
1759 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1760 #define FSL_CORENET_NUM_DEVDISR 5
1762 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1763 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1764 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1765 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1766 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1767 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1768 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1769 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1770 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1771 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1772 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1773 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1774 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1775 #define FSL_CORENET_DEVDISR_SATA1 0x00004000
1776 #define FSL_CORENET_DEVDISR_SATA2 0x00002000
1777 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1778 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1779 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1780 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1781 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1782 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1783 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1784 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1785 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1786 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1787 #define FSL_CORENET_DEVDISR2_PME 0x80000000
1788 #define FSL_CORENET_DEVDISR2_SEC 0x40000000
1789 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1790 #define FSL_CORENET_DEVDISR2_FM1 0x02000000
1791 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1792 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1793 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1794 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1795 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1796 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1797 #define FSL_CORENET_DEVDISR2_FM2 0x00020000
1798 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1799 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1800 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1801 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1802 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1803 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1804 #define FSL_CORENET_NUM_DEVDISR 2
1805 u32 powmgtcsr
; /* Power management status & control */
1808 u32 coredisru
; /* uppper portion for support of 64 cores */
1809 u32 coredisrl
; /* lower portion for support of 64 cores */
1811 u32 pvr
; /* Processor version */
1812 u32 svr
; /* System version */
1814 u32 rstcr
; /* Reset control */
1815 u32 rstrqpblsr
; /* Reset request preboot loader status */
1817 u32 rstrqmr1
; /* Reset request mask */
1819 u32 rstrqsr1
; /* Reset request status */
1822 u32 rstrqwdtmrl
; /* Reset request WDT mask */
1824 u32 rstrqwdtsrl
; /* Reset request WDT status */
1826 u32 brrl
; /* Boot release */
1828 u32 rcwsr
[16]; /* Reset control word status */
1830 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1831 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1832 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1833 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
1834 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1835 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1836 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1837 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1838 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1839 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1840 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1841 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
1842 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1843 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
1844 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1845 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1846 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1847 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1848 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1849 #elif defined(CONFIG_PPC_T1040)
1850 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1851 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1852 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1853 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1855 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1856 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1857 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1858 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1859 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1860 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1861 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1862 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1864 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1865 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1866 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1867 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1868 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1869 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1870 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1871 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1872 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1873 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1874 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
1875 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1877 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1878 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1879 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1880 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1881 #ifdef CONFIG_PPC_P4080
1882 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1883 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1884 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1885 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1886 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1887 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1889 #if defined(CONFIG_PPC_P2041) \
1890 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
1891 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1892 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1893 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1894 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1895 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1896 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1897 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1899 #if defined(CONFIG_PPC_P5040)
1900 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1901 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1902 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1903 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1904 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1905 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1906 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1908 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
1909 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1910 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1911 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1912 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1913 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1914 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1915 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1918 u32 scratchrw
[4]; /* Scratch Read/Write */
1920 u32 scratchw1r
[4]; /* Scratch Read (Write once) */
1922 u32 scrtsr
[8]; /* Core reset status */
1924 u32 pex1liodnr
; /* PCI Express 1 LIODN */
1925 u32 pex2liodnr
; /* PCI Express 2 LIODN */
1926 u32 pex3liodnr
; /* PCI Express 3 LIODN */
1927 u32 pex4liodnr
; /* PCI Express 4 LIODN */
1928 u32 rio1liodnr
; /* RIO 1 LIODN */
1929 u32 rio2liodnr
; /* RIO 2 LIODN */
1930 u32 rio3liodnr
; /* RIO 3 LIODN */
1931 u32 rio4liodnr
; /* RIO 4 LIODN */
1932 u32 usb1liodnr
; /* USB 1 LIODN */
1933 u32 usb2liodnr
; /* USB 2 LIODN */
1934 u32 usb3liodnr
; /* USB 3 LIODN */
1935 u32 usb4liodnr
; /* USB 4 LIODN */
1936 u32 sdmmc1liodnr
; /* SD/MMC 1 LIODN */
1937 u32 sdmmc2liodnr
; /* SD/MMC 2 LIODN */
1938 u32 sdmmc3liodnr
; /* SD/MMC 3 LIODN */
1939 u32 sdmmc4liodnr
; /* SD/MMC 4 LIODN */
1940 u32 rio1maintliodnr
;/* RIO 1 Maintenance LIODN */
1941 u32 rio2maintliodnr
;/* RIO 2 Maintenance LIODN */
1942 u32 rio3maintliodnr
;/* RIO 3 Maintenance LIODN */
1943 u32 rio4maintliodnr
;/* RIO 4 Maintenance LIODN */
1944 u32 sata1liodnr
; /* SATA 1 LIODN */
1945 u32 sata2liodnr
; /* SATA 2 LIODN */
1946 u32 sata3liodnr
; /* SATA 3 LIODN */
1947 u32 sata4liodnr
; /* SATA 4 LIODN */
1949 u32 dma1liodnr
; /* DMA 1 LIODN */
1950 u32 dma2liodnr
; /* DMA 2 LIODN */
1951 u32 dma3liodnr
; /* DMA 3 LIODN */
1952 u32 dma4liodnr
; /* DMA 4 LIODN */
1955 u32 pblsr
; /* Preboot loader status */
1956 u32 pamubypenr
; /* PAMU bypass enable */
1957 u32 dmacr1
; /* DMA control */
1959 u32 gensr1
; /* General status */
1961 u32 gencr1
; /* General control */
1964 u32 cgensrl
; /* Core general status */
1967 u32 cgencrl
; /* Core general control */
1969 u32 sriopstecr
; /* SRIO prescaler timer enable control */
1970 u32 dcsrcr
; /* DCSR Control register */
1972 u32 tp_ityp
[64]; /* Topology Initiator Type Register */
1976 } tp_cluster
[16]; /* Core Cluster n Topology Register */
1978 u32 pmuxcr
; /* Pin multiplexing control */
1980 u32 iovselsr
; /* I/O voltage selection status */
1982 u32 ddrclkdr
; /* DDR clock disable */
1984 u32 elbcclkdr
; /* eLBC clock disable */
1986 u32 sdhcpcr
; /* eSDHC polarity configuration */
1990 #define TP_ITYP_AV 0x00000001 /* Initiator available */
1991 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1992 #define TP_ITYP_TYPE_OTHER 0x0
1993 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1994 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1995 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
1996 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
1997 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
1999 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
2000 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
2001 #define TP_INIT_PER_CLUSTER 4
2003 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
2004 #define FSL_CORENET_DCSR_SZ_4M 0x0
2005 #define FSL_CORENET_DCSR_SZ_1G 0x3
2008 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
2009 * everything after has RMan thus msg unit LIODN is used for maintenance
2011 #define rmuliodnr rio1maintliodnr
2013 typedef struct ccsr_clk
{
2015 u32 clkcncsr
; /* core cluster n clock control status */
2017 u32 clkcgnhwacsr
;/* clock generator n hardware accelerator */
2020 u8 res_100
[0x700]; /* 0x100 */
2021 u32 pllc1gsr
; /* 0x800 Cluster PLL 1 General Status */
2023 u32 pllc2gsr
; /* 0x820 Cluster PLL 2 General Status */
2025 u32 pllc3gsr
; /* 0x840 Cluster PLL 3 General Status */
2027 u32 pllc4gsr
; /* 0x860 Cluster PLL 4 General Status */
2029 u32 pllc5gsr
; /* 0x880 Cluster PLL 5 General Status */
2031 u32 pllc6gsr
; /* 0x8a0 Cluster PLL 6 General Status */
2033 u32 pllpgsr
; /* 0xc00 Platform PLL General Status */
2035 u32 plldgsr
; /* 0xc20 DDR PLL General Status */
2039 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2040 typedef struct ccsr_rcpm
{
2042 u32 tph10sr0
; /* Thread PH10 Status Register */
2044 u32 tph10setr0
; /* Thread PH10 Set Control Register */
2046 u32 tph10clrr0
; /* Thread PH10 Clear Control Register */
2048 u32 tph10psr0
; /* Thread PH10 Previous Status Register */
2050 u32 twaitsr0
; /* Thread Wait Status Register */
2052 u32 pcph15sr
; /* Physical Core PH15 Status Register */
2053 u32 pcph15setr
; /* Physical Core PH15 Set Control Register */
2054 u32 pcph15clrr
; /* Physical Core PH15 Clear Control Register */
2055 u32 pcph15psr
; /* Physical Core PH15 Prev Status Register */
2057 u32 pcph20sr
; /* Physical Core PH20 Status Register */
2058 u32 pcph20setr
; /* Physical Core PH20 Set Control Register */
2059 u32 pcph20clrr
; /* Physical Core PH20 Clear Control Register */
2060 u32 pcph20psr
; /* Physical Core PH20 Prev Status Register */
2061 u32 pcpw20sr
; /* Physical Core PW20 Status Register */
2063 u32 pcph30sr
; /* Physical Core PH30 Status Register */
2064 u32 pcph30setr
; /* Physical Core PH30 Set Control Register */
2065 u32 pcph30clrr
; /* Physical Core PH30 Clear Control Register */
2066 u32 pcph30psr
; /* Physical Core PH30 Prev Status Register */
2068 u32 ippwrgatecr
; /* IP Power Gating Control Register */
2070 u32 powmgtcsr
; /* Power Management Control & Status Reg */
2072 u32 ippdexpcr
[4]; /* IP Powerdown Exception Control Reg */
2074 u32 tpmimr0
; /* Thread PM Interrupt Mask Reg */
2076 u32 tpmcimr0
; /* Thread PM Crit Interrupt Mask Reg */
2078 u32 tpmmcmr0
; /* Thread PM Machine Check Interrupt Mask Reg */
2080 u32 tpmnmimr0
; /* Thread PM NMI Mask Reg */
2082 u32 tmcpmaskcr0
; /* Thread Machine Check Mask Control Reg */
2083 u32 pctbenr
; /* Physical Core Time Base Enable Reg */
2084 u32 pctbclkselr
; /* Physical Core Time Base Clock Select */
2085 u32 tbclkdivr
; /* Time Base Clock Divider Register */
2087 u32 ttbhltcr
[4]; /* Thread Time Base Halt Control Register */
2088 u32 clpcl10sr
; /* Cluster PCL10 Status Register */
2089 u32 clpcl10setr
; /* Cluster PCL30 Set Control Register */
2090 u32 clpcl10clrr
; /* Cluster PCL30 Clear Control Register */
2091 u32 clpcl10psr
; /* Cluster PCL30 Prev Status Register */
2092 u32 cddslpsetr
; /* Core Domain Deep Sleep Set Register */
2093 u32 cddslpclrr
; /* Core Domain Deep Sleep Clear Register */
2094 u32 cdpwroksetr
; /* Core Domain Power OK Set Register */
2095 u32 cdpwrokclrr
; /* Core Domain Power OK Clear Register */
2096 u32 cdpwrensr
; /* Core Domain Power Enable Status Register */
2097 u32 cddslsr
; /* Core Domain Deep Sleep Status Register */
2099 u32 dslpcntcr
[8]; /* Deep Sleep Counter Cfg Register */
2103 #define ctbenrl pctbenr
2106 typedef struct ccsr_rcpm
{
2108 u32 cdozsrl
; /* Core Doze Status */
2110 u32 cdozcrl
; /* Core Doze Control */
2112 u32 cnapsrl
; /* Core Nap Status */
2114 u32 cnapcrl
; /* Core Nap Control */
2116 u32 cdozpsrl
; /* Core Doze Previous Status */
2118 u32 cdozpcrl
; /* Core Doze Previous Control */
2120 u32 cwaitsrl
; /* Core Wait Status */
2122 u32 powmgtcsr
; /* Power Mangement Control & Status */
2124 u32 ippdexpcr0
; /* IP Powerdown Exception Control 0 */
2127 u32 cpmimrl
; /* Core PM IRQ Masking */
2129 u32 cpmcimrl
; /* Core PM Critical IRQ Masking */
2131 u32 cpmmcimrl
; /* Core PM Machine Check IRQ Masking */
2133 u32 cpmnmimrl
; /* Core PM NMI Masking */
2135 u32 ctbenrl
; /* Core Time Base Enable */
2137 u32 ctbclkselrl
; /* Core Time Base Clock Select */
2139 u32 ctbhltcrl
; /* Core Time Base Halt Control */
2142 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2145 typedef struct ccsr_gur
{
2146 u32 porpllsr
; /* POR PLL ratio status */
2147 #ifdef CONFIG_MPC8536
2148 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2149 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2150 #elif defined(CONFIG_PPC_C29X)
2151 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2152 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2153 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2154 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
2156 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
2157 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2159 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2161 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2163 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2164 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
2165 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2166 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2167 u32 porbmsr
; /* POR boot mode status */
2168 #define MPC85xx_PORBMSR_HA 0x00070000
2169 #define MPC85xx_PORBMSR_HA_SHIFT 16
2170 #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
2171 #define PORBMSR_ROMLOC_SPI 0x6
2172 #define PORBMSR_ROMLOC_SDHC 0x7
2173 #define PORBMSR_ROMLOC_NAND_2K 0x9
2174 #define PORBMSR_ROMLOC_NOR 0xf
2175 u32 porimpscr
; /* POR I/O impedance status & control */
2176 u32 pordevsr
; /* POR I/O device status regsiter */
2177 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2178 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2179 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2180 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2182 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2183 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2185 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2186 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2187 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2188 #define MPC85xx_PORDEVSR_PCI1 0x00800000
2189 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2190 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2191 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
2192 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
2193 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2194 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2196 #if defined(CONFIG_P1010)
2197 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2198 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2199 #elif defined(CONFIG_BSC9132)
2200 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2201 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
2202 #elif defined(CONFIG_PPC_C29X)
2203 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2204 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2206 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2207 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
2208 #endif /* if defined(CONFIG_P1010) */
2210 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2211 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2212 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2213 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2214 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2215 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2216 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2217 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2218 u32 pordbgmsr
; /* POR debug mode status */
2219 u32 pordevsr2
; /* POR I/O device status 2 */
2220 #if defined(CONFIG_PPC_C29X)
2221 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2222 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2224 /* The 8544 RM says this is bit 26, but it's really bit 24 */
2225 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2227 u32 gpporcr
; /* General-purpose POR configuration */
2229 #if defined(CONFIG_MPC8536)
2230 u32 gencfgr
; /* General Configuration Register */
2231 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2233 u32 gpiocr
; /* GPIO control */
2236 #if defined(CONFIG_MPC8569)
2237 u32 plppar1
; /* Platform port pin assignment 1 */
2238 u32 plppar2
; /* Platform port pin assignment 2 */
2239 u32 plpdir1
; /* Platform port pin direction 1 */
2240 u32 plpdir2
; /* Platform port pin direction 2 */
2242 u32 gpoutdr
; /* General-purpose output data */
2245 u32 gpindr
; /* General-purpose input data */
2247 u32 pmuxcr
; /* Alt. function signal multiplex control */
2248 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2249 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2250 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2251 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2252 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2253 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2254 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2255 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2256 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2257 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2258 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2259 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2260 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2261 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2262 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2263 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2264 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2265 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2266 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2267 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2268 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2269 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2270 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2271 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2272 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2273 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2274 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2275 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2276 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2277 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2278 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2279 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2280 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2281 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2282 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2283 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2284 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2285 #define MPC85xx_PMUXCR_SPI_RES 0x00000030
2286 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2287 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2288 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2289 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2290 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2291 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2292 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2294 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2295 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2297 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
2298 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2299 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2300 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2301 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2302 #define MPC85xx_PMUXCR_QE0 0x00008000
2303 #define MPC85xx_PMUXCR_QE1 0x00004000
2304 #define MPC85xx_PMUXCR_QE2 0x00002000
2305 #define MPC85xx_PMUXCR_QE3 0x00001000
2306 #define MPC85xx_PMUXCR_QE4 0x00000800
2307 #define MPC85xx_PMUXCR_QE5 0x00000400
2308 #define MPC85xx_PMUXCR_QE6 0x00000200
2309 #define MPC85xx_PMUXCR_QE7 0x00000100
2310 #define MPC85xx_PMUXCR_QE8 0x00000080
2311 #define MPC85xx_PMUXCR_QE9 0x00000040
2312 #define MPC85xx_PMUXCR_QE10 0x00000020
2313 #define MPC85xx_PMUXCR_QE11 0x00000010
2314 #define MPC85xx_PMUXCR_QE12 0x00000008
2316 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2317 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2318 #define MPC85xx_PMUXCR_TDM 0x00014800
2319 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2320 #define MPC85xx_PMUXCR_SPI 0x00000000
2322 #if defined(CONFIG_BSC9131)
2323 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2324 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2325 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2326 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2327 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2328 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2329 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2330 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2331 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2332 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2333 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2334 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2335 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2336 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2337 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2338 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2339 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2340 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2341 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2342 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2343 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2344 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2345 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2346 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2347 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2348 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2349 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2350 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2351 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2352 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2353 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2354 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2355 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2356 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2357 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2358 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2359 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2360 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2361 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2362 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2363 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2364 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2366 #ifdef CONFIG_BSC9132
2367 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2368 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2370 #if defined(CONFIG_PPC_C29X)
2371 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2372 #define MPC85xx_PMUXCR_SPI 0x00000000
2373 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2375 u32 pmuxcr2
; /* Alt. function signal multiplex control 2 */
2376 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2377 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2378 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2379 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2380 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2381 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2382 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2383 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2384 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2385 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2386 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2387 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2388 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2389 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2390 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2391 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2392 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2393 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2394 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2395 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2396 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2397 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2398 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2399 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2401 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2402 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2403 #define MPC85xx_PMUXCR2_USB 0x00150000
2405 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
2406 #if defined(CONFIG_BSC9131)
2407 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2408 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2409 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2410 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2411 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2412 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2413 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2414 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2415 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2416 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2417 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2418 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2419 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2420 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2421 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2422 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2423 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2424 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2425 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2426 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2427 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2428 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2429 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2430 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2431 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2432 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2433 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2434 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2435 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2436 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2437 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2438 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2439 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2440 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2441 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2442 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2443 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2444 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2445 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2446 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2447 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2448 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2451 #if defined(CONFIG_BSC9131)
2452 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2453 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2454 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2455 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2456 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2457 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2458 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2459 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2460 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2461 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2462 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2463 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2464 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2465 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2467 #ifdef CONFIG_BSC9132
2468 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2469 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2470 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2471 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2477 u32 devdisr
; /* Device disable control */
2478 #define MPC85xx_DEVDISR_PCI1 0x80000000
2479 #define MPC85xx_DEVDISR_PCI2 0x40000000
2480 #define MPC85xx_DEVDISR_PCIE 0x20000000
2481 #define MPC85xx_DEVDISR_LBC 0x08000000
2482 #define MPC85xx_DEVDISR_PCIE2 0x04000000
2483 #define MPC85xx_DEVDISR_PCIE3 0x02000000
2484 #define MPC85xx_DEVDISR_SEC 0x01000000
2485 #define MPC85xx_DEVDISR_SRIO 0x00080000
2486 #define MPC85xx_DEVDISR_RMSG 0x00040000
2487 #define MPC85xx_DEVDISR_DDR 0x00010000
2488 #define MPC85xx_DEVDISR_CPU 0x00008000
2489 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2490 #define MPC85xx_DEVDISR_TB 0x00004000
2491 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2492 #define MPC85xx_DEVDISR_CPU1 0x00002000
2493 #define MPC85xx_DEVDISR_TB1 0x00001000
2494 #define MPC85xx_DEVDISR_DMA 0x00000400
2495 #define MPC85xx_DEVDISR_TSEC1 0x00000080
2496 #define MPC85xx_DEVDISR_TSEC2 0x00000040
2497 #define MPC85xx_DEVDISR_TSEC3 0x00000020
2498 #define MPC85xx_DEVDISR_TSEC4 0x00000010
2499 #define MPC85xx_DEVDISR_I2C 0x00000004
2500 #define MPC85xx_DEVDISR_DUART 0x00000002
2502 u32 powmgtcsr
; /* Power management status & control */
2504 u32 mcpsumr
; /* Machine check summary */
2506 u32 pvr
; /* Processor version */
2507 u32 svr
; /* System version */
2509 u32 rstcr
; /* Reset control */
2510 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
2512 par_io_t qe_par_io
[7];
2514 #elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
2518 par_io_t qe_par_io
[3];
2523 u32 clkdvdr
; /* Clock Divide register */
2525 u32 clkocr
; /* Clock out select */
2527 u32 ddrdllcr
; /* DDR DLL control */
2529 u32 lbcdllcr
; /* LBC DLL control */
2530 #if defined(CONFIG_BSC9131)
2533 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2538 u32 lbiuiplldcr0
; /* LBIU PLL Debug Reg 0 */
2539 u32 lbiuiplldcr1
; /* LBIU PLL Debug Reg 1 */
2540 u32 ddrioovcr
; /* DDR IO Override Control */
2541 u32 tsec12ioovcr
; /* eTSEC 1/2 IO override control */
2542 u32 tsec34ioovcr
; /* eTSEC 3/4 IO override control */
2544 u32 sdhcdcr
; /* SDHC debug control register */
2549 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2551 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2552 #define MAX_SERDES 4
2553 #define SRDS_MAX_LANES 8
2554 #define SRDS_MAX_BANK 2
2555 typedef struct serdes_corenet
{
2557 u32 rstctl
; /* Reset Control Register */
2558 #define SRDS_RSTCTL_RST 0x80000000
2559 #define SRDS_RSTCTL_RSTDONE 0x40000000
2560 #define SRDS_RSTCTL_RSTERR 0x20000000
2561 #define SRDS_RSTCTL_SWRST 0x10000000
2562 #define SRDS_RSTCTL_SDEN 0x00000020
2563 #define SRDS_RSTCTL_SDRST_B 0x00000040
2564 #define SRDS_RSTCTL_PLLRST_B 0x00000080
2565 u32 pllcr0
; /* PLL Control Register 0 */
2566 #define SRDS_PLLCR0_POFF 0x80000000
2567 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2568 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2569 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2570 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2571 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2572 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2573 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2574 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2575 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2576 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2577 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2578 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2579 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
2580 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
2581 u32 pllcr1
; /* PLL Control Register 1 */
2582 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2583 u32 res_0c
; /* 0x00c */
2586 u8 res_18
[0x20-0x18];
2588 u8 res_40
[0x90-0x40];
2589 u32 srdstcalcr
; /* 0x90 TX Calibration Control */
2590 u8 res_94
[0xa0-0x94];
2591 u32 srdsrcalcr
; /* 0xa0 RX Calibration Control */
2592 u8 res_a4
[0xb0-0xa4];
2593 u32 srdsgr0
; /* 0xb0 General Register 0 */
2594 u8 res_b4
[0xe0-0xb4];
2595 u32 srdspccr0
; /* 0xe0 Protocol Converter Config 0 */
2596 u32 srdspccr1
; /* 0xe4 Protocol Converter Config 1 */
2597 u32 srdspccr2
; /* 0xe8 Protocol Converter Config 2 */
2598 u32 srdspccr3
; /* 0xec Protocol Converter Config 3 */
2599 u32 srdspccr4
; /* 0xf0 Protocol Converter Config 4 */
2600 u8 res_f4
[0x100-0xf4];
2602 u32 lnpssr
; /* 0x100, 0x120, ..., 0x1e0 */
2603 u8 res_104
[0x120-0x104];
2605 u8 res_200
[0x800-0x200];
2607 u32 gcr0
; /* 0x800 General Control Register 0 */
2608 u32 gcr1
; /* 0x804 General Control Register 1 */
2609 u32 gcr2
; /* 0x808 General Control Register 2 */
2611 u32 recr0
; /* 0x810 Receive Equalization Control */
2613 u32 tecr0
; /* 0x818 Transmit Equalization Control */
2615 u32 ttlcr0
; /* 0x820 Transition Tracking Loop Ctrl 0 */
2616 u8 res_824
[0x840-0x824];
2617 } lane
[8]; /* Lane A, B, C, D, E, F, G, H */
2618 u8 res_a00
[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2621 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2623 #define SRDS_MAX_LANES 18
2624 #define SRDS_MAX_BANK 3
2625 typedef struct serdes_corenet
{
2627 u32 rstctl
; /* Reset Control Register */
2628 #define SRDS_RSTCTL_RST 0x80000000
2629 #define SRDS_RSTCTL_RSTDONE 0x40000000
2630 #define SRDS_RSTCTL_RSTERR 0x20000000
2631 #define SRDS_RSTCTL_SDPD 0x00000020
2632 u32 pllcr0
; /* PLL Control Register 0 */
2633 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2634 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2635 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2636 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2637 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2638 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2639 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2640 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2641 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2642 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2643 u32 pllcr1
; /* PLL Control Register 1 */
2644 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2648 u32 srdstcalcr
; /* TX Calibration Control */
2650 u32 srdsrcalcr
; /* RX Calibration Control */
2652 u32 srdsgr0
; /* General Register 0 */
2654 u32 srdspccr0
; /* Protocol Converter Config 0 */
2655 u32 srdspccr1
; /* Protocol Converter Config 1 */
2656 u32 srdspccr2
; /* Protocol Converter Config 2 */
2657 #define SRDS_PCCR2_RST_XGMII1 0x00800000
2658 #define SRDS_PCCR2_RST_XGMII2 0x00400000
2660 struct serdes_lane
{
2661 u32 gcr0
; /* General Control Register 0 */
2662 #define SRDS_GCR0_RRST 0x00400000
2663 #define SRDS_GCR0_1STLANE 0x00010000
2664 #define SRDS_GCR0_UOTHL 0x00100000
2665 u32 gcr1
; /* General Control Register 1 */
2666 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2667 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2668 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2669 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2670 #define SRDS_GCR1_OPAD_CTL 0x04000000
2672 u32 tecr0
; /* TX Equalization Control Reg 0 */
2673 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2674 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2676 u32 ttlcr0
; /* Transition Tracking Loop Ctrl 0 */
2677 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2678 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2679 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2680 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2681 #define SRDS_TTLCR0_PM_DIS 0x00004000
2682 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2687 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2690 FSL_SRDS_B1_LANE_A
= 0,
2691 FSL_SRDS_B1_LANE_B
= 1,
2692 FSL_SRDS_B1_LANE_C
= 2,
2693 FSL_SRDS_B1_LANE_D
= 3,
2694 FSL_SRDS_B1_LANE_E
= 4,
2695 FSL_SRDS_B1_LANE_F
= 5,
2696 FSL_SRDS_B1_LANE_G
= 6,
2697 FSL_SRDS_B1_LANE_H
= 7,
2698 FSL_SRDS_B1_LANE_I
= 8,
2699 FSL_SRDS_B1_LANE_J
= 9,
2700 FSL_SRDS_B2_LANE_A
= 16,
2701 FSL_SRDS_B2_LANE_B
= 17,
2702 FSL_SRDS_B2_LANE_C
= 18,
2703 FSL_SRDS_B2_LANE_D
= 19,
2704 FSL_SRDS_B3_LANE_A
= 20,
2705 FSL_SRDS_B3_LANE_B
= 21,
2706 FSL_SRDS_B3_LANE_C
= 22,
2707 FSL_SRDS_B3_LANE_D
= 23,
2710 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2711 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2712 typedef struct ccsr_sec
{
2714 u32 mcfgr
; /* Master CFG Register */
2717 u32 ms
; /* Job Ring LIODN Register, MS */
2718 u32 ls
; /* Job Ring LIODN Register, LS */
2722 u32 ms
; /* RTIC LIODN Register, MS */
2723 u32 ls
; /* RTIC LIODN Register, LS */
2726 u32 decorr
; /* DECO Request Register */
2728 u32 ms
; /* DECO LIODN Register, MS */
2729 u32 ls
; /* DECO LIODN Register, LS */
2732 u32 dar
; /* DECO Avail Register */
2733 u32 drr
; /* DECO Reset Register */
2735 u32 crnr_ms
; /* CHA Revision Number Register, MS */
2736 u32 crnr_ls
; /* CHA Revision Number Register, LS */
2737 u32 ctpr_ms
; /* Compile Time Parameters Register, MS */
2738 u32 ctpr_ls
; /* Compile Time Parameters Register, LS */
2740 u32 far_ms
; /* Fault Address Register, MS */
2741 u32 far_ls
; /* Fault Address Register, LS */
2742 u32 falr
; /* Fault Address LIODN Register */
2743 u32 fadr
; /* Fault Address Detail Register */
2745 u32 csta
; /* CAAM Status Register */
2747 u32 rvid
; /* Run Time Integrity Checking Version ID Reg.*/
2748 u32 ccbvid
; /* CHA Cluster Block Version ID Register */
2749 u32 chavid_ms
; /* CHA Version ID Register, MS */
2750 u32 chavid_ls
; /* CHA Version ID Register, LS */
2751 u32 chanum_ms
; /* CHA Number Register, MS */
2752 u32 chanum_ls
; /* CHA Number Register, LS */
2753 u32 secvid_ms
; /* SEC Version ID Register, MS */
2754 u32 secvid_ls
; /* SEC Version ID Register, LS */
2756 u32 qilcr_ms
; /* Queue Interface LIODN CFG Register, MS */
2757 u32 qilcr_ls
; /* Queue Interface LIODN CFG Register, LS */
2761 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
2762 #define SEC_CTPR_MS_QI 0x02000000
2763 #define SEC_RVID_MA 0x0f000000
2764 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2765 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
2766 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2767 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
2768 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
2769 #define SEC_SECVID_MS_IPID_SHIFT 16
2770 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
2771 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
2772 #define SEC_CCBVID_ERA_MASK 0xff000000
2773 #define SEC_CCBVID_ERA_SHIFT 24
2776 typedef struct ccsr_qman
{
2777 #ifdef CONFIG_SYS_FSL_QMAN_V3
2781 u32 qcsp_lio_cfg
; /* 0x0 - SW Portal n LIO cfg */
2782 u32 qcsp_io_cfg
; /* 0x4 - SW Portal n IO cfg */
2784 u32 qcsp_dd_cfg
; /* 0xc - SW Portal n Dynamic Debug cfg */
2787 /* Not actually reserved, but irrelevant to u-boot */
2788 u8 res
[0xbf8 - 0x200];
2791 u32 fqd_bare
; /* FQD Extended Base Addr Register */
2792 u32 fqd_bar
; /* FQD Base Addr Register */
2794 u32 fqd_ar
; /* FQD Attributes Register */
2796 u32 pfdr_bare
; /* PFDR Extended Base Addr Register */
2797 u32 pfdr_bar
; /* PFDR Base Addr Register */
2799 u32 pfdr_ar
; /* PFDR Attributes Register */
2801 u32 qcsp_bare
; /* QCSP Extended Base Addr Register */
2802 u32 qcsp_bar
; /* QCSP Base Addr Register */
2804 u32 ci_sched_cfg
; /* Initiator Scheduling Configuration */
2805 u32 srcidr
; /* Source ID Register */
2806 u32 liodnr
; /* LIODN Register */
2808 u32 ci_rlm_cfg
; /* Initiator Read Latency Monitor Cfg */
2809 u32 ci_rlm_avg
; /* Initiator Read Latency Monitor Avg */
2811 #ifdef CONFIG_SYS_FSL_QMAN_V3
2813 u32 qcsp_lio_cfg
; /* 0x0 - SW Portal n LIO cfg */
2814 u32 qcsp_io_cfg
; /* 0x4 - SW Portal n IO cfg */
2816 u32 qcsp_dd_cfg
; /* 0xc - SW Portal n Dynamic Debug cfg*/
2821 typedef struct ccsr_bman
{
2822 /* Not actually reserved, but irrelevant to u-boot */
2826 u32 fbpr_bare
; /* FBPR Extended Base Addr Register */
2827 u32 fbpr_bar
; /* FBPR Base Addr Register */
2829 u32 fbpr_ar
; /* FBPR Attributes Register */
2831 u32 srcidr
; /* Source ID Register */
2832 u32 liodnr
; /* LIODN Register */
2836 typedef struct ccsr_pme
{
2838 u32 liodnbr
; /* LIODN Base Register */
2840 u32 srcidr
; /* Source ID Register */
2842 u32 liodnr
; /* LIODN Register */
2844 u32 pm_ip_rev_1
; /* PME IP Block Revision Reg 1*/
2845 u32 pm_ip_rev_2
; /* PME IP Block Revision Reg 1*/
2849 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
2850 struct ccsr_usb_port_ctrl
{
2867 typedef struct ccsr_usb_phy
{
2869 struct ccsr_usb_port_ctrl port1
;
2877 struct ccsr_usb_port_ctrl port2
;
2881 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
2882 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
2883 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
2884 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
2885 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
2886 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
2887 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
2889 typedef struct ccsr_usb_phy
{
2891 u32 usb_enable_override
;
2894 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
2897 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
2900 u32 liodnbr
; /* LIODN Base Register */
2904 u32 cfg0
; /* cfg register 0 */
2905 u32 cfg1
; /* cfg register 1 */
2913 #ifdef CONFIG_SYS_DPAA_RMAN
2916 u32 mmliodnbr
; /* Message Manager LIODN Base Register */
2917 u32 mmitar
; /* RMAN Inbound Translation Address Register */
2918 u32 mmitdr
; /* RMAN Inbound Translation Data Register */
2923 #ifdef CONFIG_SYS_PMAN
2926 u32 poes1
; /* PMAN Operation Error Status Register 1 */
2927 u32 poes2
; /* PMAN Operation Error Status Register 2 */
2928 u32 poeah
; /* PMAN Operation Error Address High */
2929 u32 poeal
; /* PMAN Operation Error Address Low */
2931 u32 pr1
; /* PMAN Revision Register 1 */
2932 u32 pr2
; /* PMAN Revision Register 2 */
2934 u32 pcap
; /* PMAN Capabilities Register */
2936 u32 pc1
; /* PMAN Control Register 1 */
2937 u32 pc2
; /* PMAN Control Register 2 */
2938 u32 pc3
; /* PMAN Control Register 3 */
2939 u32 pc4
; /* PMAN Control Register 4 */
2940 u32 pc5
; /* PMAN Control Register 5 */
2941 u32 pc6
; /* PMAN Control Register 6 */
2943 u32 ppa1
; /* PMAN Prefetch Attributes Register 1 */
2944 u32 ppa2
; /* PMAN Prefetch Attributes Register 2 */
2946 u32 pics
; /* PMAN Interrupt Control and Status */
2951 #ifdef CONFIG_FSL_CORENET
2952 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2953 #ifdef CONFIG_SYS_PMAN
2954 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2955 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2956 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2958 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2959 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2960 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2961 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2962 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2963 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2964 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2965 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2966 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2967 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2968 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2969 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2970 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2971 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2972 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2973 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2974 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2975 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
2976 && !defined(CONFIG_PPC_B4420)
2977 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2978 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2979 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2980 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2982 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2983 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2984 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2985 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2987 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2988 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2989 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
2990 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2991 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2992 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2993 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2994 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2995 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2996 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2997 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2998 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2999 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
3000 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
3001 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
3002 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
3003 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
3004 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
3005 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
3006 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
3007 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
3008 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
3009 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
3010 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
3011 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
3012 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
3013 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
3014 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
3015 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
3016 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
3017 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
3018 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
3020 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
3021 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
3022 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
3023 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
3024 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
3025 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
3026 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
3027 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
3028 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
3029 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
3030 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
3031 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
3032 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
3034 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
3036 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
3037 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
3038 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
3039 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
3040 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
3041 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
3042 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
3043 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
3044 #ifdef CONFIG_TSECV2
3045 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
3046 #elif defined(CONFIG_TSECV2_1)
3047 #define CONFIG_SYS_TSEC1_OFFSET 0x10000
3049 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
3051 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
3052 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
3053 #if defined(CONFIG_PPC_C29X)
3054 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
3056 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
3058 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
3059 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
3060 #define CONFIG_SYS_SNVS_OFFSET 0xE6000
3061 #define CONFIG_SYS_SFP_OFFSET 0xE7000
3062 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
3063 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
3064 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
3065 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
3066 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
3067 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
3068 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
3071 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
3072 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
3073 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
3075 #if defined(CONFIG_BSC9132)
3076 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
3077 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
3078 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
3081 #define CONFIG_SYS_FSL_CPC_ADDR \
3082 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
3083 #define CONFIG_SYS_FSL_QMAN_ADDR \
3084 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
3085 #define CONFIG_SYS_FSL_BMAN_ADDR \
3086 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
3087 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
3088 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
3089 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
3090 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
3091 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
3092 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
3093 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
3094 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
3095 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
3096 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
3097 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
3098 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
3099 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
3100 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
3101 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
3102 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
3103 #define CONFIG_SYS_MPC8xxx_DDR_ADDR \
3104 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
3105 #define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
3106 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
3107 #define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
3108 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
3109 #define CONFIG_SYS_LBC_ADDR \
3110 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
3111 #define CONFIG_SYS_IFC_ADDR \
3112 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
3113 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
3114 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
3115 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
3116 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
3117 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
3118 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
3119 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
3120 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
3121 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
3122 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
3123 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
3124 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
3125 #define CONFIG_SYS_MPC85xx_L2_ADDR \
3126 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
3127 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
3128 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
3129 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
3130 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
3131 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
3132 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
3133 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
3134 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
3135 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
3136 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
3137 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
3138 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
3139 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3140 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
3141 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3142 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
3143 #define CONFIG_SYS_MPC85xx_USB_ADDR \
3144 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
3145 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3146 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3147 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3148 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
3149 #define CONFIG_SYS_FSL_SEC_ADDR \
3150 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
3151 #define CONFIG_SYS_FSL_FM1_ADDR \
3152 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3153 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3154 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3155 #define CONFIG_SYS_FSL_FM2_ADDR \
3156 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
3157 #define CONFIG_SYS_FSL_SRIO_ADDR \
3158 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
3160 #define CONFIG_SYS_PCI1_ADDR \
3161 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3162 #define CONFIG_SYS_PCI2_ADDR \
3163 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3164 #define CONFIG_SYS_PCIE1_ADDR \
3165 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3166 #define CONFIG_SYS_PCIE2_ADDR \
3167 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3168 #define CONFIG_SYS_PCIE3_ADDR \
3169 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
3170 #define CONFIG_SYS_PCIE4_ADDR \
3171 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
3173 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3174 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3176 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3177 struct ccsr_cluster_l2
{
3178 u32 l2csr0
; /* 0x000 L2 cache control and status register 0 */
3179 u32 l2csr1
; /* 0x004 L2 cache control and status register 1 */
3180 u32 l2cfg0
; /* 0x008 L2 cache configuration register 0 */
3181 u8 res_0c
[500];/* 0x00c - 0x1ff */
3182 u32 l2pir0
; /* 0x200 L2 cache partitioning ID register 0 */
3184 u32 l2par0
; /* 0x208 L2 cache partitioning allocation register 0 */
3185 u32 l2pwr0
; /* 0x20c L2 cache partitioning way register 0 */
3186 u32 l2pir1
; /* 0x210 L2 cache partitioning ID register 1 */
3188 u32 l2par1
; /* 0x218 L2 cache partitioning allocation register 1 */
3189 u32 l2pwr1
; /* 0x21c L2 cache partitioning way register 1 */
3190 u32 u2pir2
; /* 0x220 L2 cache partitioning ID register 2 */
3192 u32 l2par2
; /* 0x228 L2 cache partitioning allocation register 2 */
3193 u32 l2pwr2
; /* 0x22c L2 cache partitioning way register 2 */
3194 u32 l2pir3
; /* 0x230 L2 cache partitioning ID register 3 */
3196 u32 l2par3
; /* 0x238 L2 cache partitining allocation register 3 */
3197 u32 l2pwr3
; /* 0x23c L2 cache partitining way register 3 */
3198 u32 l2pir4
; /* 0x240 L2 cache partitioning ID register 3 */
3200 u32 l2par4
; /* 0x248 L2 cache partitioning allocation register 3 */
3201 u32 l2pwr4
; /* 0x24c L2 cache partitioning way register 3 */
3202 u32 l2pir5
; /* 0x250 L2 cache partitioning ID register 3 */
3204 u32 l2par5
; /* 0x258 L2 cache partitioning allocation register 3 */
3205 u32 l2pwr5
; /* 0x25c L2 cache partitioning way register 3 */
3206 u32 l2pir6
; /* 0x260 L2 cache partitioning ID register 3 */
3208 u32 l2par6
; /* 0x268 L2 cache partitioning allocation register 3 */
3209 u32 l2pwr6
; /* 0x26c L2 cache partitioning way register 3 */
3210 u32 l2pir7
; /* 0x270 L2 cache partitioning ID register 3 */
3212 u32 l2par7
; /* 0x278 L2 cache partitioning allocation register 3 */
3213 u32 l2pwr7
; /* 0x27c L2 cache partitioning way register 3 */
3214 u8 res_280
[0xb80]; /* 0x280 - 0xdff */
3215 u32 l2errinjhi
; /* 0xe00 L2 cache error injection mask high */
3216 u32 l2errinjlo
; /* 0xe04 L2 cache error injection mask low */
3217 u32 l2errinjctl
;/* 0xe08 L2 cache error injection control */
3218 u8 res_e0c
[20]; /* 0xe0c - 0x01f */
3219 u32 l2captdatahi
; /* 0xe20 L2 cache error capture data high */
3220 u32 l2captdatalo
; /* 0xe24 L2 cache error capture data low */
3221 u32 l2captecc
; /* 0xe28 L2 cache error capture ECC syndrome */
3222 u8 res_e2c
[20]; /* 0xe2c - 0xe3f */
3223 u32 l2errdet
; /* 0xe40 L2 cache error detect */
3224 u32 l2errdis
; /* 0xe44 L2 cache error disable */
3225 u32 l2errinten
; /* 0xe48 L2 cache error interrupt enable */
3226 u32 l2errattr
; /* 0xe4c L2 cache error attribute */
3227 u32 l2erreaddr
; /* 0xe50 L2 cache error extended address */
3228 u32 l2erraddr
; /* 0xe54 L2 cache error address */
3229 u32 l2errctl
; /* 0xe58 L2 cache error control */
3231 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3232 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3233 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
3235 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3236 struct dcsr_dcfg_regs
{
3239 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3240 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3241 u8 res_524
[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3243 #endif /*__IMMAP_85xx__*/