2 * MPC86xx Internal Memory Map
4 * Copyright 2004, 2011 Freescale Semiconductor
5 * Jeff Brown (Jeffrey@freescale.com)
6 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
10 #ifndef __IMMAP_86xx__
11 #define __IMMAP_86xx__
13 #include <fsl_immap.h>
14 #include <asm/types.h>
15 #include <asm/fsl_dma.h>
16 #include <asm/fsl_lbc.h>
17 #include <asm/fsl_i2c.h>
19 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
20 typedef struct ccsr_local_mcm
{
21 uint ccsrbar
; /* 0x0 - Control Configuration Status Registers Base Address Register */
23 uint altcbar
; /* 0x8 - Alternate Configuration Base Address Register */
25 uint altcar
; /* 0x10 - Alternate Configuration Attribute Register */
27 uint bptr
; /* 0x20 - Boot Page Translation Register */
29 uint lawbar0
; /* 0xc08 - Local Access Window 0 Base Address Register */
31 uint lawar0
; /* 0xc10 - Local Access Window 0 Attributes Register */
33 uint lawbar1
; /* 0xc28 - Local Access Window 1 Base Address Register */
35 uint lawar1
; /* 0xc30 - Local Access Window 1 Attributes Register */
37 uint lawbar2
; /* 0xc48 - Local Access Window 2 Base Address Register */
39 uint lawar2
; /* 0xc50 - Local Access Window 2 Attributes Register */
41 uint lawbar3
; /* 0xc68 - Local Access Window 3 Base Address Register */
43 uint lawar3
; /* 0xc70 - Local Access Window 3 Attributes Register */
45 uint lawbar4
; /* 0xc88 - Local Access Window 4 Base Address Register */
47 uint lawar4
; /* 0xc90 - Local Access Window 4 Attributes Register */
49 uint lawbar5
; /* 0xca8 - Local Access Window 5 Base Address Register */
51 uint lawar5
; /* 0xcb0 - Local Access Window 5 Attributes Register */
53 uint lawbar6
; /* 0xcc8 - Local Access Window 6 Base Address Register */
55 uint lawar6
; /* 0xcd0 - Local Access Window 6 Attributes Register */
57 uint lawbar7
; /* 0xce8 - Local Access Window 7 Base Address Register */
59 uint lawar7
; /* 0xcf0 - Local Access Window 7 Attributes Register */
61 uint lawbar8
; /* 0xd08 - Local Access Window 8 Base Address Register */
63 uint lawar8
; /* 0xd10 - Local Access Window 8 Attributes Register */
65 uint lawbar9
; /* 0xd28 - Local Access Window 9 Base Address Register */
67 uint lawar9
; /* 0xd30 - Local Access Window 9 Attributes Register */
69 uint abcr
; /* 0x1000 - MCM CCB Address Configuration Register */
71 uint dbcr
; /* 0x1008 - MCM MPX data bus Configuration Register */
73 uint pcr
; /* 0x1010 - MCM CCB Port Configuration Register */
75 uint hpmr0
; /* 0x1040 - MCM HPM Threshold Count Register 0 */
76 uint hpmr1
; /* 0x1044 - MCM HPM Threshold Count Register 1 */
77 uint hpmr2
; /* 0x1048 - MCM HPM Threshold Count Register 2 */
78 uint hpmr3
; /* 0x104c - MCM HPM Threshold Count Register 3 */
80 uint hpmr4
; /* 0x1060 - MCM HPM Threshold Count Register 4 */
81 uint hpmr5
; /* 0x1064 - MCM HPM Threshold Count Register 5 */
82 uint hpmccr
; /* 0x1068 - MCM HPM Cycle Count Register */
84 uint edr
; /* 0x1e00 - MCM Error Detect Register */
86 uint eer
; /* 0x1e08 - MCM Error Enable Register */
87 uint eatr
; /* 0x1e0c - MCM Error Attributes Capture Register */
88 uint eladr
; /* 0x1e10 - MCM Error Low Address Capture Register */
89 uint ehadr
; /* 0x1e14 - MCM Error High Address Capture Register */
93 /* Daul I2C Registers(0x3000-0x4000) */
94 typedef struct ccsr_i2c
{
95 struct fsl_i2c_base i2c
[2];
96 u8 res
[4096 - 2 * sizeof(struct fsl_i2c_base
)];
99 /* DUART Registers(0x4000-0x5000) */
100 typedef struct ccsr_duart
{
102 u_char urbr1_uthr1_udlb1
;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
103 u_char uier1_udmb1
; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
104 u_char uiir1_ufcr1_uafr1
;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
105 u_char ulcr1
; /* 0x4503 - UART1 Line Control Register */
106 u_char umcr1
; /* 0x4504 - UART1 Modem Control Register */
107 u_char ulsr1
; /* 0x4505 - UART1 Line Status Register */
108 u_char umsr1
; /* 0x4506 - UART1 Modem Status Register */
109 u_char uscr1
; /* 0x4507 - UART1 Scratch Register */
111 u_char udsr1
; /* 0x4510 - UART1 DMA Status Register */
113 u_char urbr2_uthr2_udlb2
;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
114 u_char uier2_udmb2
; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
115 u_char uiir2_ufcr2_uafr2
;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
116 u_char ulcr2
; /* 0x4603 - UART2 Line Control Register */
117 u_char umcr2
; /* 0x4604 - UART2 Modem Control Register */
118 u_char ulsr2
; /* 0x4605 - UART2 Line Status Register */
119 u_char umsr2
; /* 0x4606 - UART2 Modem Status Register */
120 u_char uscr2
; /* 0x4607 - UART2 Scratch Register */
122 u_char udsr2
; /* 0x4610 - UART2 DMA Status Register */
126 /* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
127 typedef struct ccsr_pex
{
128 uint cfg_addr
; /* 0x8000 - PEX Configuration Address Register */
129 uint cfg_data
; /* 0x8004 - PEX Configuration Data Register */
131 uint out_comp_to
; /* 0x800C - PEX Outbound Completion Timeout Register */
133 uint pme_msg_det
; /* 0x8020 - PEX PME & message detect register */
134 uint pme_msg_int_en
; /* 0x8024 - PEX PME & message interrupt enable register */
135 uint pme_msg_dis
; /* 0x8028 - PEX PME & message disable register */
136 uint pm_command
; /* 0x802c - PEX PM Command register */
138 uint block_rev1
; /* 0x8bf8 - PEX Block Revision register 1 */
139 uint block_rev2
; /* 0x8bfc - PEX Block Revision register 2 */
140 uint potar0
; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
141 uint potear0
; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
143 uint powar0
; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
145 uint potar1
; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
146 uint potear1
; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
147 uint powbar1
; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
149 uint powar1
; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
151 uint potar2
; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
152 uint potear2
; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
153 uint powbar2
; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
155 uint powar2
; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
157 uint potar3
; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
158 uint potear3
; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
159 uint powbar3
; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
161 uint powar3
; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
163 uint potar4
; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
164 uint potear4
; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
165 uint powbar4
; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
167 uint powar4
; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
170 uint pitar3
; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
172 uint piwbar3
; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
173 uint piwbear3
; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
174 uint piwar3
; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
176 uint pitar2
; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
178 uint piwbar2
; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
179 uint piwbear2
; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
180 uint piwar2
; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
182 uint pitar1
; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
184 uint piwbar1
; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
186 uint piwar1
; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
188 uint pedr
; /* 0x8e00 - PEX Error Detect Register */
190 uint peer
; /* 0x8e08 - PEX Error Interrupt Enable Register */
192 uint pecdr
; /* 0x8e10 - PEX Error Disable Register */
194 uint peer_stat
; /* 0x8e20 - PEX Error Capture Status Register */
196 uint perr_cap0
; /* 0x8e28 - PEX Error Capture Register 0 */
197 uint perr_cap1
; /* 0x8e2c - PEX Error Capture Register 1 */
198 uint perr_cap2
; /* 0x8e30 - PEX Error Capture Register 2 */
199 uint perr_cap3
; /* 0x8e34 - PEX Error Capture Register 3 */
204 /* Hyper Transport Register Block (0xA000-0xB000) */
205 typedef struct ccsr_ht
{
206 uint hcfg_addr
; /* 0xa000 - HT Configuration Address register */
207 uint hcfg_data
; /* 0xa004 - HT Configuration Data register */
209 uint howtar0
; /* 0xac00 - HT Outbound Window 0 Translation register */
211 uint howar0
; /* 0xac10 - HT Outbound Window 0 Attributes register */
213 uint howtar1
; /* 0xac20 - HT Outbound Window 1 Translation register */
215 uint howbar1
; /* 0xac28 - HT Outbound Window 1 Base Address register */
217 uint howar1
; /* 0xac30 - HT Outbound Window 1 Attributes register */
219 uint howtar2
; /* 0xac40 - HT Outbound Window 2 Translation register */
221 uint howbar2
; /* 0xac48 - HT Outbound Window 2 Base Address register */
223 uint howar2
; /* 0xac50 - HT Outbound Window 2 Attributes register */
225 uint howtar3
; /* 0xac60 - HT Outbound Window 3 Translation register */
227 uint howbar3
; /* 0xac68 - HT Outbound Window 3 Base Address register */
229 uint howar3
; /* 0xac70 - HT Outbound Window 3 Attributes register */
231 uint howtar4
; /* 0xac80 - HT Outbound Window 4 Translation register */
233 uint howbar4
; /* 0xac88 - HT Outbound Window 4 Base Address register */
235 uint howar4
; /* 0xac90 - HT Outbound Window 4 Attributes register */
237 uint hiwtar4
; /* 0xad80 - HT Inbound Window 4 Translation register */
239 uint hiwbar4
; /* 0xad88 - HT Inbound Window 4 Base Address register */
241 uint hiwar4
; /* 0xad90 - HT Inbound Window 4 Attributes register */
243 uint hiwtar3
; /* 0xada0 - HT Inbound Window 3 Translation register */
245 uint hiwbar3
; /* 0xada8 - HT Inbound Window 3 Base Address register */
247 uint hiwar3
; /* 0xadb0 - HT Inbound Window 3 Attributes register */
249 uint hiwtar2
; /* 0xadc0 - HT Inbound Window 2 Translation register */
251 uint hiwbar2
; /* 0xadc8 - HT Inbound Window 2 Base Address register */
253 uint hiwar2
; /* 0xadd0 - HT Inbound Window 2 Attributes register */
255 uint hiwtar1
; /* 0xade0 - HT Inbound Window 1 Translation register */
257 uint hiwbar1
; /* 0xade8 - HT Inbound Window 1 Base Address register */
259 uint hiwar1
; /* 0xadf0 - HT Inbound Window 1 Attributes register */
261 uint hedr
; /* 0xae00 - HT Error Detect register */
263 uint heier
; /* 0xae08 - HT Error Interrupt Enable register */
265 uint hecdr
; /* 0xae10 - HT Error Capture Disbale register */
267 uint hecsr
; /* 0xae20 - HT Error Capture Status register */
269 uint hec0
; /* 0xae28 - HT Error Capture 0 register */
270 uint hec1
; /* 0xae2c - HT Error Capture 1 register */
271 uint hec2
; /* 0xae30 - HT Error Capture 2 register */
275 /* DMA Registers(0x2_1000-0x2_2000) */
276 typedef struct ccsr_dma
{
278 struct fsl_dma dma
[4];
279 uint dgsr
; /* 0x21300 - DMA General Status Register */
283 /* tsec1-4: 24000-28000 */
284 typedef struct ccsr_tsec
{
285 uint id
; /* 0x24000 - Controller ID Register */
287 uint ievent
; /* 0x24010 - Interrupt Event Register */
288 uint imask
; /* 0x24014 - Interrupt Mask Register */
289 uint edis
; /* 0x24018 - Error Disabled Register */
291 uint ecntrl
; /* 0x24020 - Ethernet Control Register */
293 uint ptv
; /* 0x24028 - Pause Time Value Register */
294 uint dmactrl
; /* 0x2402c - DMA Control Register */
295 uint tbipa
; /* 0x24030 - TBI PHY Address Register */
297 uint fifo_tx_thr
; /* 0x2408c - FIFO transmit threshold register */
299 uint fifo_tx_starve
; /* 0x24098 - FIFO transmit starve register */
300 uint fifo_tx_starve_shutoff
;/* 0x2409c - FIFO transmit starve shutoff register */
302 uint fifo_rx_pause
; /* 0x240a4 - FIFO receive pause threshold register */
303 uint fifo_rx_alarm
; /* 0x240a8 - FIFO receive alarm threshold register */
305 uint tctrl
; /* 0x24100 - Transmit Control Register */
306 uint tstat
; /* 0x24104 - Transmit Status Register */
307 uint dfvlan
; /* 0x24108 - Default VLAN control word */
309 uint txic
; /* 0x24110 - Transmit interrupt coalescing Register */
310 uint tqueue
; /* 0x24114 - Transmit Queue Control Register */
312 uint tr03wt
; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
313 uint tw47wt
; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
315 uint tbdbph
; /* 0x2417c - Transmit Data Buffer Pointer High Register */
317 uint tbptr0
; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
319 uint tbptr1
; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
321 uint tbptr2
; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
323 uint tbptr3
; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
325 uint tbptr4
; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
327 uint tbptr5
; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
329 uint tbptr6
; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
331 uint tbptr7
; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
333 uint tbaseh
; /* 0x24200 - Transmit Descriptor Base Address High Register */
334 uint tbase0
; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
336 uint tbase1
; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
338 uint tbase2
; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
340 uint tbase3
; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
342 uint tbase4
; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
344 uint tbase5
; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
346 uint tbase6
; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
348 uint tbase7
; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
350 uint rctrl
; /* 0x24300 - Receive Control Register */
351 uint rstat
; /* 0x24304 - Receive Status Register */
353 uint rxic
; /* 0x24310 - Receive Interrupt Coalecing Register */
354 uint rqueue
; /* 0x24314 - Receive queue control register */
356 uint rbifx
; /* 0x24330 - Receive bit field extract control Register */
357 uint rqfar
; /* 0x24334 - Receive queue filing table address Register */
358 uint rqfcr
; /* 0x24338 - Receive queue filing table control Register */
359 uint rqfpr
; /* 0x2433c - Receive queue filing table property Register */
360 uint mrblr
; /* 0x24340 - Maximum Receive Buffer Length Register */
362 uint rbdbph
; /* 0x2437C - Receive Data Buffer Pointer High */
364 uint rbptr0
; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
366 uint rbptr1
; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
368 uint rbptr2
; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
370 uint rbptr3
; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
372 uint rbptr4
; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
374 uint rbptr5
; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
376 uint rbptr6
; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
378 uint rbptr7
; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
380 uint rbaseh
; /* 0x24400 - Receive Descriptor Base Address High 0 */
381 uint rbase0
; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
383 uint rbase1
; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
385 uint rbase2
; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
387 uint rbase3
; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
389 uint rbase4
; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
391 uint rbase5
; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
393 uint rbase6
; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
395 uint rbase7
; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
397 uint maccfg1
; /* 0x24500 - MAC Configuration 1 Register */
398 uint maccfg2
; /* 0x24504 - MAC Configuration 2 Register */
399 uint ipgifg
; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
400 uint hafdup
; /* 0x2450c - Half Duplex Register */
401 uint maxfrm
; /* 0x24510 - Maximum Frame Length Register */
403 uint miimcfg
; /* 0x24520 - MII Management Configuration Register */
404 uint miimcom
; /* 0x24524 - MII Management Command Register */
405 uint miimadd
; /* 0x24528 - MII Management Address Register */
406 uint miimcon
; /* 0x2452c - MII Management Control Register */
407 uint miimstat
; /* 0x24530 - MII Management Status Register */
408 uint miimind
; /* 0x24534 - MII Management Indicator Register */
409 uint ifctrl
; /* 0x24538 - Interface Contrl Register */
410 uint ifstat
; /* 0x2453c - Interface Status Register */
411 uint macstnaddr1
; /* 0x24540 - Station Address Part 1 Register */
412 uint macstnaddr2
; /* 0x24544 - Station Address Part 2 Register */
413 uint mac01addr1
; /* 0x24548 - MAC exact match address 1, part 1 */
414 uint mac01addr2
; /* 0x2454C - MAC exact match address 1, part 2 */
415 uint mac02addr1
; /* 0x24550 - MAC exact match address 2, part 1 */
416 uint mac02addr2
; /* 0x24554 - MAC exact match address 2, part 2 */
417 uint mac03addr1
; /* 0x24558 - MAC exact match address 3, part 1 */
418 uint mac03addr2
; /* 0x2455C - MAC exact match address 3, part 2 */
419 uint mac04addr1
; /* 0x24560 - MAC exact match address 4, part 1 */
420 uint mac04addr2
; /* 0x24564 - MAC exact match address 4, part 2 */
421 uint mac05addr1
; /* 0x24568 - MAC exact match address 5, part 1 */
422 uint mac05addr2
; /* 0x2456C - MAC exact match address 5, part 2 */
423 uint mac06addr1
; /* 0x24570 - MAC exact match address 6, part 1 */
424 uint mac06addr2
; /* 0x24574 - MAC exact match address 6, part 2 */
425 uint mac07addr1
; /* 0x24578 - MAC exact match address 7, part 1 */
426 uint mac07addr2
; /* 0x2457C - MAC exact match address 7, part 2 */
427 uint mac08addr1
; /* 0x24580 - MAC exact match address 8, part 1 */
428 uint mac08addr2
; /* 0x24584 - MAC exact match address 8, part 2 */
429 uint mac09addr1
; /* 0x24588 - MAC exact match address 9, part 1 */
430 uint mac09addr2
; /* 0x2458C - MAC exact match address 9, part 2 */
431 uint mac10addr1
; /* 0x24590 - MAC exact match address 10, part 1 */
432 uint mac10addr2
; /* 0x24594 - MAC exact match address 10, part 2 */
433 uint mac11addr1
; /* 0x24598 - MAC exact match address 11, part 1 */
434 uint mac11addr2
; /* 0x2459C - MAC exact match address 11, part 2 */
435 uint mac12addr1
; /* 0x245A0 - MAC exact match address 12, part 1 */
436 uint mac12addr2
; /* 0x245A4 - MAC exact match address 12, part 2 */
437 uint mac13addr1
; /* 0x245A8 - MAC exact match address 13, part 1 */
438 uint mac13addr2
; /* 0x245AC - MAC exact match address 13, part 2 */
439 uint mac14addr1
; /* 0x245B0 - MAC exact match address 14, part 1 */
440 uint mac14addr2
; /* 0x245B4 - MAC exact match address 14, part 2 */
441 uint mac15addr1
; /* 0x245B8 - MAC exact match address 15, part 1 */
442 uint mac15addr2
; /* 0x245BC - MAC exact match address 15, part 2 */
444 uint tr64
; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
445 uint tr127
; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
446 uint tr255
; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
447 uint tr511
; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
448 uint tr1k
; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
449 uint trmax
; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
450 uint trmgv
; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
451 uint rbyt
; /* 0x2469c - Receive Byte Counter */
452 uint rpkt
; /* 0x246a0 - Receive Packet Counter */
453 uint rfcs
; /* 0x246a4 - Receive FCS Error Counter */
454 uint rmca
; /* 0x246a8 - Receive Multicast Packet Counter */
455 uint rbca
; /* 0x246ac - Receive Broadcast Packet Counter */
456 uint rxcf
; /* 0x246b0 - Receive Control Frame Packet Counter */
457 uint rxpf
; /* 0x246b4 - Receive Pause Frame Packet Counter */
458 uint rxuo
; /* 0x246b8 - Receive Unknown OP Code Counter */
459 uint raln
; /* 0x246bc - Receive Alignment Error Counter */
460 uint rflr
; /* 0x246c0 - Receive Frame Length Error Counter */
461 uint rcde
; /* 0x246c4 - Receive Code Error Counter */
462 uint rcse
; /* 0x246c8 - Receive Carrier Sense Error Counter */
463 uint rund
; /* 0x246cc - Receive Undersize Packet Counter */
464 uint rovr
; /* 0x246d0 - Receive Oversize Packet Counter */
465 uint rfrg
; /* 0x246d4 - Receive Fragments Counter */
466 uint rjbr
; /* 0x246d8 - Receive Jabber Counter */
467 uint rdrp
; /* 0x246dc - Receive Drop Counter */
468 uint tbyt
; /* 0x246e0 - Transmit Byte Counter Counter */
469 uint tpkt
; /* 0x246e4 - Transmit Packet Counter */
470 uint tmca
; /* 0x246e8 - Transmit Multicast Packet Counter */
471 uint tbca
; /* 0x246ec - Transmit Broadcast Packet Counter */
472 uint txpf
; /* 0x246f0 - Transmit Pause Control Frame Counter */
473 uint tdfr
; /* 0x246f4 - Transmit Deferral Packet Counter */
474 uint tedf
; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
475 uint tscl
; /* 0x246fc - Transmit Single Collision Packet Counter */
476 uint tmcl
; /* 0x24700 - Transmit Multiple Collision Packet Counter */
477 uint tlcl
; /* 0x24704 - Transmit Late Collision Packet Counter */
478 uint txcl
; /* 0x24708 - Transmit Excessive Collision Packet Counter */
479 uint tncl
; /* 0x2470c - Transmit Total Collision Counter */
481 uint tdrp
; /* 0x24714 - Transmit Drop Frame Counter */
482 uint tjbr
; /* 0x24718 - Transmit Jabber Frame Counter */
483 uint tfcs
; /* 0x2471c - Transmit FCS Error Counter */
484 uint txcf
; /* 0x24720 - Transmit Control Frame Counter */
485 uint tovr
; /* 0x24724 - Transmit Oversize Frame Counter */
486 uint tund
; /* 0x24728 - Transmit Undersize Frame Counter */
487 uint tfrg
; /* 0x2472c - Transmit Fragments Frame Counter */
488 uint car1
; /* 0x24730 - Carry Register One */
489 uint car2
; /* 0x24734 - Carry Register Two */
490 uint cam1
; /* 0x24738 - Carry Mask Register One */
491 uint cam2
; /* 0x2473c - Carry Mask Register Two */
492 uint rrej
; /* 0x24740 - Receive filer rejected packet counter */
494 uint iaddr0
; /* 0x24800 - Indivdual address register 0 */
495 uint iaddr1
; /* 0x24804 - Indivdual address register 1 */
496 uint iaddr2
; /* 0x24808 - Indivdual address register 2 */
497 uint iaddr3
; /* 0x2480c - Indivdual address register 3 */
498 uint iaddr4
; /* 0x24810 - Indivdual address register 4 */
499 uint iaddr5
; /* 0x24814 - Indivdual address register 5 */
500 uint iaddr6
; /* 0x24818 - Indivdual address register 6 */
501 uint iaddr7
; /* 0x2481c - Indivdual address register 7 */
503 uint gaddr0
; /* 0x24880 - Global address register 0 */
504 uint gaddr1
; /* 0x24884 - Global address register 1 */
505 uint gaddr2
; /* 0x24888 - Global address register 2 */
506 uint gaddr3
; /* 0x2488c - Global address register 3 */
507 uint gaddr4
; /* 0x24890 - Global address register 4 */
508 uint gaddr5
; /* 0x24894 - Global address register 5 */
509 uint gaddr6
; /* 0x24898 - Global address register 6 */
510 uint gaddr7
; /* 0x2489c - Global address register 7 */
512 uint fifocfg
; /* 0x24A00 - FIFO interface configuration register */
514 uint attr
; /* 0x24BF8 - DMA Attribute register */
515 uint attreli
; /* 0x24BFC - DMA Attribute extract length and index register */
519 /* PIC Registers(0x4_0000-0x6_1000) */
521 typedef struct ccsr_pic
{
523 uint ipidr0
; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
525 uint ipidr1
; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
527 uint ipidr2
; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
529 uint ipidr3
; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
531 uint ctpr
; /* 0x40080 - Current Task Priority Register */
533 uint whoami
; /* 0x40090 - Who Am I Register */
535 uint iack
; /* 0x400a0 - Interrupt Acknowledge Register */
537 uint eoi
; /* 0x400b0 - End Of Interrupt Register */
539 uint frr
; /* 0x41000 - Feature Reporting Register */
541 uint gcr
; /* 0x41020 - Global Configuration Register */
542 #define MPC86xx_PICGCR_RST 0x80000000
543 #define MPC86xx_PICGCR_MODE 0x20000000
545 uint vir
; /* 0x41080 - Vendor Identification Register */
547 uint pir
; /* 0x41090 - Processor Initialization Register */
549 uint ipivpr0
; /* 0x410a0 - IPI Vector/Priority Register 0 */
551 uint ipivpr1
; /* 0x410b0 - IPI Vector/Priority Register 1 */
553 uint ipivpr2
; /* 0x410c0 - IPI Vector/Priority Register 2 */
555 uint ipivpr3
; /* 0x410d0 - IPI Vector/Priority Register 3 */
557 uint svr
; /* 0x410e0 - Spurious Vector Register */
559 uint tfrr
; /* 0x410f0 - Timer Frequency Reporting Register */
561 uint gtccr0
; /* 0x41100 - Global Timer Current Count Register 0 */
563 uint gtbcr0
; /* 0x41110 - Global Timer Base Count Register 0 */
565 uint gtvpr0
; /* 0x41120 - Global Timer Vector/Priority Register 0 */
567 uint gtdr0
; /* 0x41130 - Global Timer Destination Register 0 */
569 uint gtccr1
; /* 0x41140 - Global Timer Current Count Register 1 */
571 uint gtbcr1
; /* 0x41150 - Global Timer Base Count Register 1 */
573 uint gtvpr1
; /* 0x41160 - Global Timer Vector/Priority Register 1 */
575 uint gtdr1
; /* 0x41170 - Global Timer Destination Register 1 */
577 uint gtccr2
; /* 0x41180 - Global Timer Current Count Register 2 */
579 uint gtbcr2
; /* 0x41190 - Global Timer Base Count Register 2 */
581 uint gtvpr2
; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
583 uint gtdr2
; /* 0x411b0 - Global Timer Destination Register 2 */
585 uint gtccr3
; /* 0x411c0 - Global Timer Current Count Register 3 */
587 uint gtbcr3
; /* 0x411d0 - Global Timer Base Count Register 3 */
589 uint gtvpr3
; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
591 uint gtdr3
; /* 0x411f0 - Global Timer Destination Register 3 */
593 uint tcr
; /* 0x41300 - Timer Control Register */
595 uint irqsr0
; /* 0x41310 - IRQ_OUT Summary Register 0 */
597 uint irqsr1
; /* 0x41320 - IRQ_OUT Summary Register 1 */
599 uint cisr0
; /* 0x41330 - Critical Interrupt Summary Register 0 */
601 uint cisr1
; /* 0x41340 - Critical Interrupt Summary Register 1 */
603 uint pm0mr0
; /* 0x41350 - Performance monitor 0 mask register 0 */
605 uint pm0mr1
; /* 0x41360 - Performance monitor 0 mask register 1 */
607 uint pm1mr0
; /* 0x41370 - Performance monitor 1 mask register 0 */
609 uint pm1mr1
; /* 0x41380 - Performance monitor 1 mask register 1 */
611 uint pm2mr0
; /* 0x41390 - Performance monitor 2 mask register 0 */
613 uint pm2mr1
; /* 0x413A0 - Performance monitor 2 mask register 1 */
615 uint pm3mr0
; /* 0x413B0 - Performance monitor 3 mask register 0 */
617 uint pm3mr1
; /* 0x413C0 - Performance monitor 3 mask register 1 */
619 uint msgr0
; /* 0x41400 - Message Register 0 */
621 uint msgr1
; /* 0x41410 - Message Register 1 */
623 uint msgr2
; /* 0x41420 - Message Register 2 */
625 uint msgr3
; /* 0x41430 - Message Register 3 */
627 uint mer
; /* 0x41500 - Message Enable Register */
629 uint msr
; /* 0x41510 - Message Status Register */
631 uint eivpr0
; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
633 uint eidr0
; /* 0x50010 - External Interrupt Destination Register 0 */
635 uint eivpr1
; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
637 uint eidr1
; /* 0x50030 - External Interrupt Destination Register 1 */
639 uint eivpr2
; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
641 uint eidr2
; /* 0x50050 - External Interrupt Destination Register 2 */
643 uint eivpr3
; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
645 uint eidr3
; /* 0x50070 - External Interrupt Destination Register 3 */
647 uint eivpr4
; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
649 uint eidr4
; /* 0x50090 - External Interrupt Destination Register 4 */
651 uint eivpr5
; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
653 uint eidr5
; /* 0x500b0 - External Interrupt Destination Register 5 */
655 uint eivpr6
; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
657 uint eidr6
; /* 0x500d0 - External Interrupt Destination Register 6 */
659 uint eivpr7
; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
661 uint eidr7
; /* 0x500f0 - External Interrupt Destination Register 7 */
663 uint eivpr8
; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
665 uint eidr8
; /* 0x50110 - External Interrupt Destination Register 8 */
667 uint eivpr9
; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
669 uint eidr9
; /* 0x50130 - External Interrupt Destination Register 9 */
671 uint eivpr10
; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
673 uint eidr10
; /* 0x50150 - External Interrupt Destination Register 10 */
675 uint eivpr11
; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
677 uint eidr11
; /* 0x50170 - External Interrupt Destination Register 11 */
679 uint iivpr0
; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
681 uint iidr0
; /* 0x50210 - Internal Interrupt Destination Register 0 */
683 uint iivpr1
; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
685 uint iidr1
; /* 0x50230 - Internal Interrupt Destination Register 1 */
687 uint iivpr2
; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
689 uint iidr2
; /* 0x50250 - Internal Interrupt Destination Register 2 */
691 uint iivpr3
; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
693 uint iidr3
; /* 0x50270 - Internal Interrupt Destination Register 3 */
695 uint iivpr4
; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
697 uint iidr4
; /* 0x50290 - Internal Interrupt Destination Register 4 */
699 uint iivpr5
; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
701 uint iidr5
; /* 0x502b0 - Internal Interrupt Destination Register 5 */
703 uint iivpr6
; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
705 uint iidr6
; /* 0x502d0 - Internal Interrupt Destination Register 6 */
707 uint iivpr7
; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
709 uint iidr7
; /* 0x502f0 - Internal Interrupt Destination Register 7 */
711 uint iivpr8
; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
713 uint iidr8
; /* 0x50310 - Internal Interrupt Destination Register 8 */
715 uint iivpr9
; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
717 uint iidr9
; /* 0x50330 - Internal Interrupt Destination Register 9 */
719 uint iivpr10
; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
721 uint iidr10
; /* 0x50350 - Internal Interrupt Destination Register 10 */
723 uint iivpr11
; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
725 uint iidr11
; /* 0x50370 - Internal Interrupt Destination Register 11 */
727 uint iivpr12
; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
729 uint iidr12
; /* 0x50390 - Internal Interrupt Destination Register 12 */
731 uint iivpr13
; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
733 uint iidr13
; /* 0x503b0 - Internal Interrupt Destination Register 13 */
735 uint iivpr14
; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
737 uint iidr14
; /* 0x503d0 - Internal Interrupt Destination Register 14 */
739 uint iivpr15
; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
741 uint iidr15
; /* 0x503f0 - Internal Interrupt Destination Register 15 */
743 uint iivpr16
; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
745 uint iidr16
; /* 0x50410 - Internal Interrupt Destination Register 16 */
747 uint iivpr17
; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
749 uint iidr17
; /* 0x50430 - Internal Interrupt Destination Register 17 */
751 uint iivpr18
; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
753 uint iidr18
; /* 0x50450 - Internal Interrupt Destination Register 18 */
755 uint iivpr19
; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
757 uint iidr19
; /* 0x50470 - Internal Interrupt Destination Register 19 */
759 uint iivpr20
; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
761 uint iidr20
; /* 0x50490 - Internal Interrupt Destination Register 20 */
763 uint iivpr21
; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
765 uint iidr21
; /* 0x504b0 - Internal Interrupt Destination Register 21 */
767 uint iivpr22
; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
769 uint iidr22
; /* 0x504d0 - Internal Interrupt Destination Register 22 */
771 uint iivpr23
; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
773 uint iidr23
; /* 0x504f0 - Internal Interrupt Destination Register 23 */
775 uint iivpr24
; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
777 uint iidr24
; /* 0x50510 - Internal Interrupt Destination Register 24 */
779 uint iivpr25
; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
781 uint iidr25
; /* 0x50530 - Internal Interrupt Destination Register 25 */
783 uint iivpr26
; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
785 uint iidr26
; /* 0x50550 - Internal Interrupt Destination Register 26 */
787 uint iivpr27
; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
789 uint iidr27
; /* 0x50570 - Internal Interrupt Destination Register 27 */
791 uint iivpr28
; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
793 uint iidr28
; /* 0x50590 - Internal Interrupt Destination Register 28 */
795 uint iivpr29
; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
797 uint iidr29
; /* 0x505b0 - Internal Interrupt Destination Register 29 */
799 uint iivpr30
; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
801 uint iidr30
; /* 0x505d0 - Internal Interrupt Destination Register 30 */
803 uint iivpr31
; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
805 uint iidr31
; /* 0x505f0 - Internal Interrupt Destination Register 31 */
807 uint mivpr0
; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
809 uint midr0
; /* 0x51610 - Messaging Interrupt Destination Register 0 */
811 uint mivpr1
; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
813 uint midr1
; /* 0x51630 - Messaging Interrupt Destination Register 1 */
815 uint mivpr2
; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
817 uint midr2
; /* 0x51650 - Messaging Interrupt Destination Register 2 */
819 uint mivpr3
; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
821 uint midr3
; /* 0x51670 - Messaging Interrupt Destination Register 3 */
823 uint ipi0dr0
; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
825 uint ipi0dr1
; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
827 uint ipi0dr2
; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
829 uint ipi0dr3
; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
831 uint ctpr0
; /* 0x60080 - Current Task Priority Register for Processor 0 */
833 uint whoami0
; /* 0x60090 - Who Am I Register for Processor 0 */
835 uint iack0
; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
837 uint eoi0
; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
841 /* RapidIO Registers(0xc_0000-0xe_0000) */
843 typedef struct ccsr_rio
{
844 uint didcar
; /* 0xc0000 - Device Identity Capability Register */
845 uint dicar
; /* 0xc0004 - Device Information Capability Register */
846 uint aidcar
; /* 0xc0008 - Assembly Identity Capability Register */
847 uint aicar
; /* 0xc000c - Assembly Information Capability Register */
848 uint pefcar
; /* 0xc0010 - Processing Element Features Capability Register */
849 uint spicar
; /* 0xc0014 - Switch Port Information Capability Register */
850 uint socar
; /* 0xc0018 - Source Operations Capability Register */
851 uint docar
; /* 0xc001c - Destination Operations Capability Register */
853 uint msr
; /* 0xc0040 - Mailbox Command And Status Register */
854 uint pwdcsr
; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
856 uint pellccsr
; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
858 uint lcsbacsr
; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
859 uint bdidcsr
; /* 0xc0060 - Base Device ID Command and Status Register */
861 uint hbdidlcsr
; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
862 uint ctcsr
; /* 0xc006c - Component Tag Command and Status Register */
864 uint pmbh0csr
; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
866 uint pltoccsr
; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
867 uint prtoccsr
; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
869 uint pgccsr
; /* 0xc013c - Port General Command and Status Register */
870 uint plmreqcsr
; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
871 uint plmrespcsr
; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
872 uint plascsr
; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
874 uint pescsr
; /* 0xc0158 - Port Error and Status Command and Status Register */
875 uint pccsr
; /* 0xc015c - Port Control Command and Status Register */
877 uint erbh
; /* 0xc0600 - Error Reporting Block Header Register */
879 uint ltledcsr
; /* 0xc0608 - Logical/Transport layer error detect status register */
880 uint ltleecsr
; /* 0xc060c - Logical/Transport layer error enable register */
882 uint ltlaccsr
; /* 0xc0614 - Logical/Transport layer addresss capture register */
883 uint ltldidccsr
; /* 0xc0618 - Logical/Transport layer device ID capture register */
884 uint ltlcccsr
; /* 0xc061c - Logical/Transport layer control capture register */
886 uint edcsr
; /* 0xc0640 - Port 0 error detect status register */
887 uint erecsr
; /* 0xc0644 - Port 0 error rate enable status register */
888 uint ecacsr
; /* 0xc0648 - Port 0 error capture attributes register */
889 uint pcseccsr0
; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
890 uint peccsr1
; /* 0xc0650 - Port 0 error capture command and status register 1 */
891 uint peccsr2
; /* 0xc0654 - Port 0 error capture command and status register 2 */
892 uint peccsr3
; /* 0xc0658 - Port 0 error capture command and status register 3 */
894 uint ercsr
; /* 0xc0668 - Port 0 error rate command and status register */
895 uint ertcsr
; /* 0xc066C - Port 0 error rate threshold status register*/
897 uint llcr
; /* 0xd0004 - Logical Layer Configuration Register */
899 uint epwisr
; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
901 uint lretcr
; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
903 uint pretcr
; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
905 uint adidcsr
; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
907 uint ptaacr
; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
909 uint iecsr
; /* 0xd0130 - Port 0 Implementation Error Status Register */
911 uint pcr
; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
913 uint slcsr
; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
915 uint sleir
; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
917 uint rowtar0
; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
918 uint rowtear0
; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
920 uint rowar0
; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
922 uint rowtar1
; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
923 uint rowtear1
; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
924 uint rowbar1
; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
926 uint rowar1
; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
927 uint rows1r1
; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
928 uint rows2r1
; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
929 uint rows3r1
; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
930 uint rowtar2
; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
931 uint rowtear2
; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
932 uint rowbar2
; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
934 uint rowar2
; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
935 uint rows1r2
; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
936 uint rows2r2
; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
937 uint rows3r2
; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
938 uint rowtar3
; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
939 uint rowtear3
; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
940 uint rowbar3
; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
942 uint rowar3
; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
943 uint rows1r3
; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
944 uint rows2r3
; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
945 uint rows3r3
; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
946 uint rowtar4
; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
947 uint rowtear4
; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
948 uint rowbar4
; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
950 uint rowar4
; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
951 uint rows1r4
; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
952 uint rows2r4
; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
953 uint rows3r4
; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
954 uint rowtar5
; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
955 uint rowtear5
; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
956 uint rowbar5
; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
958 uint rowar5
; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
959 uint rows1r5
; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
960 uint rows2r5
; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
961 uint rows3r5
; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
962 uint rowtar6
; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
963 uint rowtear6
; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
964 uint rowbar6
; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
966 uint rowar6
; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
967 uint rows1r6
; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
968 uint rows2r6
; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
969 uint rows3r6
; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
970 uint rowtar7
; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
971 uint rowtear7
; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
972 uint rowbar7
; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
974 uint rowar7
; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
975 uint rows1r7
; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
976 uint rows2r7
; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
977 uint rows3r7
; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
978 uint rowtar8
; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
979 uint rowtear8
; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
980 uint rowbar8
; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
982 uint rowar8
; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
983 uint rows1r8
; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
984 uint rows2r8
; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
985 uint rows3r8
; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
987 uint riwtar4
; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
988 uint riwbar4
; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
990 uint riwar4
; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
992 uint riwtar3
; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
994 uint riwbar3
; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
996 uint riwar3
; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
998 uint riwtar2
; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1000 uint riwbar2
; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1002 uint riwar2
; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1004 uint riwtar1
; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1006 uint riwbar1
; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1008 uint riwar1
; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1010 uint riwtar0
; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1012 uint riwar0
; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1014 uint pnfedr
; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1015 uint pnfedir
; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1016 uint pnfeier
; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1017 uint pecr
; /* 0xd0e0c - Port Error Control Register */
1018 uint pepcsr0
; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1019 uint pepr1
; /* 0xd0e14 - Port Error Packet Register 1 */
1020 uint pepr2
; /* 0xd0e18 - Port Error Packet Register 2 */
1022 uint predr
; /* 0xd0e20 - Port Recoverable Error Detect Register */
1024 uint pertr
; /* 0xd0e28 - Port Error Recovery Threshold Register */
1025 uint prtr
; /* 0xd0e2c - Port Retry Threshold Register */
1027 uint omr
; /* 0xd3000 - Outbound Mode Register */
1028 uint osr
; /* 0xd3004 - Outbound Status Register */
1029 uint eodqtpar
; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1030 uint odqtpar
; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
1031 uint eosar
; /* 0xd3010 - Extended Outbound Unit Source Address Register */
1032 uint osar
; /* 0xd3014 - Outbound Unit Source Address Register */
1033 uint odpr
; /* 0xd3018 - Outbound Destination Port Register */
1034 uint odatr
; /* 0xd301c - Outbound Destination Attributes Register */
1035 uint odcr
; /* 0xd3020 - Outbound Doubleword Count Register */
1036 uint eodqhpar
; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1037 uint odqhpar
; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
1038 uint oretr
; /* 0xd302C - Outbound Retry Error Threshold Register */
1039 uint omgr
; /* 0xd3030 - Outbound Multicast Group Register */
1040 uint omlr
; /* 0xd3034 - Outbound Multicast List Register */
1042 uint imr
; /* 0xd3060 - Outbound Mode Register */
1043 uint isr
; /* 0xd3064 - Inbound Status Register */
1044 uint eidqtpar
; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1045 uint idqtpar
; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
1046 uint eifqhpar
; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
1047 uint ifqhpar
; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
1048 uint imirir
; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
1050 uint oddmr
; /* 0xd3400 - Outbound Doorbell Mode Register */
1051 uint oddsr
; /* 0xd3404 - Outbound Doorbell Status Register */
1053 uint oddpr
; /* 0xd3418 - Outbound Doorbell Destination Port Register */
1054 uint oddatr
; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
1056 uint oddretr
; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
1058 uint idmr
; /* 0xd3460 - Inbound Doorbell Mode Register */
1059 uint idsr
; /* 0xd3464 - Inbound Doorbell Status Register */
1060 uint iedqtpar
; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
1061 uint iqtpar
; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
1062 uint iedqhpar
; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
1063 uint idqhpar
; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
1064 uint idmirir
; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
1066 uint pwmr
; /* 0xd34e0 - Port-Write Mode Register */
1067 uint pwsr
; /* 0xd34e4 - Port-Write Status Register */
1068 uint epwqbar
; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
1069 uint pwqbar
; /* 0xd34ec - Port-Write Queue Base Address Register */
1073 /* Global Utilities Register Block(0xe_0000-0xf_ffff) */
1074 typedef struct ccsr_gur
{
1075 uint porpllsr
; /* 0xe0000 - POR PLL ratio status register */
1076 uint porbmsr
; /* 0xe0004 - POR boot mode status register */
1077 uint porimpscr
; /* 0xe0008 - POR I/O impedance status and control register */
1078 uint pordevsr
; /* 0xe000c - POR I/O device status regsiter */
1079 uint pordbgmsr
; /* 0xe0010 - POR debug mode status register */
1081 uint gpporcr
; /* 0xe0020 - General-purpose POR configuration register */
1083 uint gpiocr
; /* 0xe0030 - GPIO control register */
1085 uint gpoutdr
; /* 0xe0040 - General-purpose output data register */
1087 uint gpindr
; /* 0xe0050 - General-purpose input data register */
1089 uint pmuxcr
; /* 0xe0060 - Alternate function signal multiplex control */
1091 uint devdisr
; /* 0xe0070 - Device disable control */
1093 uint powmgtcsr
; /* 0xe0080 - Power management status and control register */
1095 uint mcpsumr
; /* 0xe0090 - Machine check summary register */
1096 uint rstrscr
; /* 0xe0094 - Reset request status and control register */
1098 uint pvr
; /* 0xe00a0 - Processor version register */
1099 uint svr
; /* 0xe00a4 - System version register */
1101 uint rstcr
; /* 0xe00b0 - Reset control register */
1103 uint clkdvdr
; /* 0xe0800 - Clock Divide register */
1105 uint ddr1clkdr
; /* 0xe0b20 - DDRC1 Clock Disable register */
1107 uint ddr2clkdr
; /* 0xe0b28 - DDRC2 Clock Disable register */
1109 uint clkocr
; /* 0xe0e00 - Clock out select register */
1111 uint ddrdllcr
; /* 0xe0e10 - DDR DLL control register */
1113 uint lbcdllcr
; /* 0xe0e20 - LBC DLL control register */
1115 uint srds1cr0
; /* 0xe0f04 - SerDes1 control register 0 */
1117 uint srds1cr1
; /* 0xe0f08 - SerDes1 control register 1 */
1119 uint ddrioovcr
; /* 0xe0f24 - DDR IO Overdrive Control register */
1121 uint srds2cr0
; /* 0xe0f40 - SerDes2 control register 0 */
1122 uint srds2cr1
; /* 0xe0f44 - SerDes2 control register 1 */
1126 #define MPC8610_PORBMSR_HA 0x00070000
1127 #define MPC8610_PORBMSR_HA_SHIFT 16
1128 #define MPC8641_PORBMSR_HA 0x00060000
1129 #define MPC8641_PORBMSR_HA_SHIFT 17
1130 #define MPC8610_PORDEVSR_IO_SEL 0x00380000
1131 #define MPC8610_PORDEVSR_IO_SEL_SHIFT 19
1132 #define MPC8641_PORDEVSR_IO_SEL 0x000F0000
1133 #define MPC8641_PORDEVSR_IO_SEL_SHIFT 16
1134 #define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
1135 #define MPC86xx_DEVDISR_PCIEX1 0x80000000
1136 #define MPC86xx_DEVDISR_PCIEX2 0x40000000
1137 #define MPC86xx_DEVDISR_PCI1 0x80000000
1138 #define MPC86xx_DEVDISR_PCIE1 0x40000000
1139 #define MPC86xx_DEVDISR_PCIE2 0x20000000
1140 #define MPC86xx_DEVDISR_SRIO 0x00080000
1141 #define MPC86xx_DEVDISR_RMSG 0x00040000
1142 #define MPC86xx_DEVDISR_CPU0 0x00008000
1143 #define MPC86xx_DEVDISR_CPU1 0x00004000
1144 #define MPC86xx_RSTCR_HRST_REQ 0x00000002
1147 * Watchdog register block(0xe_4000-0xe_4fff)
1149 typedef struct ccsr_wdt
{
1151 uint swcrr
; /* System watchdog control register */
1152 uint swcnr
; /* System watchdog count register */
1154 ushort swsrr
; /* System watchdog service register */
1158 typedef struct immap
{
1159 ccsr_local_mcm_t im_local_mcm
;
1160 struct ccsr_ddr im_ddr1
;
1162 ccsr_duart_t im_duart
;
1164 struct ccsr_ddr im_ddr2
;
1172 ccsr_tsec_t im_tsec1
;
1173 ccsr_tsec_t im_tsec2
;
1174 ccsr_tsec_t im_tsec3
;
1175 ccsr_tsec_t im_tsec4
;
1185 extern immap_t
*immr
;
1187 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
1188 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
1189 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
1190 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
1191 #define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
1192 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
1193 #define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
1194 #define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
1197 #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
1198 #ifdef CONFIG_MPC8610
1199 #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
1201 #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
1203 #define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000
1205 #define CONFIG_SYS_PCI1_ADDR \
1206 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
1207 #define CONFIG_SYS_PCI2_ADDR \
1208 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
1209 #define CONFIG_SYS_PCIE1_ADDR \
1210 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
1211 #define CONFIG_SYS_PCIE2_ADDR \
1212 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
1214 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
1215 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
1216 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
1218 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
1219 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
1221 #endif /*__IMMAP_86xx__*/