arch/powerpc/kernel/exceptions-64s.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * This file contains the 64-bit "server" PowerPC variant
   4  * of the low level exception handling including exception
   5  * vectors, exception return, part of the slb and stab
   6  * handling and other fixed offset specific things.
   7  *
   8  * This file is meant to be #included from head_64.S due to
   9  * position dependent assembly.
  10  *
  11  * Most of this originates from head_64.S and thus has the same
  12  * copyright history.
  13  *
  14  */
  15
  16 #include <asm/hw_irq.h>
  17 #include <asm/exception-64s.h>
  18 #include <asm/ptrace.h>
  19 #include <asm/cpuidle.h>
  20 #include <asm/head-64.h>
  21
  22 /*
  23  * There are a few constraints to be concerned with.
  24  * - Real mode exceptions code/data must be located at their physical location.
  25  * - Virtual mode exceptions must be mapped at their 0xc000... location.
  26  * - Fixed location code must not call directly beyond the __end_interrupts
  27  *   area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
  28  *   must be used.
  29  * - LOAD_HANDLER targets must be within first 64K of physical 0 /
  30  *   virtual 0xc00...
  31  * - Conditional branch targets must be within +/-32K of caller.
  32  *
  33  * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
  34  * therefore don't have to run in physically located code or rfid to
  35  * virtual mode kernel code. However on relocatable kernels they do have
  36  * to branch to KERNELBASE offset because the rest of the kernel (outside
  37  * the exception vectors) may be located elsewhere.
  38  *
  39  * Virtual exceptions correspond with physical, except their entry points
  40  * are offset by 0xc000000000000000 and also tend to get an added 0x4000
  41  * offset applied. Virtual exceptions are enabled with the Alternate
  42  * Interrupt Location (AIL) bit set in the LPCR. However this does not
  43  * guarantee they will be delivered virtually. Some conditions (see the ISA)
  44  * cause exceptions to be delivered in real mode.
  45  *
  46  * It's impossible to receive interrupts below 0x300 via AIL.
  47  *
  48  * KVM: None of the virtual exceptions are from the guest. Anything that
  49  * escalated to HV=1 from HV=0 is delivered via real mode handlers.
  50  *
  51  *
  52  * We layout physical memory as follows:
  53  * 0x0000 - 0x00ff : Secondary processor spin code
  54  * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
  55  * 0x1900 - 0x3fff : Real mode trampolines
  56  * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
  57  * 0x5900 - 0x6fff : Relon mode trampolines
  58  * 0x7000 - 0x7fff : FWNMI data area
  59  * 0x8000 -   .... : Common interrupt handlers, remaining early
  60  *                   setup code, rest of kernel.
  61  *
  62  * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
  63  * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
  64  * vectors there.
  65  */
  66 OPEN_FIXED_SECTION(real_vectors,        0x0100, 0x1900)
  67 OPEN_FIXED_SECTION(real_trampolines,    0x1900, 0x4000)
  68 OPEN_FIXED_SECTION(virt_vectors,        0x4000, 0x5900)
  69 OPEN_FIXED_SECTION(virt_trampolines,    0x5900, 0x7000)
  70 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
  71 /*
  72  * Data area reserved for FWNMI option.
  73  * This address (0x7000) is fixed by the RPA.
  74  * pseries and powernv need to keep the whole page from
  75  * 0x7000 to 0x8000 free for use by the firmware
  76  */
  77 ZERO_FIXED_SECTION(fwnmi_page,          0x7000, 0x8000)
  78 OPEN_TEXT_SECTION(0x8000)
  79 #else
  80 OPEN_TEXT_SECTION(0x7000)
  81 #endif
  82
  83 USE_FIXED_SECTION(real_vectors)
  84
  85 /*
  86  * This is the start of the interrupt handlers for pSeries
  87  * This code runs with relocation off.
  88  * Code from here to __end_interrupts gets copied down to real
  89  * address 0x100 when we are running a relocatable kernel.
  90  * Therefore any relative branches in this section must only
  91  * branch to labels in this section.
  92  */
  93         .globl __start_interrupts
  94 __start_interrupts:
  95
  96 /* No virt vectors corresponding with 0x0..0x100 */
  97 EXC_VIRT_NONE(0x4000, 0x100)
  98
  99
 100 #ifdef CONFIG_PPC_P7_NAP
 101         /*
 102          * If running native on arch 2.06 or later, check if we are waking up
 103          * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
 104          * bits 46:47. A non-0 value indicates that we are coming from a power
 105          * saving state. The idle wakeup handler initially runs in real mode,
 106          * but we branch to the 0xc000... address so we can turn on relocation
 107          * with mtmsr.
 108          */
 109 #define IDLETEST(n)                                                     \
 110         BEGIN_FTR_SECTION ;                                             \
 111         mfspr   r10,SPRN_SRR1 ;                                         \
 112         rlwinm. r10,r10,47-31,30,31 ;                                   \
 113         beq-    1f ;                                                    \
 114         cmpwi   cr3,r10,2 ;                                             \
 115         BRANCH_TO_C000(r10, system_reset_idle_common) ;                 \
 116 1:                                                                      \
 117         END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 118 #else
 119 #define IDLETEST NOTEST
 120 #endif
 121
 122 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
 123         SET_SCRATCH0(r13)
 124         /*
 125          * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
 126          * being used, so a nested NMI exception would corrupt it.
 127          */
 128         EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
 129                                  IDLETEST, 0x100)
 130
 131 EXC_REAL_END(system_reset, 0x100, 0x100)
 132 EXC_VIRT_NONE(0x4100, 0x100)
 133
 134 #ifdef CONFIG_PPC_P7_NAP
 135 EXC_COMMON_BEGIN(system_reset_idle_common)
 136         mfspr   r12,SPRN_SRR1
 137         b       pnv_powersave_wakeup
 138 #endif
 139
 140 EXC_COMMON_BEGIN(system_reset_common)
 141         /*
 142          * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
 143          * to recover, but nested NMI will notice in_nmi and not recover
 144          * because of the use of the NMI stack. in_nmi reentrancy is tested in
 145          * system_reset_exception.
 146          */
 147         lhz     r10,PACA_IN_NMI(r13)
 148         addi    r10,r10,1
 149         sth     r10,PACA_IN_NMI(r13)
 150         li      r10,MSR_RI
 151         mtmsrd  r10,1
 152
 153         mr      r10,r1
 154         ld      r1,PACA_NMI_EMERG_SP(r13)
 155         subi    r1,r1,INT_FRAME_SIZE
 156         EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
 157                         system_reset, system_reset_exception,
 158                         ADD_NVGPRS;ADD_RECONCILE)
 159
 160         /*
 161          * The stack is no longer in use, decrement in_nmi.
 162          */
 163         lhz     r10,PACA_IN_NMI(r13)
 164         subi    r10,r10,1
 165         sth     r10,PACA_IN_NMI(r13)
 166
 167         b       ret_from_except
 168
 169 #ifdef CONFIG_PPC_PSERIES
 170 /*
 171  * Vectors for the FWNMI option.  Share common code.
 172  */
 173 TRAMP_REAL_BEGIN(system_reset_fwnmi)
 174         SET_SCRATCH0(r13)               /* save r13 */
 175         /* See comment at system_reset exception */
 176         EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
 177                                                 EXC_STD, NOTEST, 0x100)
 178 #endif /* CONFIG_PPC_PSERIES */
 179
 180
 181 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
 182         /* This is moved out of line as it can be patched by FW, but
 183          * some code path might still want to branch into the original
 184          * vector
 185          */
 186         SET_SCRATCH0(r13)               /* save r13 */
 187         EXCEPTION_PROLOG_0(PACA_EXMC)
 188 BEGIN_FTR_SECTION
 189         b       machine_check_powernv_early
 190 FTR_SECTION_ELSE
 191         b       machine_check_pSeries_0
 192 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 193 EXC_REAL_END(machine_check, 0x200, 0x100)
 194 EXC_VIRT_NONE(0x4200, 0x100)
 195 TRAMP_REAL_BEGIN(machine_check_powernv_early)
 196 BEGIN_FTR_SECTION
 197         EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
 198         /*
 199          * Register contents:
 200          * R13          = PACA
 201          * R9           = CR
 202          * Original R9 to R13 is saved on PACA_EXMC
 203          *
 204          * Switch to mc_emergency stack and handle re-entrancy (we limit
 205          * the nested MCE upto level 4 to avoid stack overflow).
 206          * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
 207          *
 208          * We use paca->in_mce to check whether this is the first entry or
 209          * nested machine check. We increment paca->in_mce to track nested
 210          * machine checks.
 211          *
 212          * If this is the first entry then set stack pointer to
 213          * paca->mc_emergency_sp, otherwise r1 is already pointing to
 214          * stack frame on mc_emergency stack.
 215          *
 216          * NOTE: We are here with MSR_ME=0 (off), which means we risk a
 217          * checkstop if we get another machine check exception before we do
 218          * rfid with MSR_ME=1.
 219          *
 220          * This interrupt can wake directly from idle. If that is the case,
 221          * the machine check is handled then the idle wakeup code is called
 222          * to restore state. In that case, the POWER9 DD1 idle PACA workaround
 223          * is not applied in the early machine check code, which will cause
 224          * bugs.
 225          */
 226         mr      r11,r1                  /* Save r1 */
 227         lhz     r10,PACA_IN_MCE(r13)
 228         cmpwi   r10,0                   /* Are we in nested machine check */
 229         bne     0f                      /* Yes, we are. */
 230         /* First machine check entry */
 231         ld      r1,PACAMCEMERGSP(r13)   /* Use MC emergency stack */
 232 0:      subi    r1,r1,INT_FRAME_SIZE    /* alloc stack frame */
 233         addi    r10,r10,1               /* increment paca->in_mce */
 234         sth     r10,PACA_IN_MCE(r13)
 235         /* Limit nested MCE to level 4 to avoid stack overflow */
 236         cmpwi   r10,4
 237         bgt     2f                      /* Check if we hit limit of 4 */
 238         std     r11,GPR1(r1)            /* Save r1 on the stack. */
 239         std     r11,0(r1)               /* make stack chain pointer */
 240         mfspr   r11,SPRN_SRR0           /* Save SRR0 */
 241         std     r11,_NIP(r1)
 242         mfspr   r11,SPRN_SRR1           /* Save SRR1 */
 243         std     r11,_MSR(r1)
 244         mfspr   r11,SPRN_DAR            /* Save DAR */
 245         std     r11,_DAR(r1)
 246         mfspr   r11,SPRN_DSISR          /* Save DSISR */
 247         std     r11,_DSISR(r1)
 248         std     r9,_CCR(r1)             /* Save CR in stackframe */
 249         /* Save r9 through r13 from EXMC save area to stack frame. */
 250         EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
 251         mfmsr   r11                     /* get MSR value */
 252         ori     r11,r11,MSR_ME          /* turn on ME bit */
 253         ori     r11,r11,MSR_RI          /* turn on RI bit */
 254         LOAD_HANDLER(r12, machine_check_handle_early)
 255 1:      mtspr   SPRN_SRR0,r12
 256         mtspr   SPRN_SRR1,r11
 257         rfid
 258         b       .       /* prevent speculative execution */
 259 2:
 260         /* Stack overflow. Stay on emergency stack and panic.
 261          * Keep the ME bit off while panic-ing, so that if we hit
 262          * another machine check we checkstop.
 263          */
 264         addi    r1,r1,INT_FRAME_SIZE    /* go back to previous stack frame */
 265         ld      r11,PACAKMSR(r13)
 266         LOAD_HANDLER(r12, unrecover_mce)
 267         li      r10,MSR_ME
 268         andc    r11,r11,r10             /* Turn off MSR_ME */
 269         b       1b
 270         b       .       /* prevent speculative execution */
 271 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 272
 273 TRAMP_REAL_BEGIN(machine_check_pSeries)
 274         .globl machine_check_fwnmi
 275 machine_check_fwnmi:
 276         SET_SCRATCH0(r13)               /* save r13 */
 277         EXCEPTION_PROLOG_0(PACA_EXMC)
 278 machine_check_pSeries_0:
 279         EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
 280         /*
 281          * MSR_RI is not enabled, because PACA_EXMC is being used, so a
 282          * nested machine check corrupts it. machine_check_common enables
 283          * MSR_RI.
 284          */
 285         EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
 286
 287 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
 288
 289 EXC_COMMON_BEGIN(machine_check_common)
 290         /*
 291          * Machine check is different because we use a different
 292          * save area: PACA_EXMC instead of PACA_EXGEN.
 293          */
 294         mfspr   r10,SPRN_DAR
 295         std     r10,PACA_EXMC+EX_DAR(r13)
 296         mfspr   r10,SPRN_DSISR
 297         stw     r10,PACA_EXMC+EX_DSISR(r13)
 298         EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
 299         FINISH_NAP
 300         RECONCILE_IRQ_STATE(r10, r11)
 301         ld      r3,PACA_EXMC+EX_DAR(r13)
 302         lwz     r4,PACA_EXMC+EX_DSISR(r13)
 303         /* Enable MSR_RI when finished with PACA_EXMC */
 304         li      r10,MSR_RI
 305         mtmsrd  r10,1
 306         std     r3,_DAR(r1)
 307         std     r4,_DSISR(r1)
 308         bl      save_nvgprs
 309         addi    r3,r1,STACK_FRAME_OVERHEAD
 310         bl      machine_check_exception
 311         b       ret_from_except
 312
 313 #define MACHINE_CHECK_HANDLER_WINDUP                    \
 314         /* Clear MSR_RI before setting SRR0 and SRR1. */\
 315         li      r0,MSR_RI;                              \
 316         mfmsr   r9;             /* get MSR value */     \
 317         andc    r9,r9,r0;                               \
 318         mtmsrd  r9,1;           /* Clear MSR_RI */      \
 319         /* Move original SRR0 and SRR1 into the respective regs */      \
 320         ld      r9,_MSR(r1);                            \
 321         mtspr   SPRN_SRR1,r9;                           \
 322         ld      r3,_NIP(r1);                            \
 323         mtspr   SPRN_SRR0,r3;                           \
 324         ld      r9,_CTR(r1);                            \
 325         mtctr   r9;                                     \
 326         ld      r9,_XER(r1);                            \
 327         mtxer   r9;                                     \
 328         ld      r9,_LINK(r1);                           \
 329         mtlr    r9;                                     \
 330         REST_GPR(0, r1);                                \
 331         REST_8GPRS(2, r1);                              \
 332         REST_GPR(10, r1);                               \
 333         ld      r11,_CCR(r1);                           \
 334         mtcr    r11;                                    \
 335         /* Decrement paca->in_mce. */                   \
 336         lhz     r12,PACA_IN_MCE(r13);                   \
 337         subi    r12,r12,1;                              \
 338         sth     r12,PACA_IN_MCE(r13);                   \
 339         REST_GPR(11, r1);                               \
 340         REST_2GPRS(12, r1);                             \
 341         /* restore original r1. */                      \
 342         ld      r1,GPR1(r1)
 343
 344 #ifdef CONFIG_PPC_P7_NAP
 345 /*
 346  * This is an idle wakeup. Low level machine check has already been
 347  * done. Queue the event then call the idle code to do the wake up.
 348  */
 349 EXC_COMMON_BEGIN(machine_check_idle_common)
 350         bl      machine_check_queue_event
 351
 352         /*
 353          * We have not used any non-volatile GPRs here, and as a rule
 354          * most exception code including machine check does not.
 355          * Therefore PACA_NAPSTATELOST does not need to be set. Idle
 356          * wakeup will restore volatile registers.
 357          *
 358          * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
 359          *
 360          * Then decrement MCE nesting after finishing with the stack.
 361          */
 362         ld      r3,_MSR(r1)
 363
 364         lhz     r11,PACA_IN_MCE(r13)
 365         subi    r11,r11,1
 366         sth     r11,PACA_IN_MCE(r13)
 367
 368         /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
 369         /* Recoverability could be improved by reducing the use of SRR1. */
 370         li      r11,0
 371         mtmsrd  r11,1
 372
 373         b       pnv_powersave_wakeup_mce
 374 #endif
 375         /*
 376          * Handle machine check early in real mode. We come here with
 377          * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
 378          */
 379 EXC_COMMON_BEGIN(machine_check_handle_early)
 380         std     r0,GPR0(r1)     /* Save r0 */
 381         EXCEPTION_PROLOG_COMMON_3(0x200)
 382         bl      save_nvgprs
 383         addi    r3,r1,STACK_FRAME_OVERHEAD
 384         bl      machine_check_early
 385         std     r3,RESULT(r1)   /* Save result */
 386         ld      r12,_MSR(r1)
 387
 388 #ifdef  CONFIG_PPC_P7_NAP
 389         /*
 390          * Check if thread was in power saving mode. We come here when any
 391          * of the following is true:
 392          * a. thread wasn't in power saving mode
 393          * b. thread was in power saving mode with no state loss,
 394          *    supervisor state loss or hypervisor state loss.
 395          *
 396          * Go back to nap/sleep/winkle mode again if (b) is true.
 397          */
 398         BEGIN_FTR_SECTION
 399         rlwinm. r11,r12,47-31,30,31
 400         bne     machine_check_idle_common
 401         END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 402 #endif
 403
 404         /*
 405          * Check if we are coming from hypervisor userspace. If yes then we
 406          * continue in host kernel in V mode to deliver the MC event.
 407          */
 408         rldicl. r11,r12,4,63            /* See if MC hit while in HV mode. */
 409         beq     5f
 410         andi.   r11,r12,MSR_PR          /* See if coming from user. */
 411         bne     9f                      /* continue in V mode if we are. */
 412
 413 5:
 414 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
 415         /*
 416          * We are coming from kernel context. Check if we are coming from
 417          * guest. if yes, then we can continue. We will fall through
 418          * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
 419          */
 420         lbz     r11,HSTATE_IN_GUEST(r13)
 421         cmpwi   r11,0                   /* Check if coming from guest */
 422         bne     9f                      /* continue if we are. */
 423 #endif
 424         /*
 425          * At this point we are not sure about what context we come from.
 426          * Queue up the MCE event and return from the interrupt.
 427          * But before that, check if this is an un-recoverable exception.
 428          * If yes, then stay on emergency stack and panic.
 429          */
 430         andi.   r11,r12,MSR_RI
 431         bne     2f
 432 1:      mfspr   r11,SPRN_SRR0
 433         LOAD_HANDLER(r10,unrecover_mce)
 434         mtspr   SPRN_SRR0,r10
 435         ld      r10,PACAKMSR(r13)
 436         /*
 437          * We are going down. But there are chances that we might get hit by
 438          * another MCE during panic path and we may run into unstable state
 439          * with no way out. Hence, turn ME bit off while going down, so that
 440          * when another MCE is hit during panic path, system will checkstop
 441          * and hypervisor will get restarted cleanly by SP.
 442          */
 443         li      r3,MSR_ME
 444         andc    r10,r10,r3              /* Turn off MSR_ME */
 445         mtspr   SPRN_SRR1,r10
 446         rfid
 447         b       .
 448 2:
 449         /*
 450          * Check if we have successfully handled/recovered from error, if not
 451          * then stay on emergency stack and panic.
 452          */
 453         ld      r3,RESULT(r1)   /* Load result */
 454         cmpdi   r3,0            /* see if we handled MCE successfully */
 455
 456         beq     1b              /* if !handled then panic */
 457         /*
 458          * Return from MC interrupt.
 459          * Queue up the MCE event so that we can log it later, while
 460          * returning from kernel or opal call.
 461          */
 462         bl      machine_check_queue_event
 463         MACHINE_CHECK_HANDLER_WINDUP
 464         rfid
 465 9:
 466         /* Deliver the machine check to host kernel in V mode. */
 467         MACHINE_CHECK_HANDLER_WINDUP
 468         b       machine_check_pSeries
 469
 470 EXC_COMMON_BEGIN(unrecover_mce)
 471         /* Invoke machine_check_exception to print MCE event and panic. */
 472         addi    r3,r1,STACK_FRAME_OVERHEAD
 473         bl      machine_check_exception
 474         /*
 475          * We will not reach here. Even if we did, there is no way out. Call
 476          * unrecoverable_exception and die.
 477          */
 478 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 479         bl      unrecoverable_exception
 480         b       1b
 481
 482
 483 EXC_REAL(data_access, 0x300, 0x80)
 484 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
 485 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
 486
 487 EXC_COMMON_BEGIN(data_access_common)
 488         /*
 489          * Here r13 points to the paca, r9 contains the saved CR,
 490          * SRR0 and SRR1 are saved in r11 and r12,
 491          * r9 - r13 are saved in paca->exgen.
 492          */
 493         mfspr   r10,SPRN_DAR
 494         std     r10,PACA_EXGEN+EX_DAR(r13)
 495         mfspr   r10,SPRN_DSISR
 496         stw     r10,PACA_EXGEN+EX_DSISR(r13)
 497         EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
 498         RECONCILE_IRQ_STATE(r10, r11)
 499         ld      r12,_MSR(r1)
 500         ld      r3,PACA_EXGEN+EX_DAR(r13)
 501         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
 502         li      r5,0x300
 503         std     r3,_DAR(r1)
 504         std     r4,_DSISR(r1)
 505 BEGIN_MMU_FTR_SECTION
 506         b       do_hash_page            /* Try to handle as hpte fault */
 507 MMU_FTR_SECTION_ELSE
 508         b       handle_page_fault
 509 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
 510
 511
 512 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
 513         SET_SCRATCH0(r13)
 514         EXCEPTION_PROLOG_0(PACA_EXSLB)
 515         EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
 516         mr      r12,r3  /* save r3 */
 517         mfspr   r3,SPRN_DAR
 518         mfspr   r11,SPRN_SRR1
 519         crset   4*cr6+eq
 520         BRANCH_TO_COMMON(r10, slb_miss_common)
 521 EXC_REAL_END(data_access_slb, 0x380, 0x80)
 522
 523 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
 524         SET_SCRATCH0(r13)
 525         EXCEPTION_PROLOG_0(PACA_EXSLB)
 526         EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
 527         mr      r12,r3  /* save r3 */
 528         mfspr   r3,SPRN_DAR
 529         mfspr   r11,SPRN_SRR1
 530         crset   4*cr6+eq
 531         BRANCH_TO_COMMON(r10, slb_miss_common)
 532 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
 533 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
 534
 535
 536 EXC_REAL(instruction_access, 0x400, 0x80)
 537 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
 538 TRAMP_KVM(PACA_EXGEN, 0x400)
 539
 540 EXC_COMMON_BEGIN(instruction_access_common)
 541         EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
 542         RECONCILE_IRQ_STATE(r10, r11)
 543         ld      r12,_MSR(r1)
 544         ld      r3,_NIP(r1)
 545         andis.  r4,r12,DSISR_BAD_FAULT_64S@h
 546         li      r5,0x400
 547         std     r3,_DAR(r1)
 548         std     r4,_DSISR(r1)
 549 BEGIN_MMU_FTR_SECTION
 550         b       do_hash_page            /* Try to handle as hpte fault */
 551 MMU_FTR_SECTION_ELSE
 552         b       handle_page_fault
 553 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
 554
 555
 556 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
 557         SET_SCRATCH0(r13)
 558         EXCEPTION_PROLOG_0(PACA_EXSLB)
 559         EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
 560         mr      r12,r3  /* save r3 */
 561         mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
 562         mfspr   r11,SPRN_SRR1
 563         crclr   4*cr6+eq
 564         BRANCH_TO_COMMON(r10, slb_miss_common)
 565 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
 566
 567 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
 568         SET_SCRATCH0(r13)
 569         EXCEPTION_PROLOG_0(PACA_EXSLB)
 570         EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
 571         mr      r12,r3  /* save r3 */
 572         mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
 573         mfspr   r11,SPRN_SRR1
 574         crclr   4*cr6+eq
 575         BRANCH_TO_COMMON(r10, slb_miss_common)
 576 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
 577 TRAMP_KVM(PACA_EXSLB, 0x480)
 578
 579
 580 /*
 581  * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as
 582  * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled.
 583  */
 584 EXC_COMMON_BEGIN(slb_miss_common)
 585         /*
 586          * r13 points to the PACA, r9 contains the saved CR,
 587          * r12 contains the saved r3,
 588          * r11 contain the saved SRR1, SRR0 is still ready for return
 589          * r3 has the faulting address
 590          * r9 - r13 are saved in paca->exslb.
 591          * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
 592          * We assume we aren't going to take any exceptions during this
 593          * procedure.
 594          */
 595         mflr    r10
 596         stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
 597         std     r10,PACA_EXSLB+EX_LR(r13)       /* save LR */
 598
 599         /*
 600          * Test MSR_RI before calling slb_allocate_realmode, because the
 601          * MSR in r11 gets clobbered. However we still want to allocate
 602          * SLB in case MSR_RI=0, to minimise the risk of getting stuck in
 603          * recursive SLB faults. So use cr5 for this, which is preserved.
 604          */
 605         andi.   r11,r11,MSR_RI  /* check for unrecoverable exception */
 606         cmpdi   cr5,r11,MSR_RI
 607
 608         crset   4*cr0+eq
 609 #ifdef CONFIG_PPC_STD_MMU_64
 610 BEGIN_MMU_FTR_SECTION
 611         bl      slb_allocate
 612 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
 613 #endif
 614
 615         ld      r10,PACA_EXSLB+EX_LR(r13)
 616         lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
 617         mtlr    r10
 618
 619         beq-    8f              /* if bad address, make full stack frame */
 620
 621         bne-    cr5,2f          /* if unrecoverable exception, oops */
 622
 623         /* All done -- return from exception. */
 624
 625 .machine        push
 626 .machine        "power4"
 627         mtcrf   0x80,r9
 628         mtcrf   0x04,r9         /* MSR[RI] indication is in cr5 */
 629         mtcrf   0x02,r9         /* I/D indication is in cr6 */
 630         mtcrf   0x01,r9         /* slb_allocate uses cr0 and cr7 */
 631 .machine        pop
 632
 633         RESTORE_CTR(r9, PACA_EXSLB)
 634         RESTORE_PPR_PACA(PACA_EXSLB, r9)
 635         mr      r3,r12
 636         ld      r9,PACA_EXSLB+EX_R9(r13)
 637         ld      r10,PACA_EXSLB+EX_R10(r13)
 638         ld      r11,PACA_EXSLB+EX_R11(r13)
 639         ld      r12,PACA_EXSLB+EX_R12(r13)
 640         ld      r13,PACA_EXSLB+EX_R13(r13)
 641         rfid
 642         b       .       /* prevent speculative execution */
 643
 644 2:      std     r3,PACA_EXSLB+EX_DAR(r13)
 645         mr      r3,r12
 646         mfspr   r11,SPRN_SRR0
 647         mfspr   r12,SPRN_SRR1
 648         LOAD_HANDLER(r10,unrecov_slb)
 649         mtspr   SPRN_SRR0,r10
 650         ld      r10,PACAKMSR(r13)
 651         mtspr   SPRN_SRR1,r10
 652         rfid
 653         b       .
 654
 655 8:      std     r3,PACA_EXSLB+EX_DAR(r13)
 656         mr      r3,r12
 657         mfspr   r11,SPRN_SRR0
 658         mfspr   r12,SPRN_SRR1
 659         LOAD_HANDLER(r10,bad_addr_slb)
 660         mtspr   SPRN_SRR0,r10
 661         ld      r10,PACAKMSR(r13)
 662         mtspr   SPRN_SRR1,r10
 663         rfid
 664         b       .
 665
 666 EXC_COMMON_BEGIN(unrecov_slb)
 667         EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
 668         RECONCILE_IRQ_STATE(r10, r11)
 669         bl      save_nvgprs
 670 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 671         bl      unrecoverable_exception
 672         b       1b
 673
 674 EXC_COMMON_BEGIN(bad_addr_slb)
 675         EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
 676         RECONCILE_IRQ_STATE(r10, r11)
 677         ld      r3, PACA_EXSLB+EX_DAR(r13)
 678         std     r3, _DAR(r1)
 679         beq     cr6, 2f
 680         li      r10, 0x480              /* fix trap number for I-SLB miss */
 681         std     r10, _TRAP(r1)
 682 2:      bl      save_nvgprs
 683         addi    r3, r1, STACK_FRAME_OVERHEAD
 684         bl      slb_miss_bad_addr
 685         b       ret_from_except
 686
 687 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
 688         .globl hardware_interrupt_hv;
 689 hardware_interrupt_hv:
 690         BEGIN_FTR_SECTION
 691                 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
 692                                             EXC_HV, SOFTEN_TEST_HV)
 693         FTR_SECTION_ELSE
 694                 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
 695                                             EXC_STD, SOFTEN_TEST_PR)
 696         ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 697 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
 698
 699 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
 700         .globl hardware_interrupt_relon_hv;
 701 hardware_interrupt_relon_hv:
 702         BEGIN_FTR_SECTION
 703                 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
 704         FTR_SECTION_ELSE
 705                 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
 706         ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 707 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
 708
 709 TRAMP_KVM(PACA_EXGEN, 0x500)
 710 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
 711 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
 712
 713
 714 EXC_REAL(alignment, 0x600, 0x100)
 715 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
 716 TRAMP_KVM(PACA_EXGEN, 0x600)
 717 EXC_COMMON_BEGIN(alignment_common)
 718         mfspr   r10,SPRN_DAR
 719         std     r10,PACA_EXGEN+EX_DAR(r13)
 720         mfspr   r10,SPRN_DSISR
 721         stw     r10,PACA_EXGEN+EX_DSISR(r13)
 722         EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
 723         ld      r3,PACA_EXGEN+EX_DAR(r13)
 724         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
 725         std     r3,_DAR(r1)
 726         std     r4,_DSISR(r1)
 727         bl      save_nvgprs
 728         RECONCILE_IRQ_STATE(r10, r11)
 729         addi    r3,r1,STACK_FRAME_OVERHEAD
 730         bl      alignment_exception
 731         b       ret_from_except
 732
 733
 734 EXC_REAL(program_check, 0x700, 0x100)
 735 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
 736 TRAMP_KVM(PACA_EXGEN, 0x700)
 737 EXC_COMMON_BEGIN(program_check_common)
 738         /*
 739          * It's possible to receive a TM Bad Thing type program check with
 740          * userspace register values (in particular r1), but with SRR1 reporting
 741          * that we came from the kernel. Normally that would confuse the bad
 742          * stack logic, and we would report a bad kernel stack pointer. Instead
 743          * we switch to the emergency stack if we're taking a TM Bad Thing from
 744          * the kernel.
 745          */
 746         li      r10,MSR_PR              /* Build a mask of MSR_PR ..    */
 747         oris    r10,r10,0x200000@h      /* .. and SRR1_PROGTM           */
 748         and     r10,r10,r12             /* Mask SRR1 with that.         */
 749         srdi    r10,r10,8               /* Shift it so we can compare   */
 750         cmpldi  r10,(0x200000 >> 8)     /* .. with an immediate.        */
 751         bne 1f                          /* If != go to normal path.     */
 752
 753         /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack  */
 754         andi.   r10,r12,MSR_PR;         /* Set CR0 correctly for label  */
 755                                         /* 3 in EXCEPTION_PROLOG_COMMON */
 756         mr      r10,r1                  /* Save r1                      */
 757         ld      r1,PACAEMERGSP(r13)     /* Use emergency stack          */
 758         subi    r1,r1,INT_FRAME_SIZE    /* alloc stack frame            */
 759         b 3f                            /* Jump into the macro !!       */
 760 1:      EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
 761         bl      save_nvgprs
 762         RECONCILE_IRQ_STATE(r10, r11)
 763         addi    r3,r1,STACK_FRAME_OVERHEAD
 764         bl      program_check_exception
 765         b       ret_from_except
 766
 767
 768 EXC_REAL(fp_unavailable, 0x800, 0x100)
 769 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
 770 TRAMP_KVM(PACA_EXGEN, 0x800)
 771 EXC_COMMON_BEGIN(fp_unavailable_common)
 772         EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
 773         bne     1f                      /* if from user, just load it up */
 774         bl      save_nvgprs
 775         RECONCILE_IRQ_STATE(r10, r11)
 776         addi    r3,r1,STACK_FRAME_OVERHEAD
 777         bl      kernel_fp_unavailable_exception
 778         BUG_OPCODE
 779 1:
 780 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 781 BEGIN_FTR_SECTION
 782         /* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
 783          * transaction), go do TM stuff
 784          */
 785         rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
 786         bne-    2f
 787 END_FTR_SECTION_IFSET(CPU_FTR_TM)
 788 #endif
 789         bl      load_up_fpu
 790         b       fast_exception_return
 791 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 792 2:      /* User process was in a transaction */
 793         bl      save_nvgprs
 794         RECONCILE_IRQ_STATE(r10, r11)
 795         addi    r3,r1,STACK_FRAME_OVERHEAD
 796         bl      fp_unavailable_tm
 797         b       ret_from_except
 798 #endif
 799
 800
 801 EXC_REAL_MASKABLE(decrementer, 0x900, 0x80)
 802 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900)
 803 TRAMP_KVM(PACA_EXGEN, 0x900)
 804 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
 805
 806
 807 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
 808 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
 809 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
 810 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
 811
 812
 813 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100)
 814 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00)
 815 TRAMP_KVM(PACA_EXGEN, 0xa00)
 816 #ifdef CONFIG_PPC_DOORBELL
 817 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
 818 #else
 819 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
 820 #endif
 821
 822
 823 EXC_REAL(trap_0b, 0xb00, 0x100)
 824 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
 825 TRAMP_KVM(PACA_EXGEN, 0xb00)
 826 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
 827
 828 /*
 829  * system call / hypercall (0xc00, 0x4c00)
 830  *
 831  * The system call exception is invoked with "sc 0" and does not alter HV bit.
 832  * There is support for kernel code to invoke system calls but there are no
 833  * in-tree users.
 834  *
 835  * The hypercall is invoked with "sc 1" and sets HV=1.
 836  *
 837  * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
 838  * 0x4c00 virtual mode.
 839  *
 840  * Call convention:
 841  *
 842  * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
 843  *
 844  * For hypercalls, the register convention is as follows:
 845  * r0 volatile
 846  * r1-2 nonvolatile
 847  * r3 volatile parameter and return value for status
 848  * r4-r10 volatile input and output value
 849  * r11 volatile hypercall number and output value
 850  * r12 volatile input and output value
 851  * r13-r31 nonvolatile
 852  * LR nonvolatile
 853  * CTR volatile
 854  * XER volatile
 855  * CR0-1 CR5-7 volatile
 856  * CR2-4 nonvolatile
 857  * Other registers nonvolatile
 858  *
 859  * The intersection of volatile registers that don't contain possible
 860  * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
 861  * without saving, though xer is not a good idea to use, as hardware may
 862  * interpret some bits so it may be costly to change them.
 863  */
 864 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
 865         /*
 866          * There is a little bit of juggling to get syscall and hcall
 867          * working well. Save r13 in ctr to avoid using SPRG scratch
 868          * register.
 869          *
 870          * Userspace syscalls have already saved the PPR, hcalls must save
 871          * it before setting HMT_MEDIUM.
 872          */
 873 #define SYSCALL_KVMTEST                                                 \
 874         mtctr   r13;                                                    \
 875         GET_PACA(r13);                                                  \
 876         std     r10,PACA_EXGEN+EX_R10(r13);                             \
 877         KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
 878         HMT_MEDIUM;                                                     \
 879         mfctr   r9;
 880
 881 #else
 882 #define SYSCALL_KVMTEST                                                 \
 883         HMT_MEDIUM;                                                     \
 884         mr      r9,r13;                                                 \
 885         GET_PACA(r13);
 886 #endif
 887
 888 #define LOAD_SYSCALL_HANDLER(reg)                                       \
 889         __LOAD_HANDLER(reg, system_call_common)
 890
 891 #define SYSCALL_FASTENDIAN_TEST                                 \
 892 BEGIN_FTR_SECTION                                               \
 893         cmpdi   r0,0x1ebe ;                                     \
 894         beq-    1f ;                                            \
 895 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)                          \
 896
 897 /*
 898  * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
 899  * and HMT_MEDIUM.
 900  */
 901 #define SYSCALL_REAL                                            \
 902         mfspr   r11,SPRN_SRR0 ;                                 \
 903         mfspr   r12,SPRN_SRR1 ;                                 \
 904         LOAD_SYSCALL_HANDLER(r10) ;                             \
 905         mtspr   SPRN_SRR0,r10 ;                                 \
 906         ld      r10,PACAKMSR(r13) ;                             \
 907         mtspr   SPRN_SRR1,r10 ;                                 \
 908         rfid ;                                                  \
 909         b       . ;     /* prevent speculative execution */
 910
 911 #define SYSCALL_FASTENDIAN                                      \
 912         /* Fast LE/BE switch system call */                     \
 913 1:      mfspr   r12,SPRN_SRR1 ;                                 \
 914         xori    r12,r12,MSR_LE ;                                \
 915         mtspr   SPRN_SRR1,r12 ;                                 \
 916         mr      r13,r9 ;                                        \
 917         rfid ;          /* return to userspace */               \
 918         b       . ;     /* prevent speculative execution */
 919
 920 #if defined(CONFIG_RELOCATABLE)
 921         /*
 922          * We can't branch directly so we do it via the CTR which
 923          * is volatile across system calls.
 924          */
 925 #define SYSCALL_VIRT                                            \
 926         LOAD_SYSCALL_HANDLER(r10) ;                             \
 927         mtctr   r10 ;                                           \
 928         mfspr   r11,SPRN_SRR0 ;                                 \
 929         mfspr   r12,SPRN_SRR1 ;                                 \
 930         li      r10,MSR_RI ;                                    \
 931         mtmsrd  r10,1 ;                                         \
 932         bctr ;
 933 #else
 934         /* We can branch directly */
 935 #define SYSCALL_VIRT                                            \
 936         mfspr   r11,SPRN_SRR0 ;                                 \
 937         mfspr   r12,SPRN_SRR1 ;                                 \
 938         li      r10,MSR_RI ;                                    \
 939         mtmsrd  r10,1 ;                 /* Set RI (EE=0) */     \
 940         b       system_call_common ;
 941 #endif
 942
 943 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
 944         SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
 945         SYSCALL_FASTENDIAN_TEST
 946         SYSCALL_REAL
 947         SYSCALL_FASTENDIAN
 948 EXC_REAL_END(system_call, 0xc00, 0x100)
 949
 950 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
 951         SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
 952         SYSCALL_FASTENDIAN_TEST
 953         SYSCALL_VIRT
 954         SYSCALL_FASTENDIAN
 955 EXC_VIRT_END(system_call, 0x4c00, 0x100)
 956
 957 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
 958         /*
 959          * This is a hcall, so register convention is as above, with these
 960          * differences:
 961          * r13 = PACA
 962          * ctr = orig r13
 963          * orig r10 saved in PACA
 964          */
 965 TRAMP_KVM_BEGIN(do_kvm_0xc00)
 966          /*
 967           * Save the PPR (on systems that support it) before changing to
 968           * HMT_MEDIUM. That allows the KVM code to save that value into the
 969           * guest state (it is the guest's PPR value).
 970           */
 971         OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
 972         HMT_MEDIUM
 973         OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
 974         mfctr   r10
 975         SET_SCRATCH0(r10)
 976         std     r9,PACA_EXGEN+EX_R9(r13)
 977         mfcr    r9
 978         KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
 979 #endif
 980
 981
 982 EXC_REAL(single_step, 0xd00, 0x100)
 983 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
 984 TRAMP_KVM(PACA_EXGEN, 0xd00)
 985 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
 986
 987 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
 988 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
 989 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
 990 EXC_COMMON_BEGIN(h_data_storage_common)
 991         mfspr   r10,SPRN_HDAR
 992         std     r10,PACA_EXGEN+EX_DAR(r13)
 993         mfspr   r10,SPRN_HDSISR
 994         stw     r10,PACA_EXGEN+EX_DSISR(r13)
 995         EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
 996         bl      save_nvgprs
 997         RECONCILE_IRQ_STATE(r10, r11)
 998         addi    r3,r1,STACK_FRAME_OVERHEAD
 999         bl      unknown_exception
1000         b       ret_from_except
1001
1002
1003 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1004 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1005 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1006 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1007
1008
1009 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1010 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1011 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1012 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1013
1014
1015 /*
1016  * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1017  * first, and then eventaully from there to the trampoline to get into virtual
1018  * mode.
1019  */
1020 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1021 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
1022 EXC_VIRT_NONE(0x4e60, 0x20)
1023 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1024 TRAMP_REAL_BEGIN(hmi_exception_early)
1025         EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1026         mr      r10,r1                  /* Save r1 */
1027         ld      r1,PACAEMERGSP(r13)     /* Use emergency stack for realmode */
1028         subi    r1,r1,INT_FRAME_SIZE    /* alloc stack frame            */
1029         mfspr   r11,SPRN_HSRR0          /* Save HSRR0 */
1030         mfspr   r12,SPRN_HSRR1          /* Save HSRR1 */
1031         EXCEPTION_PROLOG_COMMON_1()
1032         EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1033         EXCEPTION_PROLOG_COMMON_3(0xe60)
1034         addi    r3,r1,STACK_FRAME_OVERHEAD
1035         BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
1036         /* Windup the stack. */
1037         /* Move original HSRR0 and HSRR1 into the respective regs */
1038         ld      r9,_MSR(r1)
1039         mtspr   SPRN_HSRR1,r9
1040         ld      r3,_NIP(r1)
1041         mtspr   SPRN_HSRR0,r3
1042         ld      r9,_CTR(r1)
1043         mtctr   r9
1044         ld      r9,_XER(r1)
1045         mtxer   r9
1046         ld      r9,_LINK(r1)
1047         mtlr    r9
1048         REST_GPR(0, r1)
1049         REST_8GPRS(2, r1)
1050         REST_GPR(10, r1)
1051         ld      r11,_CCR(r1)
1052         mtcr    r11
1053         REST_GPR(11, r1)
1054         REST_2GPRS(12, r1)
1055         /* restore original r1. */
1056         ld      r1,GPR1(r1)
1057
1058         /*
1059          * Go to virtual mode and pull the HMI event information from
1060          * firmware.
1061          */
1062         .globl hmi_exception_after_realmode
1063 hmi_exception_after_realmode:
1064         SET_SCRATCH0(r13)
1065         EXCEPTION_PROLOG_0(PACA_EXGEN)
1066         b       tramp_real_hmi_exception
1067
1068 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1069
1070
1071 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20)
1072 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80)
1073 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1074 #ifdef CONFIG_PPC_DOORBELL
1075 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1076 #else
1077 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1078 #endif
1079
1080
1081 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20)
1082 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0)
1083 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1084 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1085
1086
1087 EXC_REAL_NONE(0xec0, 0x20)
1088 EXC_VIRT_NONE(0x4ec0, 0x20)
1089 EXC_REAL_NONE(0xee0, 0x20)
1090 EXC_VIRT_NONE(0x4ee0, 0x20)
1091
1092
1093 EXC_REAL_OOL(performance_monitor, 0xf00, 0x20)
1094 EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00)
1095 TRAMP_KVM(PACA_EXGEN, 0xf00)
1096 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1097
1098
1099 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1100 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1101 TRAMP_KVM(PACA_EXGEN, 0xf20)
1102 EXC_COMMON_BEGIN(altivec_unavailable_common)
1103         EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1104 #ifdef CONFIG_ALTIVEC
1105 BEGIN_FTR_SECTION
1106         beq     1f
1107 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1108   BEGIN_FTR_SECTION_NESTED(69)
1109         /* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1110          * transaction), go do TM stuff
1111          */
1112         rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1113         bne-    2f
1114   END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1115 #endif
1116         bl      load_up_altivec
1117         b       fast_exception_return
1118 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1119 2:      /* User process was in a transaction */
1120         bl      save_nvgprs
1121         RECONCILE_IRQ_STATE(r10, r11)
1122         addi    r3,r1,STACK_FRAME_OVERHEAD
1123         bl      altivec_unavailable_tm
1124         b       ret_from_except
1125 #endif
1126 1:
1127 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1128 #endif
1129         bl      save_nvgprs
1130         RECONCILE_IRQ_STATE(r10, r11)
1131         addi    r3,r1,STACK_FRAME_OVERHEAD
1132         bl      altivec_unavailable_exception
1133         b       ret_from_except
1134
1135
1136 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1137 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1138 TRAMP_KVM(PACA_EXGEN, 0xf40)
1139 EXC_COMMON_BEGIN(vsx_unavailable_common)
1140         EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1141 #ifdef CONFIG_VSX
1142 BEGIN_FTR_SECTION
1143         beq     1f
1144 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1145   BEGIN_FTR_SECTION_NESTED(69)
1146         /* Test if 2 TM state bits are zero.  If non-zero (ie. userspace was in
1147          * transaction), go do TM stuff
1148          */
1149         rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1150         bne-    2f
1151   END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1152 #endif
1153         b       load_up_vsx
1154 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1155 2:      /* User process was in a transaction */
1156         bl      save_nvgprs
1157         RECONCILE_IRQ_STATE(r10, r11)
1158         addi    r3,r1,STACK_FRAME_OVERHEAD
1159         bl      vsx_unavailable_tm
1160         b       ret_from_except
1161 #endif
1162 1:
1163 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1164 #endif
1165         bl      save_nvgprs
1166         RECONCILE_IRQ_STATE(r10, r11)
1167         addi    r3,r1,STACK_FRAME_OVERHEAD
1168         bl      vsx_unavailable_exception
1169         b       ret_from_except
1170
1171
1172 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1173 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1174 TRAMP_KVM(PACA_EXGEN, 0xf60)
1175 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1176
1177
1178 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1179 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1180 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1181 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1182
1183
1184 EXC_REAL_NONE(0xfa0, 0x20)
1185 EXC_VIRT_NONE(0x4fa0, 0x20)
1186 EXC_REAL_NONE(0xfc0, 0x20)
1187 EXC_VIRT_NONE(0x4fc0, 0x20)
1188 EXC_REAL_NONE(0xfe0, 0x20)
1189 EXC_VIRT_NONE(0x4fe0, 0x20)
1190
1191 EXC_REAL_NONE(0x1000, 0x100)
1192 EXC_VIRT_NONE(0x5000, 0x100)
1193 EXC_REAL_NONE(0x1100, 0x100)
1194 EXC_VIRT_NONE(0x5100, 0x100)
1195
1196 #ifdef CONFIG_CBE_RAS
1197 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1198 EXC_VIRT_NONE(0x5200, 0x100)
1199 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1200 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1201 #else /* CONFIG_CBE_RAS */
1202 EXC_REAL_NONE(0x1200, 0x100)
1203 EXC_VIRT_NONE(0x5200, 0x100)
1204 #endif
1205
1206
1207 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1208 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1209 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1210 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1211
1212 EXC_REAL_NONE(0x1400, 0x100)
1213 EXC_VIRT_NONE(0x5400, 0x100)
1214
1215 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1216         mtspr   SPRN_SPRG_HSCRATCH0,r13
1217         EXCEPTION_PROLOG_0(PACA_EXGEN)
1218         EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1219
1220 #ifdef CONFIG_PPC_DENORMALISATION
1221         mfspr   r10,SPRN_HSRR1
1222         mfspr   r11,SPRN_HSRR0          /* save HSRR0 */
1223         andis.  r10,r10,(HSRR1_DENORM)@h /* denorm? */
1224         addi    r11,r11,-4              /* HSRR0 is next instruction */
1225         bne+    denorm_assist
1226 #endif
1227
1228         KVMTEST_PR(0x1500)
1229         EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1230 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1231
1232 #ifdef CONFIG_PPC_DENORMALISATION
1233 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1234         b       exc_real_0x1500_denorm_exception_hv
1235 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1236 #else
1237 EXC_VIRT_NONE(0x5500, 0x100)
1238 #endif
1239
1240 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1241
1242 #ifdef CONFIG_PPC_DENORMALISATION
1243 TRAMP_REAL_BEGIN(denorm_assist)
1244 BEGIN_FTR_SECTION
1245 /*
1246  * To denormalise we need to move a copy of the register to itself.
1247  * For POWER6 do that here for all FP regs.
1248  */
1249         mfmsr   r10
1250         ori     r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1251         xori    r10,r10,(MSR_FE0|MSR_FE1)
1252         mtmsrd  r10
1253         sync
1254
1255 #define FMR2(n)  fmr (n), (n) ; fmr n+1, n+1
1256 #define FMR4(n)  FMR2(n) ; FMR2(n+2)
1257 #define FMR8(n)  FMR4(n) ; FMR4(n+4)
1258 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1259 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1260         FMR32(0)
1261
1262 FTR_SECTION_ELSE
1263 /*
1264  * To denormalise we need to move a copy of the register to itself.
1265  * For POWER7 do that here for the first 32 VSX registers only.
1266  */
1267         mfmsr   r10
1268         oris    r10,r10,MSR_VSX@h
1269         mtmsrd  r10
1270         sync
1271
1272 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1273 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1274 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1275 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1276 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1277         XVCPSGNDP32(0)
1278
1279 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1280
1281 BEGIN_FTR_SECTION
1282         b       denorm_done
1283 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1284 /*
1285  * To denormalise we need to move a copy of the register to itself.
1286  * For POWER8 we need to do that for all 64 VSX registers
1287  */
1288         XVCPSGNDP32(32)
1289 denorm_done:
1290         mtspr   SPRN_HSRR0,r11
1291         mtcrf   0x80,r9
1292         ld      r9,PACA_EXGEN+EX_R9(r13)
1293         RESTORE_PPR_PACA(PACA_EXGEN, r10)
1294 BEGIN_FTR_SECTION
1295         ld      r10,PACA_EXGEN+EX_CFAR(r13)
1296         mtspr   SPRN_CFAR,r10
1297 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1298         ld      r10,PACA_EXGEN+EX_R10(r13)
1299         ld      r11,PACA_EXGEN+EX_R11(r13)
1300         ld      r12,PACA_EXGEN+EX_R12(r13)
1301         ld      r13,PACA_EXGEN+EX_R13(r13)
1302         HRFID
1303         b       .
1304 #endif
1305
1306 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1307
1308
1309 #ifdef CONFIG_CBE_RAS
1310 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1311 EXC_VIRT_NONE(0x5600, 0x100)
1312 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1313 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1314 #else /* CONFIG_CBE_RAS */
1315 EXC_REAL_NONE(0x1600, 0x100)
1316 EXC_VIRT_NONE(0x5600, 0x100)
1317 #endif
1318
1319
1320 EXC_REAL(altivec_assist, 0x1700, 0x100)
1321 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1322 TRAMP_KVM(PACA_EXGEN, 0x1700)
1323 #ifdef CONFIG_ALTIVEC
1324 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1325 #else
1326 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1327 #endif
1328
1329
1330 #ifdef CONFIG_CBE_RAS
1331 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1332 EXC_VIRT_NONE(0x5800, 0x100)
1333 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1334 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1335 #else /* CONFIG_CBE_RAS */
1336 EXC_REAL_NONE(0x1800, 0x100)
1337 EXC_VIRT_NONE(0x5800, 0x100)
1338 #endif
1339
1340 #ifdef CONFIG_PPC_WATCHDOG
1341
1342 #define MASKED_DEC_HANDLER_LABEL 3f
1343
1344 #define MASKED_DEC_HANDLER(_H)                          \
1345 3: /* soft-nmi */                                       \
1346         std     r12,PACA_EXGEN+EX_R12(r13);             \
1347         GET_SCRATCH0(r10);                              \
1348         std     r10,PACA_EXGEN+EX_R13(r13);             \
1349         EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H)
1350
1351 /*
1352  * Branch to soft_nmi_interrupt using the emergency stack. The emergency
1353  * stack is one that is usable by maskable interrupts so long as MSR_EE
1354  * remains off. It is used for recovery when something has corrupted the
1355  * normal kernel stack, for example. The "soft NMI" must not use the process
1356  * stack because we want irq disabled sections to avoid touching the stack
1357  * at all (other than PMU interrupts), so use the emergency stack for this,
1358  * and run it entirely with interrupts hard disabled.
1359  */
1360 EXC_COMMON_BEGIN(soft_nmi_common)
1361         mr      r10,r1
1362         ld      r1,PACAEMERGSP(r13)
1363         subi    r1,r1,INT_FRAME_SIZE
1364         EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900,
1365                         system_reset, soft_nmi_interrupt,
1366                         ADD_NVGPRS;ADD_RECONCILE)
1367         b       ret_from_except
1368
1369 #else /* CONFIG_PPC_WATCHDOG */
1370 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1371 #define MASKED_DEC_HANDLER(_H)
1372 #endif /* CONFIG_PPC_WATCHDOG */
1373
1374 /*
1375  * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1376  * - If it was a decrementer interrupt, we bump the dec to max and and return.
1377  * - If it was a doorbell we return immediately since doorbells are edge
1378  *   triggered and won't automatically refire.
1379  * - If it was a HMI we return immediately since we handled it in realmode
1380  *   and it won't refire.
1381  * - else we hard disable and return.
1382  * This is called with r10 containing the value to OR to the paca field.
1383  */
1384 #define MASKED_INTERRUPT(_H)                            \
1385 masked_##_H##interrupt:                                 \
1386         std     r11,PACA_EXGEN+EX_R11(r13);             \
1387         lbz     r11,PACAIRQHAPPENED(r13);               \
1388         or      r11,r11,r10;                            \
1389         stb     r11,PACAIRQHAPPENED(r13);               \
1390         cmpwi   r10,PACA_IRQ_DEC;                       \
1391         bne     1f;                                     \
1392         lis     r10,0x7fff;                             \
1393         ori     r10,r10,0xffff;                         \
1394         mtspr   SPRN_DEC,r10;                           \
1395         b       MASKED_DEC_HANDLER_LABEL;               \
1396 1:      andi.   r10,r10,(PACA_IRQ_DBELL|PACA_IRQ_HMI);  \
1397         bne     2f;                                     \
1398         mfspr   r10,SPRN_##_H##SRR1;                    \
1399         xori    r10,r10,MSR_EE; /* clear MSR_EE */      \
1400         mtspr   SPRN_##_H##SRR1,r10;                    \
1401 2:      mtcrf   0x80,r9;                                \
1402         ld      r9,PACA_EXGEN+EX_R9(r13);               \
1403         ld      r10,PACA_EXGEN+EX_R10(r13);             \
1404         ld      r11,PACA_EXGEN+EX_R11(r13);             \
1405         /* returns to kernel where r13 must be set up, so don't restore it */ \
1406         ##_H##rfid;                                     \
1407         b       .;                                      \
1408         MASKED_DEC_HANDLER(_H)
1409
1410 /*
1411  * Real mode exceptions actually use this too, but alternate
1412  * instruction code patches (which end up in the common .text area)
1413  * cannot reach these if they are put there.
1414  */
1415 USE_FIXED_SECTION(virt_trampolines)
1416         MASKED_INTERRUPT()
1417         MASKED_INTERRUPT(H)
1418
1419 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1420 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1421         /*
1422          * Here all GPRs are unchanged from when the interrupt happened
1423          * except for r13, which is saved in SPRG_SCRATCH0.
1424          */
1425         mfspr   r13, SPRN_SRR0
1426         addi    r13, r13, 4
1427         mtspr   SPRN_SRR0, r13
1428         GET_SCRATCH0(r13)
1429         rfid
1430         b       .
1431
1432 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1433         /*
1434          * Here all GPRs are unchanged from when the interrupt happened
1435          * except for r13, which is saved in SPRG_SCRATCH0.
1436          */
1437         mfspr   r13, SPRN_HSRR0
1438         addi    r13, r13, 4
1439         mtspr   SPRN_HSRR0, r13
1440         GET_SCRATCH0(r13)
1441         hrfid
1442         b       .
1443 #endif
1444
1445 /*
1446  * Ensure that any handlers that get invoked from the exception prologs
1447  * above are below the first 64KB (0x10000) of the kernel image because
1448  * the prologs assemble the addresses of these handlers using the
1449  * LOAD_HANDLER macro, which uses an ori instruction.
1450  */
1451
1452 /*** Common interrupt handlers ***/
1453
1454
1455         /*
1456          * Relocation-on interrupts: A subset of the interrupts can be delivered
1457          * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1458          * it.  Addresses are the same as the original interrupt addresses, but
1459          * offset by 0xc000000000004000.
1460          * It's impossible to receive interrupts below 0x300 via this mechanism.
1461          * KVM: None of these traps are from the guest ; anything that escalated
1462          * to HV=1 from HV=0 is delivered via real mode handlers.
1463          */
1464
1465         /*
1466          * This uses the standard macro, since the original 0x300 vector
1467          * only has extra guff for STAB-based processors -- which never
1468          * come here.
1469          */
1470
1471 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1472         b       __ppc64_runlatch_on
1473
1474 USE_FIXED_SECTION(virt_trampolines)
1475         /*
1476          * The __end_interrupts marker must be past the out-of-line (OOL)
1477          * handlers, so that they are copied to real address 0x100 when running
1478          * a relocatable kernel. This ensures they can be reached from the short
1479          * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1480          * directly, without using LOAD_HANDLER().
1481          */
1482         .align  7
1483         .globl  __end_interrupts
1484 __end_interrupts:
1485 DEFINE_FIXED_SYMBOL(__end_interrupts)
1486
1487 #ifdef CONFIG_PPC_970_NAP
1488 EXC_COMMON_BEGIN(power4_fixup_nap)
1489         andc    r9,r9,r10
1490         std     r9,TI_LOCAL_FLAGS(r11)
1491         ld      r10,_LINK(r1)           /* make idle task do the */
1492         std     r10,_NIP(r1)            /* equivalent of a blr */
1493         blr
1494 #endif
1495
1496 CLOSE_FIXED_SECTION(real_vectors);
1497 CLOSE_FIXED_SECTION(real_trampolines);
1498 CLOSE_FIXED_SECTION(virt_vectors);
1499 CLOSE_FIXED_SECTION(virt_trampolines);
1500
1501 USE_TEXT_SECTION()
1502
1503 /*
1504  * Hash table stuff
1505  */
1506         .balign IFETCH_ALIGN_BYTES
1507 do_hash_page:
1508         #ifdef CONFIG_PPC_STD_MMU_64
1509         lis     r0,DSISR_BAD_FAULT_64S@h
1510         ori     r0,r0,DSISR_BAD_FAULT_64S@l
1511         and.    r0,r4,r0                /* weird error? */
1512         bne-    handle_page_fault       /* if not, try to insert a HPTE */
1513         CURRENT_THREAD_INFO(r11, r1)
1514         lwz     r0,TI_PREEMPT(r11)      /* If we're in an "NMI" */
1515         andis.  r0,r0,NMI_MASK@h        /* (i.e. an irq when soft-disabled) */
1516         bne     77f                     /* then don't call hash_page now */
1517
1518         /*
1519          * r3 contains the faulting address
1520          * r4 msr
1521          * r5 contains the trap number
1522          * r6 contains dsisr
1523          *
1524          * at return r3 = 0 for success, 1 for page fault, negative for error
1525          */
1526         mr      r4,r12
1527         ld      r6,_DSISR(r1)
1528         bl      __hash_page             /* build HPTE if possible */
1529         cmpdi   r3,0                    /* see if __hash_page succeeded */
1530
1531         /* Success */
1532         beq     fast_exc_return_irq     /* Return from exception on success */
1533
1534         /* Error */
1535         blt-    13f
1536
1537         /* Reload DSISR into r4 for the DABR check below */
1538         ld      r4,_DSISR(r1)
1539 #endif /* CONFIG_PPC_STD_MMU_64 */
1540
1541 /* Here we have a page fault that hash_page can't handle. */
1542 handle_page_fault:
1543 11:     andis.  r0,r4,DSISR_DABRMATCH@h
1544         bne-    handle_dabr_fault
1545         ld      r4,_DAR(r1)
1546         ld      r5,_DSISR(r1)
1547         addi    r3,r1,STACK_FRAME_OVERHEAD
1548         bl      do_page_fault
1549         cmpdi   r3,0
1550         beq+    12f
1551         bl      save_nvgprs
1552         mr      r5,r3
1553         addi    r3,r1,STACK_FRAME_OVERHEAD
1554         lwz     r4,_DAR(r1)
1555         bl      bad_page_fault
1556         b       ret_from_except
1557
1558 /* We have a data breakpoint exception - handle it */
1559 handle_dabr_fault:
1560         bl      save_nvgprs
1561         ld      r4,_DAR(r1)
1562         ld      r5,_DSISR(r1)
1563         addi    r3,r1,STACK_FRAME_OVERHEAD
1564         bl      do_break
1565 12:     b       ret_from_except_lite
1566
1567
1568 #ifdef CONFIG_PPC_STD_MMU_64
1569 /* We have a page fault that hash_page could handle but HV refused
1570  * the PTE insertion
1571  */
1572 13:     bl      save_nvgprs
1573         mr      r5,r3
1574         addi    r3,r1,STACK_FRAME_OVERHEAD
1575         ld      r4,_DAR(r1)
1576         bl      low_hash_fault
1577         b       ret_from_except
1578 #endif
1579
1580 /*
1581  * We come here as a result of a DSI at a point where we don't want
1582  * to call hash_page, such as when we are accessing memory (possibly
1583  * user memory) inside a PMU interrupt that occurred while interrupts
1584  * were soft-disabled.  We want to invoke the exception handler for
1585  * the access, or panic if there isn't a handler.
1586  */
1587 77:     bl      save_nvgprs
1588         mr      r4,r3
1589         addi    r3,r1,STACK_FRAME_OVERHEAD
1590         li      r5,SIGSEGV
1591         bl      bad_page_fault
1592         b       ret_from_except
1593
1594 /*
1595  * Here we have detected that the kernel stack pointer is bad.
1596  * R9 contains the saved CR, r13 points to the paca,
1597  * r10 contains the (bad) kernel stack pointer,
1598  * r11 and r12 contain the saved SRR0 and SRR1.
1599  * We switch to using an emergency stack, save the registers there,
1600  * and call kernel_bad_stack(), which panics.
1601  */
1602 bad_stack:
1603         ld      r1,PACAEMERGSP(r13)
1604         subi    r1,r1,64+INT_FRAME_SIZE
1605         std     r9,_CCR(r1)
1606         std     r10,GPR1(r1)
1607         std     r11,_NIP(r1)
1608         std     r12,_MSR(r1)
1609         mfspr   r11,SPRN_DAR
1610         mfspr   r12,SPRN_DSISR
1611         std     r11,_DAR(r1)
1612         std     r12,_DSISR(r1)
1613         mflr    r10
1614         mfctr   r11
1615         mfxer   r12
1616         std     r10,_LINK(r1)
1617         std     r11,_CTR(r1)
1618         std     r12,_XER(r1)
1619         SAVE_GPR(0,r1)
1620         SAVE_GPR(2,r1)
1621         ld      r10,EX_R3(r3)
1622         std     r10,GPR3(r1)
1623         SAVE_GPR(4,r1)
1624         SAVE_4GPRS(5,r1)
1625         ld      r9,EX_R9(r3)
1626         ld      r10,EX_R10(r3)
1627         SAVE_2GPRS(9,r1)
1628         ld      r9,EX_R11(r3)
1629         ld      r10,EX_R12(r3)
1630         ld      r11,EX_R13(r3)
1631         std     r9,GPR11(r1)
1632         std     r10,GPR12(r1)
1633         std     r11,GPR13(r1)
1634 BEGIN_FTR_SECTION
1635         ld      r10,EX_CFAR(r3)
1636         std     r10,ORIG_GPR3(r1)
1637 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1638         SAVE_8GPRS(14,r1)
1639         SAVE_10GPRS(22,r1)
1640         lhz     r12,PACA_TRAP_SAVE(r13)
1641         std     r12,_TRAP(r1)
1642         addi    r11,r1,INT_FRAME_SIZE
1643         std     r11,0(r1)
1644         li      r12,0
1645         std     r12,0(r11)
1646         ld      r2,PACATOC(r13)
1647         ld      r11,exception_marker@toc(r2)
1648         std     r12,RESULT(r1)
1649         std     r11,STACK_FRAME_OVERHEAD-16(r1)
1650 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1651         bl      kernel_bad_stack
1652         b       1b
1653 _ASM_NOKPROBE_SYMBOL(bad_stack);
1654
1655 /*
1656  * When doorbell is triggered from system reset wakeup, the message is
1657  * not cleared, so it would fire again when EE is enabled.
1658  *
1659  * When coming from local_irq_enable, there may be the same problem if
1660  * we were hard disabled.
1661  *
1662  * Execute msgclr to clear pending exceptions before handling it.
1663  */
1664 h_doorbell_common_msgclr:
1665         LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1666         PPC_MSGCLR(3)
1667         b       h_doorbell_common
1668
1669 doorbell_super_common_msgclr:
1670         LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1671         PPC_MSGCLRP(3)
1672         b       doorbell_super_common
1673
1674 /*
1675  * Called from arch_local_irq_enable when an interrupt needs
1676  * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1677  * which kind of interrupt. MSR:EE is already off. We generate a
1678  * stackframe like if a real interrupt had happened.
1679  *
1680  * Note: While MSR:EE is off, we need to make sure that _MSR
1681  * in the generated frame has EE set to 1 or the exception
1682  * handler will not properly re-enable them.
1683  *
1684  * Note that we don't specify LR as the NIP (return address) for
1685  * the interrupt because that would unbalance the return branch
1686  * predictor.
1687  */
1688 _GLOBAL(__replay_interrupt)
1689         /* We are going to jump to the exception common code which
1690          * will retrieve various register values from the PACA which
1691          * we don't give a damn about, so we don't bother storing them.
1692          */
1693         mfmsr   r12
1694         LOAD_REG_ADDR(r11, replay_interrupt_return)
1695         mfcr    r9
1696         ori     r12,r12,MSR_EE
1697         cmpwi   r3,0x900
1698         beq     decrementer_common
1699         cmpwi   r3,0x500
1700 BEGIN_FTR_SECTION
1701         beq     h_virt_irq_common
1702 FTR_SECTION_ELSE
1703         beq     hardware_interrupt_common
1704 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
1705 BEGIN_FTR_SECTION
1706         cmpwi   r3,0xa00
1707         beq     h_doorbell_common_msgclr
1708         cmpwi   r3,0xe60
1709         beq     hmi_exception_common
1710 FTR_SECTION_ELSE
1711         cmpwi   r3,0xa00
1712         beq     doorbell_super_common_msgclr
1713 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1714 replay_interrupt_return:
1715         blr
1716
1717 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)