arch/powerpc/kernel/head_fsl_booke.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2004 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *    Copyright 2004 Freescale Semiconductor, Inc
  25  *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  */
  32
  33 #include <linux/init.h>
  34 #include <linux/threads.h>
  35 #include <asm/processor.h>
  36 #include <asm/page.h>
  37 #include <asm/mmu.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/cputable.h>
  40 #include <asm/thread_info.h>
  41 #include <asm/ppc_asm.h>
  42 #include <asm/asm-offsets.h>
  43 #include <asm/cache.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/export.h>
  46 #include <asm/feature-fixups.h>
  47 #include "head_booke.h"
  48
  49 /* As with the other PowerPC ports, it is expected that when code
  50  * execution begins here, the following registers contain valid, yet
  51  * optional, information:
  52  *
  53  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  54  *   r4 - Starting address of the init RAM disk
  55  *   r5 - Ending address of the init RAM disk
  56  *   r6 - Start of kernel command line string (e.g. "mem=128")
  57  *   r7 - End of kernel command line string
  58  *
  59  */
  60         __HEAD
  61 _ENTRY(_stext);
  62 _ENTRY(_start);
  63         /*
  64          * Reserve a word at a fixed location to store the address
  65          * of abatron_pteptrs
  66          */
  67         nop
  68
  69         /* Translate device tree address to physical, save in r30/r31 */
  70         bl      get_phys_addr
  71         mr      r30,r3
  72         mr      r31,r4
  73
  74         li      r25,0                   /* phys kernel start (low) */
  75         li      r24,0                   /* CPU number */
  76         li      r23,0                   /* phys kernel start (high) */
  77
  78 #ifdef CONFIG_RELOCATABLE
  79         LOAD_REG_ADDR_PIC(r3, _stext)   /* Get our current runtime base */
  80
  81         /* Translate _stext address to physical, save in r23/r25 */
  82         bl      get_phys_addr
  83         mr      r23,r3
  84         mr      r25,r4
  85
  86         bl      0f
  87 0:      mflr    r8
  88         addis   r3,r8,(is_second_reloc - 0b)@ha
  89         lwz     r19,(is_second_reloc - 0b)@l(r3)
  90
  91         /* Check if this is the second relocation. */
  92         cmpwi   r19,1
  93         bne     1f
  94
  95         /*
  96          * For the second relocation, we already get the real memstart_addr
  97          * from device tree. So we will map PAGE_OFFSET to memstart_addr,
  98          * then the virtual address of start kernel should be:
  99          *          PAGE_OFFSET + (kernstart_addr - memstart_addr)
 100          * Since the offset between kernstart_addr and memstart_addr should
 101          * never be beyond 1G, so we can just use the lower 32bit of them
 102          * for the calculation.
 103          */
 104         lis     r3,PAGE_OFFSET@h
 105
 106         addis   r4,r8,(kernstart_addr - 0b)@ha
 107         addi    r4,r4,(kernstart_addr - 0b)@l
 108         lwz     r5,4(r4)
 109
 110         addis   r6,r8,(memstart_addr - 0b)@ha
 111         addi    r6,r6,(memstart_addr - 0b)@l
 112         lwz     r7,4(r6)
 113
 114         subf    r5,r7,r5
 115         add     r3,r3,r5
 116         b       2f
 117
 118 1:
 119         /*
 120          * We have the runtime (virutal) address of our base.
 121          * We calculate our shift of offset from a 64M page.
 122          * We could map the 64M page we belong to at PAGE_OFFSET and
 123          * get going from there.
 124          */
 125         lis     r4,KERNELBASE@h
 126         ori     r4,r4,KERNELBASE@l
 127         rlwinm  r6,r25,0,0x3ffffff              /* r6 = PHYS_START % 64M */
 128         rlwinm  r5,r4,0,0x3ffffff               /* r5 = KERNELBASE % 64M */
 129         subf    r3,r5,r6                        /* r3 = r6 - r5 */
 130         add     r3,r4,r3                        /* Required Virtual Address */
 131
 132 2:      bl      relocate
 133
 134         /*
 135          * For the second relocation, we already set the right tlb entries
 136          * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
 137         */
 138         cmpwi   r19,1
 139         beq     set_ivor
 140 #endif
 141
 142 /* We try to not make any assumptions about how the boot loader
 143  * setup or used the TLBs.  We invalidate all mappings from the
 144  * boot loader and load a single entry in TLB1[0] to map the
 145  * first 64M of kernel memory.  Any boot info passed from the
 146  * bootloader needs to live in this first 64M.
 147  *
 148  * Requirement on bootloader:
 149  *  - The page we're executing in needs to reside in TLB1 and
 150  *    have IPROT=1.  If not an invalidate broadcast could
 151  *    evict the entry we're currently executing in.
 152  *
 153  *  r3 = Index of TLB1 were executing in
 154  *  r4 = Current MSR[IS]
 155  *  r5 = Index of TLB1 temp mapping
 156  *
 157  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
 158  * if needed
 159  */
 160
 161 _ENTRY(__early_start)
 162
 163 #define ENTRY_MAPPING_BOOT_SETUP
 164 #include "fsl_booke_entry_mapping.S"
 165 #undef ENTRY_MAPPING_BOOT_SETUP
 166
 167 set_ivor:
 168         /* Establish the interrupt vector offsets */
 169         SET_IVOR(0,  CriticalInput);
 170         SET_IVOR(1,  MachineCheck);
 171         SET_IVOR(2,  DataStorage);
 172         SET_IVOR(3,  InstructionStorage);
 173         SET_IVOR(4,  ExternalInput);
 174         SET_IVOR(5,  Alignment);
 175         SET_IVOR(6,  Program);
 176         SET_IVOR(7,  FloatingPointUnavailable);
 177         SET_IVOR(8,  SystemCall);
 178         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 179         SET_IVOR(10, Decrementer);
 180         SET_IVOR(11, FixedIntervalTimer);
 181         SET_IVOR(12, WatchdogTimer);
 182         SET_IVOR(13, DataTLBError);
 183         SET_IVOR(14, InstructionTLBError);
 184         SET_IVOR(15, DebugCrit);
 185
 186         /* Establish the interrupt vector base */
 187         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 188         mtspr   SPRN_IVPR,r4
 189
 190         /* Setup the defaults for TLB entries */
 191         li      r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
 192 #ifdef CONFIG_E200
 193         oris    r2,r2,MAS4_TLBSELD(1)@h
 194 #endif
 195         mtspr   SPRN_MAS4, r2
 196
 197 #if 0
 198         /* Enable DOZE */
 199         mfspr   r2,SPRN_HID0
 200         oris    r2,r2,HID0_DOZE@h
 201         mtspr   SPRN_HID0, r2
 202 #endif
 203
 204 #if !defined(CONFIG_BDI_SWITCH)
 205         /*
 206          * The Abatron BDI JTAG debugger does not tolerate others
 207          * mucking with the debug registers.
 208          */
 209         lis     r2,DBCR0_IDM@h
 210         mtspr   SPRN_DBCR0,r2
 211         isync
 212         /* clear any residual debug events */
 213         li      r2,-1
 214         mtspr   SPRN_DBSR,r2
 215 #endif
 216
 217 #ifdef CONFIG_SMP
 218         /* Check to see if we're the second processor, and jump
 219          * to the secondary_start code if so
 220          */
 221         LOAD_REG_ADDR_PIC(r24, boot_cpuid)
 222         lwz     r24, 0(r24)
 223         cmpwi   r24, -1
 224         mfspr   r24,SPRN_PIR
 225         bne     __secondary_start
 226 #endif
 227
 228         /*
 229          * This is where the main kernel code starts.
 230          */
 231
 232         /* ptr to current */
 233         lis     r2,init_task@h
 234         ori     r2,r2,init_task@l
 235
 236         /* ptr to current thread */
 237         addi    r4,r2,THREAD    /* init task's THREAD */
 238         mtspr   SPRN_SPRG_THREAD,r4
 239
 240         /* stack */
 241         lis     r1,init_thread_union@h
 242         ori     r1,r1,init_thread_union@l
 243         li      r0,0
 244         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 245
 246         CURRENT_THREAD_INFO(r22, r1)
 247         stw     r24, TI_CPU(r22)
 248
 249         bl      early_init
 250
 251 #ifdef CONFIG_RELOCATABLE
 252         mr      r3,r30
 253         mr      r4,r31
 254 #ifdef CONFIG_PHYS_64BIT
 255         mr      r5,r23
 256         mr      r6,r25
 257 #else
 258         mr      r5,r25
 259 #endif
 260         bl      relocate_init
 261 #endif
 262
 263 #ifdef CONFIG_DYNAMIC_MEMSTART
 264         lis     r3,kernstart_addr@ha
 265         la      r3,kernstart_addr@l(r3)
 266 #ifdef CONFIG_PHYS_64BIT
 267         stw     r23,0(r3)
 268         stw     r25,4(r3)
 269 #else
 270         stw     r25,0(r3)
 271 #endif
 272 #endif
 273
 274 /*
 275  * Decide what sort of machine this is and initialize the MMU.
 276  */
 277         mr      r3,r30
 278         mr      r4,r31
 279         bl      machine_init
 280         bl      MMU_init
 281
 282         /* Setup PTE pointers for the Abatron bdiGDB */
 283         lis     r6, swapper_pg_dir@h
 284         ori     r6, r6, swapper_pg_dir@l
 285         lis     r5, abatron_pteptrs@h
 286         ori     r5, r5, abatron_pteptrs@l
 287         lis     r4, KERNELBASE@h
 288         ori     r4, r4, KERNELBASE@l
 289         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 290         stw     r6, 0(r5)
 291
 292         /* Let's move on */
 293         lis     r4,start_kernel@h
 294         ori     r4,r4,start_kernel@l
 295         lis     r3,MSR_KERNEL@h
 296         ori     r3,r3,MSR_KERNEL@l
 297         mtspr   SPRN_SRR0,r4
 298         mtspr   SPRN_SRR1,r3
 299         rfi                     /* change context and jump to start_kernel */
 300
 301 /* Macros to hide the PTE size differences
 302  *
 303  * FIND_PTE -- walks the page tables given EA & pgdir pointer
 304  *   r10 -- EA of fault
 305  *   r11 -- PGDIR pointer
 306  *   r12 -- free
 307  *   label 2: is the bailout case
 308  *
 309  * if we find the pte (fall through):
 310  *   r11 is low pte word
 311  *   r12 is pointer to the pte
 312  *   r10 is the pshift from the PGD, if we're a hugepage
 313  */
 314 #ifdef CONFIG_PTE_64BIT
 315 #ifdef CONFIG_HUGETLB_PAGE
 316 #define FIND_PTE        \
 317         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 318         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 319         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 320         blt     1000f;                  /* Normal non-huge page */      \
 321         beq     2f;                     /* Bail if no table */          \
 322         oris    r11, r11, PD_HUGE@h;    /* Put back address bit */      \
 323         andi.   r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
 324         xor     r12, r10, r11;          /* drop size bits from pointer */ \
 325         b       1001f;                                                  \
 326 1000:   rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 327         li      r10, 0;                 /* clear r10 */                 \
 328 1001:   lwz     r11, 4(r12);            /* Get pte entry */
 329 #else
 330 #define FIND_PTE        \
 331         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 332         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 333         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 334         beq     2f;                     /* Bail if no table */          \
 335         rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 336         lwz     r11, 4(r12);            /* Get pte entry */
 337 #endif /* HUGEPAGE */
 338 #else /* !PTE_64BIT */
 339 #define FIND_PTE        \
 340         rlwimi  r11, r10, 12, 20, 29;   /* Create L1 (pgdir/pmd) address */     \
 341         lwz     r11, 0(r11);            /* Get L1 entry */                      \
 342         rlwinm. r12, r11, 0, 0, 19;     /* Extract L2 (pte) base address */     \
 343         beq     2f;                     /* Bail if no table */                  \
 344         rlwimi  r12, r10, 22, 20, 29;   /* Compute PTE address */               \
 345         lwz     r11, 0(r12);            /* Get Linux PTE */
 346 #endif
 347
 348 /*
 349  * Interrupt vector entry code
 350  *
 351  * The Book E MMUs are always on so we don't need to handle
 352  * interrupts in real mode as with previous PPC processors. In
 353  * this case we handle interrupts in the kernel virtual address
 354  * space.
 355  *
 356  * Interrupt vectors are dynamically placed relative to the
 357  * interrupt prefix as determined by the address of interrupt_base.
 358  * The interrupt vectors offsets are programmed using the labels
 359  * for each interrupt vector entry.
 360  *
 361  * Interrupt vectors must be aligned on a 16 byte boundary.
 362  * We align on a 32 byte cache line boundary for good measure.
 363  */
 364
 365 interrupt_base:
 366         /* Critical Input Interrupt */
 367         CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
 368
 369         /* Machine Check Interrupt */
 370 #ifdef CONFIG_E200
 371         /* no RFMCI, MCSRRs on E200 */
 372         CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
 373                            machine_check_exception)
 374 #else
 375         MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 376 #endif
 377
 378         /* Data Storage Interrupt */
 379         START_EXCEPTION(DataStorage)
 380         NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
 381         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 382         stw     r5,_ESR(r11)
 383         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 384         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
 385         bne     1f
 386         EXC_XFER_LITE(0x0300, handle_page_fault)
 387 1:
 388         addi    r3,r1,STACK_FRAME_OVERHEAD
 389         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
 390
 391         /* Instruction Storage Interrupt */
 392         INSTRUCTION_STORAGE_EXCEPTION
 393
 394         /* External Input Interrupt */
 395         EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
 396
 397         /* Alignment Interrupt */
 398         ALIGNMENT_EXCEPTION
 399
 400         /* Program Interrupt */
 401         PROGRAM_EXCEPTION
 402
 403         /* Floating Point Unavailable Interrupt */
 404 #ifdef CONFIG_PPC_FPU
 405         FP_UNAVAILABLE_EXCEPTION
 406 #else
 407 #ifdef CONFIG_E200
 408         /* E200 treats 'normal' floating point instructions as FP Unavail exception */
 409         EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
 410                   program_check_exception, EXC_XFER_EE)
 411 #else
 412         EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
 413                   unknown_exception, EXC_XFER_EE)
 414 #endif
 415 #endif
 416
 417         /* System Call Interrupt */
 418         START_EXCEPTION(SystemCall)
 419         NORMAL_EXCEPTION_PROLOG(SYSCALL)
 420         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 421
 422         /* Auxiliary Processor Unavailable Interrupt */
 423         EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
 424                   unknown_exception, EXC_XFER_EE)
 425
 426         /* Decrementer Interrupt */
 427         DECREMENTER_EXCEPTION
 428
 429         /* Fixed Internal Timer Interrupt */
 430         /* TODO: Add FIT support */
 431         EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
 432                   unknown_exception, EXC_XFER_EE)
 433
 434         /* Watchdog Timer Interrupt */
 435 #ifdef CONFIG_BOOKE_WDT
 436         CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
 437 #else
 438         CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
 439 #endif
 440
 441         /* Data TLB Error Interrupt */
 442         START_EXCEPTION(DataTLBError)
 443         mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
 444         mfspr   r10, SPRN_SPRG_THREAD
 445         stw     r11, THREAD_NORMSAVE(0)(r10)
 446 #ifdef CONFIG_KVM_BOOKE_HV
 447 BEGIN_FTR_SECTION
 448         mfspr   r11, SPRN_SRR1
 449 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 450 #endif
 451         stw     r12, THREAD_NORMSAVE(1)(r10)
 452         stw     r13, THREAD_NORMSAVE(2)(r10)
 453         mfcr    r13
 454         stw     r13, THREAD_NORMSAVE(3)(r10)
 455         DO_KVM  BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
 456 START_BTB_FLUSH_SECTION
 457         mfspr r11, SPRN_SRR1
 458         andi. r10,r11,MSR_PR
 459         beq 1f
 460         BTB_FLUSH(r10)
 461 1:
 462 END_BTB_FLUSH_SECTION
 463         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 464
 465         /* If we are faulting a kernel address, we have to use the
 466          * kernel page tables.
 467          */
 468         lis     r11, PAGE_OFFSET@h
 469         cmplw   5, r10, r11
 470         blt     5, 3f
 471         lis     r11, swapper_pg_dir@h
 472         ori     r11, r11, swapper_pg_dir@l
 473
 474         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 475         rlwinm  r12,r12,0,16,1
 476         mtspr   SPRN_MAS1,r12
 477
 478         b       4f
 479
 480         /* Get the PGD for the current thread */
 481 3:
 482         mfspr   r11,SPRN_SPRG_THREAD
 483         lwz     r11,PGDIR(r11)
 484
 485 4:
 486         /* Mask of required permission bits. Note that while we
 487          * do copy ESR:ST to _PAGE_RW position as trying to write
 488          * to an RO page is pretty common, we don't do it with
 489          * _PAGE_DIRTY. We could do it, but it's a fairly rare
 490          * event so I'd rather take the overhead when it happens
 491          * rather than adding an instruction here. We should measure
 492          * whether the whole thing is worth it in the first place
 493          * as we could avoid loading SPRN_ESR completely in the first
 494          * place...
 495          *
 496          * TODO: Is it worth doing that mfspr & rlwimi in the first
 497          *       place or can we save a couple of instructions here ?
 498          */
 499         mfspr   r12,SPRN_ESR
 500 #ifdef CONFIG_PTE_64BIT
 501         li      r13,_PAGE_PRESENT
 502         oris    r13,r13,_PAGE_ACCESSED@h
 503 #else
 504         li      r13,_PAGE_PRESENT|_PAGE_ACCESSED
 505 #endif
 506         rlwimi  r13,r12,11,29,29
 507
 508         FIND_PTE
 509         andc.   r13,r13,r11             /* Check permission */
 510
 511 #ifdef CONFIG_PTE_64BIT
 512 #ifdef CONFIG_SMP
 513         subf    r13,r11,r12             /* create false data dep */
 514         lwzx    r13,r11,r13             /* Get upper pte bits */
 515 #else
 516         lwz     r13,0(r12)              /* Get upper pte bits */
 517 #endif
 518 #endif
 519
 520         bne     2f                      /* Bail if permission/valid mismach */
 521
 522         /* Jump to common tlb load */
 523         b       finish_tlb_load
 524 2:
 525         /* The bailout.  Restore registers to pre-exception conditions
 526          * and call the heavyweights to help us out.
 527          */
 528         mfspr   r10, SPRN_SPRG_THREAD
 529         lwz     r11, THREAD_NORMSAVE(3)(r10)
 530         mtcr    r11
 531         lwz     r13, THREAD_NORMSAVE(2)(r10)
 532         lwz     r12, THREAD_NORMSAVE(1)(r10)
 533         lwz     r11, THREAD_NORMSAVE(0)(r10)
 534         mfspr   r10, SPRN_SPRG_RSCRATCH0
 535         b       DataStorage
 536
 537         /* Instruction TLB Error Interrupt */
 538         /*
 539          * Nearly the same as above, except we get our
 540          * information from different registers and bailout
 541          * to a different point.
 542          */
 543         START_EXCEPTION(InstructionTLBError)
 544         mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
 545         mfspr   r10, SPRN_SPRG_THREAD
 546         stw     r11, THREAD_NORMSAVE(0)(r10)
 547 #ifdef CONFIG_KVM_BOOKE_HV
 548 BEGIN_FTR_SECTION
 549         mfspr   r11, SPRN_SRR1
 550 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 551 #endif
 552         stw     r12, THREAD_NORMSAVE(1)(r10)
 553         stw     r13, THREAD_NORMSAVE(2)(r10)
 554         mfcr    r13
 555         stw     r13, THREAD_NORMSAVE(3)(r10)
 556         DO_KVM  BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
 557 START_BTB_FLUSH_SECTION
 558         mfspr r11, SPRN_SRR1
 559         andi. r10,r11,MSR_PR
 560         beq 1f
 561         BTB_FLUSH(r10)
 562 1:
 563 END_BTB_FLUSH_SECTION
 564
 565         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 566
 567         /* If we are faulting a kernel address, we have to use the
 568          * kernel page tables.
 569          */
 570         lis     r11, PAGE_OFFSET@h
 571         cmplw   5, r10, r11
 572         blt     5, 3f
 573         lis     r11, swapper_pg_dir@h
 574         ori     r11, r11, swapper_pg_dir@l
 575
 576         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 577         rlwinm  r12,r12,0,16,1
 578         mtspr   SPRN_MAS1,r12
 579
 580         /* Make up the required permissions for kernel code */
 581 #ifdef CONFIG_PTE_64BIT
 582         li      r13,_PAGE_PRESENT | _PAGE_BAP_SX
 583         oris    r13,r13,_PAGE_ACCESSED@h
 584 #else
 585         li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
 586 #endif
 587         b       4f
 588
 589         /* Get the PGD for the current thread */
 590 3:
 591         mfspr   r11,SPRN_SPRG_THREAD
 592         lwz     r11,PGDIR(r11)
 593
 594         /* Make up the required permissions for user code */
 595 #ifdef CONFIG_PTE_64BIT
 596         li      r13,_PAGE_PRESENT | _PAGE_BAP_UX
 597         oris    r13,r13,_PAGE_ACCESSED@h
 598 #else
 599         li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
 600 #endif
 601
 602 4:
 603         FIND_PTE
 604         andc.   r13,r13,r11             /* Check permission */
 605
 606 #ifdef CONFIG_PTE_64BIT
 607 #ifdef CONFIG_SMP
 608         subf    r13,r11,r12             /* create false data dep */
 609         lwzx    r13,r11,r13             /* Get upper pte bits */
 610 #else
 611         lwz     r13,0(r12)              /* Get upper pte bits */
 612 #endif
 613 #endif
 614
 615         bne     2f                      /* Bail if permission mismach */
 616
 617         /* Jump to common TLB load point */
 618         b       finish_tlb_load
 619
 620 2:
 621         /* The bailout.  Restore registers to pre-exception conditions
 622          * and call the heavyweights to help us out.
 623          */
 624         mfspr   r10, SPRN_SPRG_THREAD
 625         lwz     r11, THREAD_NORMSAVE(3)(r10)
 626         mtcr    r11
 627         lwz     r13, THREAD_NORMSAVE(2)(r10)
 628         lwz     r12, THREAD_NORMSAVE(1)(r10)
 629         lwz     r11, THREAD_NORMSAVE(0)(r10)
 630         mfspr   r10, SPRN_SPRG_RSCRATCH0
 631         b       InstructionStorage
 632
 633 /* Define SPE handlers for e200 and e500v2 */
 634 #ifdef CONFIG_SPE
 635         /* SPE Unavailable */
 636         START_EXCEPTION(SPEUnavailable)
 637         NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
 638         beq     1f
 639         bl      load_up_spe
 640         b       fast_exception_return
 641 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 642         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 643 #elif defined(CONFIG_SPE_POSSIBLE)
 644         EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
 645                   unknown_exception, EXC_XFER_EE)
 646 #endif /* CONFIG_SPE_POSSIBLE */
 647
 648         /* SPE Floating Point Data */
 649 #ifdef CONFIG_SPE
 650         EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
 651                   SPEFloatingPointException, EXC_XFER_EE)
 652
 653         /* SPE Floating Point Round */
 654         EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
 655                   SPEFloatingPointRoundException, EXC_XFER_EE)
 656 #elif defined(CONFIG_SPE_POSSIBLE)
 657         EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
 658                   unknown_exception, EXC_XFER_EE)
 659         EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
 660                   unknown_exception, EXC_XFER_EE)
 661 #endif /* CONFIG_SPE_POSSIBLE */
 662
 663
 664         /* Performance Monitor */
 665         EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
 666                   performance_monitor_exception, EXC_XFER_STD)
 667
 668         EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
 669
 670         CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
 671                            CriticalDoorbell, unknown_exception)
 672
 673         /* Debug Interrupt */
 674         DEBUG_DEBUG_EXCEPTION
 675         DEBUG_CRIT_EXCEPTION
 676
 677         GUEST_DOORBELL_EXCEPTION
 678
 679         CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
 680                            unknown_exception)
 681
 682         /* Hypercall */
 683         EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE)
 684
 685         /* Embedded Hypervisor Privilege */
 686         EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
 687
 688 interrupt_end:
 689
 690 /*
 691  * Local functions
 692  */
 693
 694 /*
 695  * Both the instruction and data TLB miss get to this
 696  * point to load the TLB.
 697  *      r10 - tsize encoding (if HUGETLB_PAGE) or available to use
 698  *      r11 - TLB (info from Linux PTE)
 699  *      r12 - available to use
 700  *      r13 - upper bits of PTE (if PTE_64BIT) or available to use
 701  *      CR5 - results of addr >= PAGE_OFFSET
 702  *      MAS0, MAS1 - loaded with proper value when we get here
 703  *      MAS2, MAS3 - will need additional info from Linux PTE
 704  *      Upon exit, we reload everything and RFI.
 705  */
 706 finish_tlb_load:
 707 #ifdef CONFIG_HUGETLB_PAGE
 708         cmpwi   6, r10, 0                       /* check for huge page */
 709         beq     6, finish_tlb_load_cont         /* !huge */
 710
 711         /* Alas, we need more scratch registers for hugepages */
 712         mfspr   r12, SPRN_SPRG_THREAD
 713         stw     r14, THREAD_NORMSAVE(4)(r12)
 714         stw     r15, THREAD_NORMSAVE(5)(r12)
 715         stw     r16, THREAD_NORMSAVE(6)(r12)
 716         stw     r17, THREAD_NORMSAVE(7)(r12)
 717
 718         /* Get the next_tlbcam_idx percpu var */
 719 #ifdef CONFIG_SMP
 720         lwz     r12, THREAD_INFO-THREAD(r12)
 721         lwz     r15, TI_CPU(r12)
 722         lis     r14, __per_cpu_offset@h
 723         ori     r14, r14, __per_cpu_offset@l
 724         rlwinm  r15, r15, 2, 0, 29
 725         lwzx    r16, r14, r15
 726 #else
 727         li      r16, 0
 728 #endif
 729         lis     r17, next_tlbcam_idx@h
 730         ori     r17, r17, next_tlbcam_idx@l
 731         add     r17, r17, r16                   /* r17 = *next_tlbcam_idx */
 732         lwz     r15, 0(r17)                     /* r15 = next_tlbcam_idx */
 733
 734         lis     r14, MAS0_TLBSEL(1)@h           /* select TLB1 (TLBCAM) */
 735         rlwimi  r14, r15, 16, 4, 15             /* next_tlbcam_idx entry */
 736         mtspr   SPRN_MAS0, r14
 737
 738         /* Extract TLB1CFG(NENTRY) */
 739         mfspr   r16, SPRN_TLB1CFG
 740         andi.   r16, r16, 0xfff
 741
 742         /* Update next_tlbcam_idx, wrapping when necessary */
 743         addi    r15, r15, 1
 744         cmpw    r15, r16
 745         blt     100f
 746         lis     r14, tlbcam_index@h
 747         ori     r14, r14, tlbcam_index@l
 748         lwz     r15, 0(r14)
 749 100:    stw     r15, 0(r17)
 750
 751         /*
 752          * Calc MAS1_TSIZE from r10 (which has pshift encoded)
 753          * tlb_enc = (pshift - 10).
 754          */
 755         subi    r15, r10, 10
 756         mfspr   r16, SPRN_MAS1
 757         rlwimi  r16, r15, 7, 20, 24
 758         mtspr   SPRN_MAS1, r16
 759
 760         /* copy the pshift for use later */
 761         mr      r14, r10
 762
 763         /* fall through */
 764
 765 #endif /* CONFIG_HUGETLB_PAGE */
 766
 767         /*
 768          * We set execute, because we don't have the granularity to
 769          * properly set this at the page level (Linux problem).
 770          * Many of these bits are software only.  Bits we don't set
 771          * here we (properly should) assume have the appropriate value.
 772          */
 773 finish_tlb_load_cont:
 774 #ifdef CONFIG_PTE_64BIT
 775         rlwinm  r12, r11, 32-2, 26, 31  /* Move in perm bits */
 776         andi.   r10, r11, _PAGE_DIRTY
 777         bne     1f
 778         li      r10, MAS3_SW | MAS3_UW
 779         andc    r12, r12, r10
 780 1:      rlwimi  r12, r13, 20, 0, 11     /* grab RPN[32:43] */
 781         rlwimi  r12, r11, 20, 12, 19    /* grab RPN[44:51] */
 782 2:      mtspr   SPRN_MAS3, r12
 783 BEGIN_MMU_FTR_SECTION
 784         srwi    r10, r13, 12            /* grab RPN[12:31] */
 785         mtspr   SPRN_MAS7, r10
 786 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
 787 #else
 788         li      r10, (_PAGE_EXEC | _PAGE_PRESENT)
 789         mr      r13, r11
 790         rlwimi  r10, r11, 31, 29, 29    /* extract _PAGE_DIRTY into SW */
 791         and     r12, r11, r10
 792         andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
 793         slwi    r10, r12, 1
 794         or      r10, r10, r12
 795         iseleq  r12, r12, r10
 796         rlwimi  r13, r12, 0, 20, 31     /* Get RPN from PTE, merge w/ perms */
 797         mtspr   SPRN_MAS3, r13
 798 #endif
 799
 800         mfspr   r12, SPRN_MAS2
 801 #ifdef CONFIG_PTE_64BIT
 802         rlwimi  r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
 803 #else
 804         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 805 #endif
 806 #ifdef CONFIG_HUGETLB_PAGE
 807         beq     6, 3f                   /* don't mask if page isn't huge */
 808         li      r13, 1
 809         slw     r13, r13, r14
 810         subi    r13, r13, 1
 811         rlwinm  r13, r13, 0, 0, 19      /* bottom bits used for WIMGE/etc */
 812         andc    r12, r12, r13           /* mask off ea bits within the page */
 813 #endif
 814 3:      mtspr   SPRN_MAS2, r12
 815
 816 #ifdef CONFIG_E200
 817         /* Round robin TLB1 entries assignment */
 818         mfspr   r12, SPRN_MAS0
 819
 820         /* Extract TLB1CFG(NENTRY) */
 821         mfspr   r11, SPRN_TLB1CFG
 822         andi.   r11, r11, 0xfff
 823
 824         /* Extract MAS0(NV) */
 825         andi.   r13, r12, 0xfff
 826         addi    r13, r13, 1
 827         cmpw    0, r13, r11
 828         addi    r12, r12, 1
 829
 830         /* check if we need to wrap */
 831         blt     7f
 832
 833         /* wrap back to first free tlbcam entry */
 834         lis     r13, tlbcam_index@ha
 835         lwz     r13, tlbcam_index@l(r13)
 836         rlwimi  r12, r13, 0, 20, 31
 837 7:
 838         mtspr   SPRN_MAS0,r12
 839 #endif /* CONFIG_E200 */
 840
 841 tlb_write_entry:
 842         tlbwe
 843
 844         /* Done...restore registers and get out of here.  */
 845         mfspr   r10, SPRN_SPRG_THREAD
 846 #ifdef CONFIG_HUGETLB_PAGE
 847         beq     6, 8f /* skip restore for 4k page faults */
 848         lwz     r14, THREAD_NORMSAVE(4)(r10)
 849         lwz     r15, THREAD_NORMSAVE(5)(r10)
 850         lwz     r16, THREAD_NORMSAVE(6)(r10)
 851         lwz     r17, THREAD_NORMSAVE(7)(r10)
 852 #endif
 853 8:      lwz     r11, THREAD_NORMSAVE(3)(r10)
 854         mtcr    r11
 855         lwz     r13, THREAD_NORMSAVE(2)(r10)
 856         lwz     r12, THREAD_NORMSAVE(1)(r10)
 857         lwz     r11, THREAD_NORMSAVE(0)(r10)
 858         mfspr   r10, SPRN_SPRG_RSCRATCH0
 859         rfi                                     /* Force context change */
 860
 861 #ifdef CONFIG_SPE
 862 /* Note that the SPE support is closely modeled after the AltiVec
 863  * support.  Changes to one are likely to be applicable to the
 864  * other!  */
 865 _GLOBAL(load_up_spe)
 866 /*
 867  * Disable SPE for the task which had SPE previously,
 868  * and save its SPE registers in its thread_struct.
 869  * Enables SPE for use in the kernel on return.
 870  * On SMP we know the SPE units are free, since we give it up every
 871  * switch.  -- Kumar
 872  */
 873         mfmsr   r5
 874         oris    r5,r5,MSR_SPE@h
 875         mtmsr   r5                      /* enable use of SPE now */
 876         isync
 877         /* enable use of SPE after return */
 878         oris    r9,r9,MSR_SPE@h
 879         mfspr   r5,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
 880         li      r4,1
 881         li      r10,THREAD_ACC
 882         stw     r4,THREAD_USED_SPE(r5)
 883         evlddx  evr4,r10,r5
 884         evmra   evr4,evr4
 885         REST_32EVRS(0,r10,r5,THREAD_EVR0)
 886         blr
 887
 888 /*
 889  * SPE unavailable trap from kernel - print a message, but let
 890  * the task use SPE in the kernel until it returns to user mode.
 891  */
 892 KernelSPE:
 893         lwz     r3,_MSR(r1)
 894         oris    r3,r3,MSR_SPE@h
 895         stw     r3,_MSR(r1)     /* enable use of SPE after return */
 896 #ifdef CONFIG_PRINTK
 897         lis     r3,87f@h
 898         ori     r3,r3,87f@l
 899         mr      r4,r2           /* current */
 900         lwz     r5,_NIP(r1)
 901         bl      printk
 902 #endif
 903         b       ret_from_except
 904 #ifdef CONFIG_PRINTK
 905 87:     .string "SPE used in kernel  (task=%p, pc=%x)  \n"
 906 #endif
 907         .align  4,0
 908
 909 #endif /* CONFIG_SPE */
 910
 911 /*
 912  * Translate the effec addr in r3 to phys addr. The phys addr will be put
 913  * into r3(higher 32bit) and r4(lower 32bit)
 914  */
 915 get_phys_addr:
 916         mfmsr   r8
 917         mfspr   r9,SPRN_PID
 918         rlwinm  r9,r9,16,0x3fff0000     /* turn PID into MAS6[SPID] */
 919         rlwimi  r9,r8,28,0x00000001     /* turn MSR[DS] into MAS6[SAS] */
 920         mtspr   SPRN_MAS6,r9
 921
 922         tlbsx   0,r3                    /* must succeed */
 923
 924         mfspr   r8,SPRN_MAS1
 925         mfspr   r12,SPRN_MAS3
 926         rlwinm  r9,r8,25,0x1f           /* r9 = log2(page size) */
 927         li      r10,1024
 928         slw     r10,r10,r9              /* r10 = page size */
 929         addi    r10,r10,-1
 930         and     r11,r3,r10              /* r11 = page offset */
 931         andc    r4,r12,r10              /* r4 = page base */
 932         or      r4,r4,r11               /* r4 = devtree phys addr */
 933 #ifdef CONFIG_PHYS_64BIT
 934         mfspr   r3,SPRN_MAS7
 935 #endif
 936         blr
 937
 938 /*
 939  * Global functions
 940  */
 941
 942 #ifdef CONFIG_E200
 943 /* Adjust or setup IVORs for e200 */
 944 _GLOBAL(__setup_e200_ivors)
 945         li      r3,DebugDebug@l
 946         mtspr   SPRN_IVOR15,r3
 947         li      r3,SPEUnavailable@l
 948         mtspr   SPRN_IVOR32,r3
 949         li      r3,SPEFloatingPointData@l
 950         mtspr   SPRN_IVOR33,r3
 951         li      r3,SPEFloatingPointRound@l
 952         mtspr   SPRN_IVOR34,r3
 953         sync
 954         blr
 955 #endif
 956
 957 #ifdef CONFIG_E500
 958 #ifndef CONFIG_PPC_E500MC
 959 /* Adjust or setup IVORs for e500v1/v2 */
 960 _GLOBAL(__setup_e500_ivors)
 961         li      r3,DebugCrit@l
 962         mtspr   SPRN_IVOR15,r3
 963         li      r3,SPEUnavailable@l
 964         mtspr   SPRN_IVOR32,r3
 965         li      r3,SPEFloatingPointData@l
 966         mtspr   SPRN_IVOR33,r3
 967         li      r3,SPEFloatingPointRound@l
 968         mtspr   SPRN_IVOR34,r3
 969         li      r3,PerformanceMonitor@l
 970         mtspr   SPRN_IVOR35,r3
 971         sync
 972         blr
 973 #else
 974 /* Adjust or setup IVORs for e500mc */
 975 _GLOBAL(__setup_e500mc_ivors)
 976         li      r3,DebugDebug@l
 977         mtspr   SPRN_IVOR15,r3
 978         li      r3,PerformanceMonitor@l
 979         mtspr   SPRN_IVOR35,r3
 980         li      r3,Doorbell@l
 981         mtspr   SPRN_IVOR36,r3
 982         li      r3,CriticalDoorbell@l
 983         mtspr   SPRN_IVOR37,r3
 984         sync
 985         blr
 986
 987 /* setup ehv ivors for */
 988 _GLOBAL(__setup_ehv_ivors)
 989         li      r3,GuestDoorbell@l
 990         mtspr   SPRN_IVOR38,r3
 991         li      r3,CriticalGuestDoorbell@l
 992         mtspr   SPRN_IVOR39,r3
 993         li      r3,Hypercall@l
 994         mtspr   SPRN_IVOR40,r3
 995         li      r3,Ehvpriv@l
 996         mtspr   SPRN_IVOR41,r3
 997         sync
 998         blr
 999 #endif /* CONFIG_PPC_E500MC */
1000 #endif /* CONFIG_E500 */
1001
1002 #ifdef CONFIG_SPE
1003 /*
1004  * extern void __giveup_spe(struct task_struct *prev)
1005  *
1006  */
1007 _GLOBAL(__giveup_spe)
1008         addi    r3,r3,THREAD            /* want THREAD of task */
1009         lwz     r5,PT_REGS(r3)
1010         cmpi    0,r5,0
1011         SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1012         evxor   evr6, evr6, evr6        /* clear out evr6 */
1013         evmwumiaa evr6, evr6, evr6      /* evr6 <- ACC = 0 * 0 + ACC */
1014         li      r4,THREAD_ACC
1015         evstddx evr6, r4, r3            /* save off accumulator */
1016         beq     1f
1017         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1018         lis     r3,MSR_SPE@h
1019         andc    r4,r4,r3                /* disable SPE for previous task */
1020         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1021 1:
1022         blr
1023 #endif /* CONFIG_SPE */
1024
1025 /*
1026  * extern void abort(void)
1027  *
1028  * At present, this routine just applies a system reset.
1029  */
1030 _GLOBAL(abort)
1031         li      r13,0
1032         mtspr   SPRN_DBCR0,r13          /* disable all debug events */
1033         isync
1034         mfmsr   r13
1035         ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
1036         mtmsr   r13
1037         isync
1038         mfspr   r13,SPRN_DBCR0
1039         lis     r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1040         mtspr   SPRN_DBCR0,r13
1041         isync
1042
1043 _GLOBAL(set_context)
1044
1045 #ifdef CONFIG_BDI_SWITCH
1046         /* Context switch the PTE pointer for the Abatron BDI2000.
1047          * The PGDIR is the second parameter.
1048          */
1049         lis     r5, abatron_pteptrs@h
1050         ori     r5, r5, abatron_pteptrs@l
1051         stw     r4, 0x4(r5)
1052 #endif
1053         mtspr   SPRN_PID,r3
1054         isync                   /* Force context change */
1055         blr
1056
1057 #ifdef CONFIG_SMP
1058 /* When we get here, r24 needs to hold the CPU # */
1059         .globl __secondary_start
1060 __secondary_start:
1061         LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1062         lwz     r3,0(r3)
1063         mtctr   r3
1064         li      r26,0           /* r26 safe? */
1065
1066         bl      switch_to_as1
1067         mr      r27,r3          /* tlb entry */
1068         /* Load each CAM entry */
1069 1:      mr      r3,r26
1070         bl      loadcam_entry
1071         addi    r26,r26,1
1072         bdnz    1b
1073         mr      r3,r27          /* tlb entry */
1074         LOAD_REG_ADDR_PIC(r4, memstart_addr)
1075         lwz     r4,0(r4)
1076         mr      r5,r25          /* phys kernel start */
1077         rlwinm  r5,r5,0,~0x3ffffff      /* aligned 64M */
1078         subf    r4,r5,r4        /* memstart_addr - phys kernel start */
1079         li      r5,0            /* no device tree */
1080         li      r6,0            /* not boot cpu */
1081         bl      restore_to_as0
1082
1083
1084         lis     r3,__secondary_hold_acknowledge@h
1085         ori     r3,r3,__secondary_hold_acknowledge@l
1086         stw     r24,0(r3)
1087
1088         li      r3,0
1089         mr      r4,r24          /* Why? */
1090         bl      call_setup_cpu
1091
1092         /* get current_thread_info and current */
1093         lis     r1,secondary_ti@ha
1094         lwz     r1,secondary_ti@l(r1)
1095         lwz     r2,TI_TASK(r1)
1096
1097         /* stack */
1098         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1099         li      r0,0
1100         stw     r0,0(r1)
1101
1102         /* ptr to current thread */
1103         addi    r4,r2,THREAD    /* address of our thread_struct */
1104         mtspr   SPRN_SPRG_THREAD,r4
1105
1106         /* Setup the defaults for TLB entries */
1107         li      r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1108         mtspr   SPRN_MAS4,r4
1109
1110         /* Jump to start_secondary */
1111         lis     r4,MSR_KERNEL@h
1112         ori     r4,r4,MSR_KERNEL@l
1113         lis     r3,start_secondary@h
1114         ori     r3,r3,start_secondary@l
1115         mtspr   SPRN_SRR0,r3
1116         mtspr   SPRN_SRR1,r4
1117         sync
1118         rfi
1119         sync
1120
1121         .globl __secondary_hold_acknowledge
1122 __secondary_hold_acknowledge:
1123         .long   -1
1124 #endif
1125
1126 /*
1127  * Create a tlb entry with the same effective and physical address as
1128  * the tlb entry used by the current running code. But set the TS to 1.
1129  * Then switch to the address space 1. It will return with the r3 set to
1130  * the ESEL of the new created tlb.
1131  */
1132 _GLOBAL(switch_to_as1)
1133         mflr    r5
1134
1135         /* Find a entry not used */
1136         mfspr   r3,SPRN_TLB1CFG
1137         andi.   r3,r3,0xfff
1138         mfspr   r4,SPRN_PID
1139         rlwinm  r4,r4,16,0x3fff0000     /* turn PID into MAS6[SPID] */
1140         mtspr   SPRN_MAS6,r4
1141 1:      lis     r4,0x1000               /* Set MAS0(TLBSEL) = 1 */
1142         addi    r3,r3,-1
1143         rlwimi  r4,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
1144         mtspr   SPRN_MAS0,r4
1145         tlbre
1146         mfspr   r4,SPRN_MAS1
1147         andis.  r4,r4,MAS1_VALID@h
1148         bne     1b
1149
1150         /* Get the tlb entry used by the current running code */
1151         bl      0f
1152 0:      mflr    r4
1153         tlbsx   0,r4
1154
1155         mfspr   r4,SPRN_MAS1
1156         ori     r4,r4,MAS1_TS           /* Set the TS = 1 */
1157         mtspr   SPRN_MAS1,r4
1158
1159         mfspr   r4,SPRN_MAS0
1160         rlwinm  r4,r4,0,~MAS0_ESEL_MASK
1161         rlwimi  r4,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
1162         mtspr   SPRN_MAS0,r4
1163         tlbwe
1164         isync
1165         sync
1166
1167         mfmsr   r4
1168         ori     r4,r4,MSR_IS | MSR_DS
1169         mtspr   SPRN_SRR0,r5
1170         mtspr   SPRN_SRR1,r4
1171         sync
1172         rfi
1173
1174 /*
1175  * Restore to the address space 0 and also invalidate the tlb entry created
1176  * by switch_to_as1.
1177  * r3 - the tlb entry which should be invalidated
1178  * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1179  * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1180  * r6 - boot cpu
1181 */
1182 _GLOBAL(restore_to_as0)
1183         mflr    r0
1184
1185         bl      0f
1186 0:      mflr    r9
1187         addi    r9,r9,1f - 0b
1188
1189         /*
1190          * We may map the PAGE_OFFSET in AS0 to a different physical address,
1191          * so we need calculate the right jump and device tree address based
1192          * on the offset passed by r4.
1193          */
1194         add     r9,r9,r4
1195         add     r5,r5,r4
1196         add     r0,r0,r4
1197
1198 2:      mfmsr   r7
1199         li      r8,(MSR_IS | MSR_DS)
1200         andc    r7,r7,r8
1201
1202         mtspr   SPRN_SRR0,r9
1203         mtspr   SPRN_SRR1,r7
1204         sync
1205         rfi
1206
1207         /* Invalidate the temporary tlb entry for AS1 */
1208 1:      lis     r9,0x1000               /* Set MAS0(TLBSEL) = 1 */
1209         rlwimi  r9,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
1210         mtspr   SPRN_MAS0,r9
1211         tlbre
1212         mfspr   r9,SPRN_MAS1
1213         rlwinm  r9,r9,0,2,31            /* Clear MAS1 Valid and IPPROT */
1214         mtspr   SPRN_MAS1,r9
1215         tlbwe
1216         isync
1217
1218         cmpwi   r4,0
1219         cmpwi   cr1,r6,0
1220         cror    eq,4*cr1+eq,eq
1221         bne     3f                      /* offset != 0 && is_boot_cpu */
1222         mtlr    r0
1223         blr
1224
1225         /*
1226          * The PAGE_OFFSET will map to a different physical address,
1227          * jump to _start to do another relocation again.
1228         */
1229 3:      mr      r3,r5
1230         bl      _start
1231
1232 /*
1233  * We put a few things here that have to be page-aligned. This stuff
1234  * goes at the beginning of the data segment, which is page-aligned.
1235  */
1236         .data
1237         .align  12
1238         .globl  sdata
1239 sdata:
1240         .globl  empty_zero_page
1241 empty_zero_page:
1242         .space  4096
1243 EXPORT_SYMBOL(empty_zero_page)
1244         .globl  swapper_pg_dir
1245 swapper_pg_dir:
1246         .space  PGD_TABLE_SIZE
1247
1248 /*
1249  * Room for two PTE pointers, usually the kernel and current user pointers
1250  * to their respective root page table.
1251  */
1252 abatron_pteptrs:
1253         .space  8