2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38 #include <linux/context_tracking.h>
40 #include <asm/emulated_ops.h>
41 #include <asm/pgtable.h>
42 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
48 #ifdef CONFIG_PMAC_BACKLIGHT
49 #include <asm/backlight.h>
52 #include <asm/firmware.h>
53 #include <asm/processor.h>
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
62 #include <asm/debug.h>
63 #include <sysdev/fsl_pci.h>
65 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
66 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
67 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
68 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
69 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
70 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
71 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
72 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
74 EXPORT_SYMBOL(__debugger
);
75 EXPORT_SYMBOL(__debugger_ipi
);
76 EXPORT_SYMBOL(__debugger_bpt
);
77 EXPORT_SYMBOL(__debugger_sstep
);
78 EXPORT_SYMBOL(__debugger_iabr_match
);
79 EXPORT_SYMBOL(__debugger_break_match
);
80 EXPORT_SYMBOL(__debugger_fault_handler
);
83 /* Transactional Memory trap debug */
85 #define TM_DEBUG(x...) printk(KERN_INFO x)
87 #define TM_DEBUG(x...) do { } while(0)
91 * Trap & Exception support
94 #ifdef CONFIG_PMAC_BACKLIGHT
95 static void pmac_backlight_unblank(void)
97 mutex_lock(&pmac_backlight_mutex
);
99 struct backlight_properties
*props
;
101 props
= &pmac_backlight
->props
;
102 props
->brightness
= props
->max_brightness
;
103 props
->power
= FB_BLANK_UNBLANK
;
104 backlight_update_status(pmac_backlight
);
106 mutex_unlock(&pmac_backlight_mutex
);
109 static inline void pmac_backlight_unblank(void) { }
112 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
113 static int die_owner
= -1;
114 static unsigned int die_nest_count
;
115 static int die_counter
;
117 static unsigned __kprobes
long oops_begin(struct pt_regs
*regs
)
127 /* racy, but better than risking deadlock. */
128 raw_local_irq_save(flags
);
129 cpu
= smp_processor_id();
130 if (!arch_spin_trylock(&die_lock
)) {
131 if (cpu
== die_owner
)
132 /* nested oops. should stop eventually */;
134 arch_spin_lock(&die_lock
);
140 if (machine_is(powermac
))
141 pmac_backlight_unblank();
145 static void __kprobes
oops_end(unsigned long flags
, struct pt_regs
*regs
,
150 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
155 /* Nest count reaches zero, release the lock. */
156 arch_spin_unlock(&die_lock
);
157 raw_local_irq_restore(flags
);
159 crash_fadump(regs
, "die oops");
162 * A system reset (0x100) is a request to dump, so we always send
163 * it through the crashdump code.
165 if (kexec_should_crash(current
) || (TRAP(regs
) == 0x100)) {
169 * We aren't the primary crash CPU. We need to send it
170 * to a holding pattern to avoid it ending up in the panic
173 crash_kexec_secondary(regs
);
180 * While our oops output is serialised by a spinlock, output
181 * from panic() called below can race and corrupt it. If we
182 * know we are going to panic, delay for 1 second so we have a
183 * chance to get clean backtraces from all CPUs that are oopsing.
185 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
186 is_global_init(current
)) {
187 mdelay(MSEC_PER_SEC
);
191 panic("Fatal exception in interrupt");
193 panic("Fatal exception");
197 static int __kprobes
__die(const char *str
, struct pt_regs
*regs
, long err
)
199 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
200 #ifdef CONFIG_PREEMPT
204 printk("SMP NR_CPUS=%d ", NR_CPUS
);
206 if (debug_pagealloc_enabled())
207 printk("DEBUG_PAGEALLOC ");
211 printk("%s\n", ppc_md
.name
? ppc_md
.name
: "");
213 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
222 void die(const char *str
, struct pt_regs
*regs
, long err
)
224 unsigned long flags
= oops_begin(regs
);
226 if (__die(str
, regs
, err
))
228 oops_end(flags
, regs
, err
);
231 void user_single_step_siginfo(struct task_struct
*tsk
,
232 struct pt_regs
*regs
, siginfo_t
*info
)
234 memset(info
, 0, sizeof(*info
));
235 info
->si_signo
= SIGTRAP
;
236 info
->si_code
= TRAP_TRACE
;
237 info
->si_addr
= (void __user
*)regs
->nip
;
240 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
243 const char fmt32
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
244 "at %08lx nip %08lx lr %08lx code %x\n";
245 const char fmt64
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
246 "at %016lx nip %016lx lr %016lx code %x\n";
248 if (!user_mode(regs
)) {
249 die("Exception in kernel mode", regs
, signr
);
253 if (show_unhandled_signals
&& unhandled_signal(current
, signr
)) {
254 printk_ratelimited(regs
->msr
& MSR_64BIT
? fmt64
: fmt32
,
255 current
->comm
, current
->pid
, signr
,
256 addr
, regs
->nip
, regs
->link
, code
);
259 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
262 current
->thread
.trap_nr
= code
;
263 memset(&info
, 0, sizeof(info
));
264 info
.si_signo
= signr
;
266 info
.si_addr
= (void __user
*) addr
;
267 force_sig_info(signr
, &info
, current
);
271 void system_reset_exception(struct pt_regs
*regs
)
273 /* See if any machine dependent calls */
274 if (ppc_md
.system_reset_exception
) {
275 if (ppc_md
.system_reset_exception(regs
))
279 die("System Reset", regs
, SIGABRT
);
281 /* Must die if the interrupt is not recoverable */
282 if (!(regs
->msr
& MSR_RI
))
283 panic("Unrecoverable System Reset");
285 /* What should we do here? We could issue a shutdown or hard reset. */
289 * This function is called in real mode. Strictly no printk's please.
291 * regs->nip and regs->msr contains srr0 and ssr1.
293 long machine_check_early(struct pt_regs
*regs
)
297 __this_cpu_inc(irq_stat
.mce_exceptions
);
299 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
301 if (cur_cpu_spec
&& cur_cpu_spec
->machine_check_early
)
302 handled
= cur_cpu_spec
->machine_check_early(regs
);
306 long hmi_exception_realmode(struct pt_regs
*regs
)
308 __this_cpu_inc(irq_stat
.hmi_exceptions
);
310 if (ppc_md
.hmi_exception_early
)
311 ppc_md
.hmi_exception_early(regs
);
319 * I/O accesses can cause machine checks on powermacs.
320 * Check if the NIP corresponds to the address of a sync
321 * instruction for which there is an entry in the exception
323 * Note that the 601 only takes a machine check on TEA
324 * (transfer error ack) signal assertion, and does not
325 * set any of the top 16 bits of SRR1.
328 static inline int check_io_access(struct pt_regs
*regs
)
331 unsigned long msr
= regs
->msr
;
332 const struct exception_table_entry
*entry
;
333 unsigned int *nip
= (unsigned int *)regs
->nip
;
335 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
336 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
338 * Check that it's a sync instruction, or somewhere
339 * in the twi; isync; nop sequence that inb/inw/inl uses.
340 * As the address is in the exception table
341 * we should be able to read the instr there.
342 * For the debug message, we look at the preceding
345 if (*nip
== 0x60000000) /* nop */
347 else if (*nip
== 0x4c00012c) /* isync */
349 if (*nip
== 0x7c0004ac || (*nip
>> 26) == 3) {
354 rb
= (*nip
>> 11) & 0x1f;
355 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
356 (*nip
& 0x100)? "OUT to": "IN from",
357 regs
->gpr
[rb
] - _IO_BASE
, nip
);
359 regs
->nip
= entry
->fixup
;
363 #endif /* CONFIG_PPC32 */
367 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
368 /* On 4xx, the reason for the machine check or program exception
370 #define get_reason(regs) ((regs)->dsisr)
371 #ifndef CONFIG_FSL_BOOKE
372 #define get_mc_reason(regs) ((regs)->dsisr)
374 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
376 #define REASON_FP ESR_FP
377 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
378 #define REASON_PRIVILEGED ESR_PPR
379 #define REASON_TRAP ESR_PTR
381 /* single-step stuff */
382 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
383 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
386 /* On non-4xx, the reason for the machine check or program
387 exception is in the MSR. */
388 #define get_reason(regs) ((regs)->msr)
389 #define get_mc_reason(regs) ((regs)->msr)
390 #define REASON_TM 0x200000
391 #define REASON_FP 0x100000
392 #define REASON_ILLEGAL 0x80000
393 #define REASON_PRIVILEGED 0x40000
394 #define REASON_TRAP 0x20000
396 #define single_stepping(regs) ((regs)->msr & MSR_SE)
397 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
400 #if defined(CONFIG_4xx)
401 int machine_check_4xx(struct pt_regs
*regs
)
403 unsigned long reason
= get_mc_reason(regs
);
405 if (reason
& ESR_IMCP
) {
406 printk("Instruction");
407 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
410 printk(" machine check in kernel mode.\n");
415 int machine_check_440A(struct pt_regs
*regs
)
417 unsigned long reason
= get_mc_reason(regs
);
419 printk("Machine check in kernel mode.\n");
420 if (reason
& ESR_IMCP
){
421 printk("Instruction Synchronous Machine Check exception\n");
422 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
425 u32 mcsr
= mfspr(SPRN_MCSR
);
427 printk("Instruction Read PLB Error\n");
429 printk("Data Read PLB Error\n");
431 printk("Data Write PLB Error\n");
432 if (mcsr
& MCSR_TLBP
)
433 printk("TLB Parity Error\n");
434 if (mcsr
& MCSR_ICP
){
435 flush_instruction_cache();
436 printk("I-Cache Parity Error\n");
438 if (mcsr
& MCSR_DCSP
)
439 printk("D-Cache Search Parity Error\n");
440 if (mcsr
& MCSR_DCFP
)
441 printk("D-Cache Flush Parity Error\n");
442 if (mcsr
& MCSR_IMPE
)
443 printk("Machine Check exception is imprecise\n");
446 mtspr(SPRN_MCSR
, mcsr
);
451 int machine_check_47x(struct pt_regs
*regs
)
453 unsigned long reason
= get_mc_reason(regs
);
456 printk(KERN_ERR
"Machine check in kernel mode.\n");
457 if (reason
& ESR_IMCP
) {
459 "Instruction Synchronous Machine Check exception\n");
460 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
463 mcsr
= mfspr(SPRN_MCSR
);
465 printk(KERN_ERR
"Instruction Read PLB Error\n");
467 printk(KERN_ERR
"Data Read PLB Error\n");
469 printk(KERN_ERR
"Data Write PLB Error\n");
470 if (mcsr
& MCSR_TLBP
)
471 printk(KERN_ERR
"TLB Parity Error\n");
472 if (mcsr
& MCSR_ICP
) {
473 flush_instruction_cache();
474 printk(KERN_ERR
"I-Cache Parity Error\n");
476 if (mcsr
& MCSR_DCSP
)
477 printk(KERN_ERR
"D-Cache Search Parity Error\n");
478 if (mcsr
& PPC47x_MCSR_GPR
)
479 printk(KERN_ERR
"GPR Parity Error\n");
480 if (mcsr
& PPC47x_MCSR_FPR
)
481 printk(KERN_ERR
"FPR Parity Error\n");
482 if (mcsr
& PPC47x_MCSR_IPR
)
483 printk(KERN_ERR
"Machine Check exception is imprecise\n");
486 mtspr(SPRN_MCSR
, mcsr
);
490 #elif defined(CONFIG_E500)
491 int machine_check_e500mc(struct pt_regs
*regs
)
493 unsigned long mcsr
= mfspr(SPRN_MCSR
);
494 unsigned long reason
= mcsr
;
497 if (reason
& MCSR_LD
) {
498 recoverable
= fsl_rio_mcheck_exception(regs
);
499 if (recoverable
== 1)
503 printk("Machine check in kernel mode.\n");
504 printk("Caused by (from MCSR=%lx): ", reason
);
506 if (reason
& MCSR_MCP
)
507 printk("Machine Check Signal\n");
509 if (reason
& MCSR_ICPERR
) {
510 printk("Instruction Cache Parity Error\n");
513 * This is recoverable by invalidating the i-cache.
515 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
516 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
520 * This will generally be accompanied by an instruction
521 * fetch error report -- only treat MCSR_IF as fatal
522 * if it wasn't due to an L1 parity error.
527 if (reason
& MCSR_DCPERR_MC
) {
528 printk("Data Cache Parity Error\n");
531 * In write shadow mode we auto-recover from the error, but it
532 * may still get logged and cause a machine check. We should
533 * only treat the non-write shadow case as non-recoverable.
535 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
539 if (reason
& MCSR_L2MMU_MHIT
) {
540 printk("Hit on multiple TLB entries\n");
544 if (reason
& MCSR_NMI
)
545 printk("Non-maskable interrupt\n");
547 if (reason
& MCSR_IF
) {
548 printk("Instruction Fetch Error Report\n");
552 if (reason
& MCSR_LD
) {
553 printk("Load Error Report\n");
557 if (reason
& MCSR_ST
) {
558 printk("Store Error Report\n");
562 if (reason
& MCSR_LDG
) {
563 printk("Guarded Load Error Report\n");
567 if (reason
& MCSR_TLBSYNC
)
568 printk("Simultaneous tlbsync operations\n");
570 if (reason
& MCSR_BSL2_ERR
) {
571 printk("Level 2 Cache Error\n");
575 if (reason
& MCSR_MAV
) {
578 addr
= mfspr(SPRN_MCAR
);
579 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
581 printk("Machine Check %s Address: %#llx\n",
582 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
586 mtspr(SPRN_MCSR
, mcsr
);
587 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
590 int machine_check_e500(struct pt_regs
*regs
)
592 unsigned long reason
= get_mc_reason(regs
);
594 if (reason
& MCSR_BUS_RBERR
) {
595 if (fsl_rio_mcheck_exception(regs
))
597 if (fsl_pci_mcheck_exception(regs
))
601 printk("Machine check in kernel mode.\n");
602 printk("Caused by (from MCSR=%lx): ", reason
);
604 if (reason
& MCSR_MCP
)
605 printk("Machine Check Signal\n");
606 if (reason
& MCSR_ICPERR
)
607 printk("Instruction Cache Parity Error\n");
608 if (reason
& MCSR_DCP_PERR
)
609 printk("Data Cache Push Parity Error\n");
610 if (reason
& MCSR_DCPERR
)
611 printk("Data Cache Parity Error\n");
612 if (reason
& MCSR_BUS_IAERR
)
613 printk("Bus - Instruction Address Error\n");
614 if (reason
& MCSR_BUS_RAERR
)
615 printk("Bus - Read Address Error\n");
616 if (reason
& MCSR_BUS_WAERR
)
617 printk("Bus - Write Address Error\n");
618 if (reason
& MCSR_BUS_IBERR
)
619 printk("Bus - Instruction Data Error\n");
620 if (reason
& MCSR_BUS_RBERR
)
621 printk("Bus - Read Data Bus Error\n");
622 if (reason
& MCSR_BUS_WBERR
)
623 printk("Bus - Write Data Bus Error\n");
624 if (reason
& MCSR_BUS_IPERR
)
625 printk("Bus - Instruction Parity Error\n");
626 if (reason
& MCSR_BUS_RPERR
)
627 printk("Bus - Read Parity Error\n");
632 int machine_check_generic(struct pt_regs
*regs
)
636 #elif defined(CONFIG_E200)
637 int machine_check_e200(struct pt_regs
*regs
)
639 unsigned long reason
= get_mc_reason(regs
);
641 printk("Machine check in kernel mode.\n");
642 printk("Caused by (from MCSR=%lx): ", reason
);
644 if (reason
& MCSR_MCP
)
645 printk("Machine Check Signal\n");
646 if (reason
& MCSR_CP_PERR
)
647 printk("Cache Push Parity Error\n");
648 if (reason
& MCSR_CPERR
)
649 printk("Cache Parity Error\n");
650 if (reason
& MCSR_EXCP_ERR
)
651 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
652 if (reason
& MCSR_BUS_IRERR
)
653 printk("Bus - Read Bus Error on instruction fetch\n");
654 if (reason
& MCSR_BUS_DRERR
)
655 printk("Bus - Read Bus Error on data load\n");
656 if (reason
& MCSR_BUS_WRERR
)
657 printk("Bus - Write Bus Error on buffered store or cache line push\n");
662 int machine_check_generic(struct pt_regs
*regs
)
664 unsigned long reason
= get_mc_reason(regs
);
666 printk("Machine check in kernel mode.\n");
667 printk("Caused by (from SRR1=%lx): ", reason
);
668 switch (reason
& 0x601F0000) {
670 printk("Machine check signal\n");
672 case 0: /* for 601 */
674 case 0x140000: /* 7450 MSS error and TEA */
675 printk("Transfer error ack signal\n");
678 printk("Data parity error signal\n");
681 printk("Address parity error signal\n");
684 printk("L1 Data Cache error\n");
687 printk("L1 Instruction Cache error\n");
690 printk("L2 data cache parity error\n");
693 printk("Unknown values in msr\n");
697 #endif /* everything else */
699 void machine_check_exception(struct pt_regs
*regs
)
701 enum ctx_state prev_state
= exception_enter();
704 __this_cpu_inc(irq_stat
.mce_exceptions
);
706 /* See if any machine dependent calls. In theory, we would want
707 * to call the CPU first, and call the ppc_md. one if the CPU
708 * one returns a positive number. However there is existing code
709 * that assumes the board gets a first chance, so let's keep it
710 * that way for now and fix things later. --BenH.
712 if (ppc_md
.machine_check_exception
)
713 recover
= ppc_md
.machine_check_exception(regs
);
714 else if (cur_cpu_spec
->machine_check
)
715 recover
= cur_cpu_spec
->machine_check(regs
);
720 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
721 /* the qspan pci read routines can cause machine checks -- Cort
723 * yuck !!! that totally needs to go away ! There are better ways
724 * to deal with that than having a wart in the mcheck handler.
727 bad_page_fault(regs
, regs
->dar
, SIGBUS
);
731 if (debugger_fault_handler(regs
))
734 if (check_io_access(regs
))
737 die("Machine check", regs
, SIGBUS
);
739 /* Must die if the interrupt is not recoverable */
740 if (!(regs
->msr
& MSR_RI
))
741 panic("Unrecoverable Machine check");
744 exception_exit(prev_state
);
747 void SMIException(struct pt_regs
*regs
)
749 die("System Management Interrupt", regs
, SIGABRT
);
752 void handle_hmi_exception(struct pt_regs
*regs
)
754 struct pt_regs
*old_regs
;
756 old_regs
= set_irq_regs(regs
);
759 if (ppc_md
.handle_hmi_exception
)
760 ppc_md
.handle_hmi_exception(regs
);
763 set_irq_regs(old_regs
);
766 void unknown_exception(struct pt_regs
*regs
)
768 enum ctx_state prev_state
= exception_enter();
770 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
771 regs
->nip
, regs
->msr
, regs
->trap
);
773 _exception(SIGTRAP
, regs
, 0, 0);
775 exception_exit(prev_state
);
778 void instruction_breakpoint_exception(struct pt_regs
*regs
)
780 enum ctx_state prev_state
= exception_enter();
782 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
783 5, SIGTRAP
) == NOTIFY_STOP
)
785 if (debugger_iabr_match(regs
))
787 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
790 exception_exit(prev_state
);
793 void RunModeException(struct pt_regs
*regs
)
795 _exception(SIGTRAP
, regs
, 0, 0);
798 void __kprobes
single_step_exception(struct pt_regs
*regs
)
800 enum ctx_state prev_state
= exception_enter();
802 clear_single_step(regs
);
804 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
805 5, SIGTRAP
) == NOTIFY_STOP
)
807 if (debugger_sstep(regs
))
810 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
813 exception_exit(prev_state
);
817 * After we have successfully emulated an instruction, we have to
818 * check if the instruction was being single-stepped, and if so,
819 * pretend we got a single-step exception. This was pointed out
820 * by Kumar Gala. -- paulus
822 static void emulate_single_step(struct pt_regs
*regs
)
824 if (single_stepping(regs
))
825 single_step_exception(regs
);
828 static inline int __parse_fpscr(unsigned long fpscr
)
832 /* Invalid operation */
833 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
837 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
841 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
845 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
849 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
855 static void parse_fpe(struct pt_regs
*regs
)
859 flush_fp_to_thread(current
);
861 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
863 _exception(SIGFPE
, regs
, code
, regs
->nip
);
867 * Illegal instruction emulation support. Originally written to
868 * provide the PVR to user applications using the mfspr rd, PVR.
869 * Return non-zero if we can't emulate, or -EFAULT if the associated
870 * memory access caused an access fault. Return zero on success.
872 * There are a couple of ways to do this, either "decode" the instruction
873 * or directly match lots of bits. In this case, matching lots of
874 * bits is faster and easier.
877 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
879 u8 rT
= (instword
>> 21) & 0x1f;
880 u8 rA
= (instword
>> 16) & 0x1f;
881 u8 NB_RB
= (instword
>> 11) & 0x1f;
886 /* Early out if we are an invalid form of lswx */
887 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
888 if ((rT
== rA
) || (rT
== NB_RB
))
891 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
893 switch (instword
& PPC_INST_STRING_MASK
) {
897 num_bytes
= regs
->xer
& 0x7f;
901 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
907 while (num_bytes
!= 0)
910 u32 shift
= 8 * (3 - (pos
& 0x3));
912 /* if process is 32-bit, clear upper 32 bits of EA */
913 if ((regs
->msr
& MSR_64BIT
) == 0)
916 switch ((instword
& PPC_INST_STRING_MASK
)) {
919 if (get_user(val
, (u8 __user
*)EA
))
921 /* first time updating this reg,
925 regs
->gpr
[rT
] |= val
<< shift
;
929 val
= regs
->gpr
[rT
] >> shift
;
930 if (put_user(val
, (u8 __user
*)EA
))
934 /* move EA to next address */
938 /* manage our position within the register */
949 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
954 ra
= (instword
>> 16) & 0x1f;
955 rs
= (instword
>> 21) & 0x1f;
958 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
959 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
960 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
966 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
968 u8 rT
= (instword
>> 21) & 0x1f;
969 u8 rA
= (instword
>> 16) & 0x1f;
970 u8 rB
= (instword
>> 11) & 0x1f;
971 u8 BC
= (instword
>> 6) & 0x1f;
975 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
976 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
978 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
983 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
984 static inline bool tm_abort_check(struct pt_regs
*regs
, int cause
)
986 /* If we're emulating a load/store in an active transaction, we cannot
987 * emulate it as the kernel operates in transaction suspended context.
988 * We need to abort the transaction. This creates a persistent TM
989 * abort so tell the user what caused it with a new code.
991 if (MSR_TM_TRANSACTIONAL(regs
->msr
)) {
999 static inline bool tm_abort_check(struct pt_regs
*regs
, int reason
)
1005 static int emulate_instruction(struct pt_regs
*regs
)
1010 if (!user_mode(regs
))
1012 CHECK_FULL_REGS(regs
);
1014 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
1017 /* Emulate the mfspr rD, PVR. */
1018 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
1019 PPC_WARN_EMULATED(mfpvr
, regs
);
1020 rd
= (instword
>> 21) & 0x1f;
1021 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
1025 /* Emulating the dcba insn is just a no-op. */
1026 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
1027 PPC_WARN_EMULATED(dcba
, regs
);
1031 /* Emulate the mcrxr insn. */
1032 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
1033 int shift
= (instword
>> 21) & 0x1c;
1034 unsigned long msk
= 0xf0000000UL
>> shift
;
1036 PPC_WARN_EMULATED(mcrxr
, regs
);
1037 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
1038 regs
->xer
&= ~0xf0000000UL
;
1042 /* Emulate load/store string insn. */
1043 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
1044 if (tm_abort_check(regs
,
1045 TM_CAUSE_EMULATE
| TM_CAUSE_PERSISTENT
))
1047 PPC_WARN_EMULATED(string
, regs
);
1048 return emulate_string_inst(regs
, instword
);
1051 /* Emulate the popcntb (Population Count Bytes) instruction. */
1052 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
1053 PPC_WARN_EMULATED(popcntb
, regs
);
1054 return emulate_popcntb_inst(regs
, instword
);
1057 /* Emulate isel (Integer Select) instruction */
1058 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
1059 PPC_WARN_EMULATED(isel
, regs
);
1060 return emulate_isel(regs
, instword
);
1063 /* Emulate sync instruction variants */
1064 if ((instword
& PPC_INST_SYNC_MASK
) == PPC_INST_SYNC
) {
1065 PPC_WARN_EMULATED(sync
, regs
);
1066 asm volatile("sync");
1071 /* Emulate the mfspr rD, DSCR. */
1072 if ((((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
) ==
1073 PPC_INST_MFSPR_DSCR_USER
) ||
1074 ((instword
& PPC_INST_MFSPR_DSCR_MASK
) ==
1075 PPC_INST_MFSPR_DSCR
)) &&
1076 cpu_has_feature(CPU_FTR_DSCR
)) {
1077 PPC_WARN_EMULATED(mfdscr
, regs
);
1078 rd
= (instword
>> 21) & 0x1f;
1079 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
1082 /* Emulate the mtspr DSCR, rD. */
1083 if ((((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
) ==
1084 PPC_INST_MTSPR_DSCR_USER
) ||
1085 ((instword
& PPC_INST_MTSPR_DSCR_MASK
) ==
1086 PPC_INST_MTSPR_DSCR
)) &&
1087 cpu_has_feature(CPU_FTR_DSCR
)) {
1088 PPC_WARN_EMULATED(mtdscr
, regs
);
1089 rd
= (instword
>> 21) & 0x1f;
1090 current
->thread
.dscr
= regs
->gpr
[rd
];
1091 current
->thread
.dscr_inherit
= 1;
1092 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
1100 int is_valid_bugaddr(unsigned long addr
)
1102 return is_kernel_addr(addr
);
1105 #ifdef CONFIG_MATH_EMULATION
1106 static int emulate_math(struct pt_regs
*regs
)
1109 extern int do_mathemu(struct pt_regs
*regs
);
1111 ret
= do_mathemu(regs
);
1113 PPC_WARN_EMULATED(math
, regs
);
1117 emulate_single_step(regs
);
1121 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1122 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1126 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1133 static inline int emulate_math(struct pt_regs
*regs
) { return -1; }
1136 void __kprobes
program_check_exception(struct pt_regs
*regs
)
1138 enum ctx_state prev_state
= exception_enter();
1139 unsigned int reason
= get_reason(regs
);
1141 /* We can now get here via a FP Unavailable exception if the core
1142 * has no FPU, in that case the reason flags will be 0 */
1144 if (reason
& REASON_FP
) {
1145 /* IEEE FP exception */
1149 if (reason
& REASON_TRAP
) {
1150 /* Debugger is first in line to stop recursive faults in
1151 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1152 if (debugger_bpt(regs
))
1155 /* trap exception */
1156 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1160 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1161 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1165 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1168 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1169 if (reason
& REASON_TM
) {
1170 /* This is a TM "Bad Thing Exception" program check.
1172 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1173 * transition in TM states.
1174 * - A trechkpt is attempted when transactional.
1175 * - A treclaim is attempted when non transactional.
1176 * - A tend is illegally attempted.
1177 * - writing a TM SPR when transactional.
1179 if (!user_mode(regs
) &&
1180 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1184 /* If usermode caused this, it's done something illegal and
1185 * gets a SIGILL slap on the wrist. We call it an illegal
1186 * operand to distinguish from the instruction just being bad
1187 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1188 * illegal /placement/ of a valid instruction.
1190 if (user_mode(regs
)) {
1191 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1194 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1195 "at %lx (msr 0x%x)\n", regs
->nip
, reason
);
1196 die("Unrecoverable exception", regs
, SIGABRT
);
1202 * If we took the program check in the kernel skip down to sending a
1203 * SIGILL. The subsequent cases all relate to emulating instructions
1204 * which we should only do for userspace. We also do not want to enable
1205 * interrupts for kernel faults because that might lead to further
1206 * faults, and loose the context of the original exception.
1208 if (!user_mode(regs
))
1211 /* We restore the interrupt state now */
1212 if (!arch_irq_disabled_regs(regs
))
1215 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1216 * but there seems to be a hardware bug on the 405GP (RevD)
1217 * that means ESR is sometimes set incorrectly - either to
1218 * ESR_DST (!?) or 0. In the process of chasing this with the
1219 * hardware people - not sure if it can happen on any illegal
1220 * instruction or only on FP instructions, whether there is a
1221 * pattern to occurrences etc. -dgibson 31/Mar/2003
1223 if (!emulate_math(regs
))
1226 /* Try to emulate it if we should. */
1227 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1228 switch (emulate_instruction(regs
)) {
1231 emulate_single_step(regs
);
1234 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1240 if (reason
& REASON_PRIVILEGED
)
1241 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1243 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1246 exception_exit(prev_state
);
1250 * This occurs when running in hypervisor mode on POWER6 or later
1251 * and an illegal instruction is encountered.
1253 void __kprobes
emulation_assist_interrupt(struct pt_regs
*regs
)
1255 regs
->msr
|= REASON_ILLEGAL
;
1256 program_check_exception(regs
);
1259 void alignment_exception(struct pt_regs
*regs
)
1261 enum ctx_state prev_state
= exception_enter();
1262 int sig
, code
, fixed
= 0;
1264 /* We restore the interrupt state now */
1265 if (!arch_irq_disabled_regs(regs
))
1268 if (tm_abort_check(regs
, TM_CAUSE_ALIGNMENT
| TM_CAUSE_PERSISTENT
))
1271 /* we don't implement logging of alignment exceptions */
1272 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1273 fixed
= fix_alignment(regs
);
1276 regs
->nip
+= 4; /* skip over emulated instruction */
1277 emulate_single_step(regs
);
1281 /* Operand address was bad */
1282 if (fixed
== -EFAULT
) {
1289 if (user_mode(regs
))
1290 _exception(sig
, regs
, code
, regs
->dar
);
1292 bad_page_fault(regs
, regs
->dar
, sig
);
1295 exception_exit(prev_state
);
1298 void StackOverflow(struct pt_regs
*regs
)
1300 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
1301 current
, regs
->gpr
[1]);
1304 panic("kernel stack overflow");
1307 void nonrecoverable_exception(struct pt_regs
*regs
)
1309 printk(KERN_ERR
"Non-recoverable exception at PC=%lx MSR=%lx\n",
1310 regs
->nip
, regs
->msr
);
1312 die("nonrecoverable exception", regs
, SIGKILL
);
1315 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1317 enum ctx_state prev_state
= exception_enter();
1319 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1320 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1321 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1323 exception_exit(prev_state
);
1326 void altivec_unavailable_exception(struct pt_regs
*regs
)
1328 enum ctx_state prev_state
= exception_enter();
1330 if (user_mode(regs
)) {
1331 /* A user program has executed an altivec instruction,
1332 but this kernel doesn't support altivec. */
1333 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1337 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1338 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1339 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1342 exception_exit(prev_state
);
1345 void vsx_unavailable_exception(struct pt_regs
*regs
)
1347 if (user_mode(regs
)) {
1348 /* A user program has executed an vsx instruction,
1349 but this kernel doesn't support vsx. */
1350 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1354 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1355 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1356 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1360 void facility_unavailable_exception(struct pt_regs
*regs
)
1362 static char *facility_strings
[] = {
1363 [FSCR_FP_LG
] = "FPU",
1364 [FSCR_VECVSX_LG
] = "VMX/VSX",
1365 [FSCR_DSCR_LG
] = "DSCR",
1366 [FSCR_PM_LG
] = "PMU SPRs",
1367 [FSCR_BHRB_LG
] = "BHRB",
1368 [FSCR_TM_LG
] = "TM",
1369 [FSCR_EBB_LG
] = "EBB",
1370 [FSCR_TAR_LG
] = "TAR",
1372 char *facility
= "unknown";
1378 hv
= (regs
->trap
== 0xf80);
1380 value
= mfspr(SPRN_HFSCR
);
1382 value
= mfspr(SPRN_FSCR
);
1384 status
= value
>> 56;
1385 if (status
== FSCR_DSCR_LG
) {
1387 * User is accessing the DSCR register using the problem
1388 * state only SPR number (0x03) either through a mfspr or
1389 * a mtspr instruction. If it is a write attempt through
1390 * a mtspr, then we set the inherit bit. This also allows
1391 * the user to write or read the register directly in the
1392 * future by setting via the FSCR DSCR bit. But in case it
1393 * is a read DSCR attempt through a mfspr instruction, we
1394 * just emulate the instruction instead. This code path will
1395 * always emulate all the mfspr instructions till the user
1396 * has attempted atleast one mtspr instruction. This way it
1397 * preserves the same behaviour when the user is accessing
1398 * the DSCR through privilege level only SPR number (0x11)
1399 * which is emulated through illegal instruction exception.
1400 * We always leave HFSCR DSCR set.
1402 if (get_user(instword
, (u32 __user
*)(regs
->nip
))) {
1403 pr_err("Failed to fetch the user instruction\n");
1407 /* Write into DSCR (mtspr 0x03, RS) */
1408 if ((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
)
1409 == PPC_INST_MTSPR_DSCR_USER
) {
1410 rd
= (instword
>> 21) & 0x1f;
1411 current
->thread
.dscr
= regs
->gpr
[rd
];
1412 current
->thread
.dscr_inherit
= 1;
1413 mtspr(SPRN_FSCR
, value
| FSCR_DSCR
);
1416 /* Read from DSCR (mfspr RT, 0x03) */
1417 if ((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
)
1418 == PPC_INST_MFSPR_DSCR_USER
) {
1419 if (emulate_instruction(regs
)) {
1420 pr_err("DSCR based mfspr emulation failed\n");
1424 emulate_single_step(regs
);
1429 if ((status
< ARRAY_SIZE(facility_strings
)) &&
1430 facility_strings
[status
])
1431 facility
= facility_strings
[status
];
1433 /* We restore the interrupt state now */
1434 if (!arch_irq_disabled_regs(regs
))
1438 "%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
1439 hv
? "Hypervisor " : "", facility
, regs
->nip
, regs
->msr
);
1441 if (user_mode(regs
)) {
1442 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1446 die("Unexpected facility unavailable exception", regs
, SIGABRT
);
1450 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1452 void fp_unavailable_tm(struct pt_regs
*regs
)
1454 /* Note: This does not handle any kind of FP laziness. */
1456 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1457 regs
->nip
, regs
->msr
);
1459 /* We can only have got here if the task started using FP after
1460 * beginning the transaction. So, the transactional regs are just a
1461 * copy of the checkpointed ones. But, we still need to recheckpoint
1462 * as we're enabling FP for the process; it will return, abort the
1463 * transaction, and probably retry but now with FP enabled. So the
1464 * checkpointed FP registers need to be loaded.
1466 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1467 /* Reclaim didn't save out any FPRs to transact_fprs. */
1469 /* Enable FP for the task: */
1470 regs
->msr
|= (MSR_FP
| current
->thread
.fpexc_mode
);
1472 /* This loads and recheckpoints the FP registers from
1473 * thread.fpr[]. They will remain in registers after the
1474 * checkpoint so we don't need to reload them after.
1475 * If VMX is in use, the VRs now hold checkpointed values,
1476 * so we don't want to load the VRs from the thread_struct.
1478 tm_recheckpoint(¤t
->thread
, MSR_FP
);
1480 /* If VMX is in use, get the transactional values back */
1481 if (regs
->msr
& MSR_VEC
) {
1482 do_load_up_transact_altivec(¤t
->thread
);
1483 /* At this point all the VSX state is loaded, so enable it */
1484 regs
->msr
|= MSR_VSX
;
1488 void altivec_unavailable_tm(struct pt_regs
*regs
)
1490 /* See the comments in fp_unavailable_tm(). This function operates
1494 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1496 regs
->nip
, regs
->msr
);
1497 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1498 regs
->msr
|= MSR_VEC
;
1499 tm_recheckpoint(¤t
->thread
, MSR_VEC
);
1500 current
->thread
.used_vr
= 1;
1502 if (regs
->msr
& MSR_FP
) {
1503 do_load_up_transact_fpu(¤t
->thread
);
1504 regs
->msr
|= MSR_VSX
;
1508 void vsx_unavailable_tm(struct pt_regs
*regs
)
1510 unsigned long orig_msr
= regs
->msr
;
1512 /* See the comments in fp_unavailable_tm(). This works similarly,
1513 * though we're loading both FP and VEC registers in here.
1515 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1516 * regs. Either way, set MSR_VSX.
1519 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1521 regs
->nip
, regs
->msr
);
1523 current
->thread
.used_vsr
= 1;
1525 /* If FP and VMX are already loaded, we have all the state we need */
1526 if ((orig_msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
)) {
1527 regs
->msr
|= MSR_VSX
;
1531 /* This reclaims FP and/or VR regs if they're already enabled */
1532 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1534 regs
->msr
|= MSR_VEC
| MSR_FP
| current
->thread
.fpexc_mode
|
1537 /* This loads & recheckpoints FP and VRs; but we have
1538 * to be sure not to overwrite previously-valid state.
1540 tm_recheckpoint(¤t
->thread
, regs
->msr
& ~orig_msr
);
1542 if (orig_msr
& MSR_FP
)
1543 do_load_up_transact_fpu(¤t
->thread
);
1544 if (orig_msr
& MSR_VEC
)
1545 do_load_up_transact_altivec(¤t
->thread
);
1547 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1549 void performance_monitor_exception(struct pt_regs
*regs
)
1551 __this_cpu_inc(irq_stat
.pmu_irqs
);
1557 void SoftwareEmulation(struct pt_regs
*regs
)
1559 CHECK_FULL_REGS(regs
);
1561 if (!user_mode(regs
)) {
1563 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1567 if (!emulate_math(regs
))
1570 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1572 #endif /* CONFIG_8xx */
1574 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1575 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1579 * Determine the cause of the debug event, clear the
1580 * event flags and send a trap to the handler. Torez
1582 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1583 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1584 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1585 current
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
1587 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
, TRAP_HWBKPT
,
1590 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1591 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1592 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
, TRAP_HWBKPT
,
1595 } else if (debug_status
& DBSR_IAC1
) {
1596 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
1597 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1598 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
, TRAP_HWBKPT
,
1601 } else if (debug_status
& DBSR_IAC2
) {
1602 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
1603 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
, TRAP_HWBKPT
,
1606 } else if (debug_status
& DBSR_IAC3
) {
1607 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
1608 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1609 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
, TRAP_HWBKPT
,
1612 } else if (debug_status
& DBSR_IAC4
) {
1613 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
1614 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
, TRAP_HWBKPT
,
1619 * At the point this routine was called, the MSR(DE) was turned off.
1620 * Check all other debug flags and see if that bit needs to be turned
1623 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1624 current
->thread
.debug
.dbcr1
))
1625 regs
->msr
|= MSR_DE
;
1627 /* Make sure the IDM flag is off */
1628 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1631 mtspr(SPRN_DBCR0
, current
->thread
.debug
.dbcr0
);
1634 void __kprobes
DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1636 current
->thread
.debug
.dbsr
= debug_status
;
1638 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1639 * on server, it stops on the target of the branch. In order to simulate
1640 * the server behaviour, we thus restart right away with a single step
1641 * instead of stopping here when hitting a BT
1643 if (debug_status
& DBSR_BT
) {
1644 regs
->msr
&= ~MSR_DE
;
1647 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1648 /* Clear the BT event */
1649 mtspr(SPRN_DBSR
, DBSR_BT
);
1651 /* Do the single step trick only when coming from userspace */
1652 if (user_mode(regs
)) {
1653 current
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
1654 current
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1655 regs
->msr
|= MSR_DE
;
1659 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1660 5, SIGTRAP
) == NOTIFY_STOP
) {
1663 if (debugger_sstep(regs
))
1665 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1666 regs
->msr
&= ~MSR_DE
;
1668 /* Disable instruction completion */
1669 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1670 /* Clear the instruction completion event */
1671 mtspr(SPRN_DBSR
, DBSR_IC
);
1673 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1674 5, SIGTRAP
) == NOTIFY_STOP
) {
1678 if (debugger_sstep(regs
))
1681 if (user_mode(regs
)) {
1682 current
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
1683 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1684 current
->thread
.debug
.dbcr1
))
1685 regs
->msr
|= MSR_DE
;
1687 /* Make sure the IDM bit is off */
1688 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1691 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1693 handle_debug(regs
, debug_status
);
1695 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1697 #if !defined(CONFIG_TAU_INT)
1698 void TAUException(struct pt_regs
*regs
)
1700 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1701 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
1703 #endif /* CONFIG_INT_TAU */
1705 #ifdef CONFIG_ALTIVEC
1706 void altivec_assist_exception(struct pt_regs
*regs
)
1710 if (!user_mode(regs
)) {
1711 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
1712 " at %lx\n", regs
->nip
);
1713 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
1716 flush_altivec_to_thread(current
);
1718 PPC_WARN_EMULATED(altivec
, regs
);
1719 err
= emulate_altivec(regs
);
1721 regs
->nip
+= 4; /* skip emulated instruction */
1722 emulate_single_step(regs
);
1726 if (err
== -EFAULT
) {
1727 /* got an error reading the instruction */
1728 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1730 /* didn't recognize the instruction */
1731 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1732 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
1733 "in %s at %lx\n", current
->comm
, regs
->nip
);
1734 current
->thread
.vr_state
.vscr
.u
[3] |= 0x10000;
1737 #endif /* CONFIG_ALTIVEC */
1739 #ifdef CONFIG_FSL_BOOKE
1740 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
1741 unsigned long error_code
)
1743 /* We treat cache locking instructions from the user
1744 * as priv ops, in the future we could try to do
1747 if (error_code
& (ESR_DLK
|ESR_ILK
))
1748 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1751 #endif /* CONFIG_FSL_BOOKE */
1754 void SPEFloatingPointException(struct pt_regs
*regs
)
1756 extern int do_spe_mathemu(struct pt_regs
*regs
);
1757 unsigned long spefscr
;
1762 flush_spe_to_thread(current
);
1764 spefscr
= current
->thread
.spefscr
;
1765 fpexc_mode
= current
->thread
.fpexc_mode
;
1767 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
1770 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
1773 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
1775 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
1778 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
1781 err
= do_spe_mathemu(regs
);
1783 regs
->nip
+= 4; /* skip emulated instruction */
1784 emulate_single_step(regs
);
1788 if (err
== -EFAULT
) {
1789 /* got an error reading the instruction */
1790 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1791 } else if (err
== -EINVAL
) {
1792 /* didn't recognize the instruction */
1793 printk(KERN_ERR
"unrecognized spe instruction "
1794 "in %s at %lx\n", current
->comm
, regs
->nip
);
1796 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1802 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
1804 extern int speround_handler(struct pt_regs
*regs
);
1808 if (regs
->msr
& MSR_SPE
)
1809 giveup_spe(current
);
1813 err
= speround_handler(regs
);
1815 regs
->nip
+= 4; /* skip emulated instruction */
1816 emulate_single_step(regs
);
1820 if (err
== -EFAULT
) {
1821 /* got an error reading the instruction */
1822 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1823 } else if (err
== -EINVAL
) {
1824 /* didn't recognize the instruction */
1825 printk(KERN_ERR
"unrecognized spe instruction "
1826 "in %s at %lx\n", current
->comm
, regs
->nip
);
1828 _exception(SIGFPE
, regs
, 0, regs
->nip
);
1835 * We enter here if we get an unrecoverable exception, that is, one
1836 * that happened at a point where the RI (recoverable interrupt) bit
1837 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1838 * we therefore lost state by taking this exception.
1840 void unrecoverable_exception(struct pt_regs
*regs
)
1842 printk(KERN_EMERG
"Unrecoverable exception %lx at %lx\n",
1843 regs
->trap
, regs
->nip
);
1844 die("Unrecoverable exception", regs
, SIGABRT
);
1847 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1849 * Default handler for a Watchdog exception,
1850 * spins until a reboot occurs
1852 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
1854 /* Generic WatchdogHandler, implement your own */
1855 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
1859 void WatchdogException(struct pt_regs
*regs
)
1861 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
1862 WatchdogHandler(regs
);
1867 * We enter here if we discover during exception entry that we are
1868 * running in supervisor mode with a userspace value in the stack pointer.
1870 void kernel_bad_stack(struct pt_regs
*regs
)
1872 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
1873 regs
->gpr
[1], regs
->nip
);
1874 die("Bad kernel stack pointer", regs
, SIGABRT
);
1877 void __init
trap_init(void)
1882 #ifdef CONFIG_PPC_EMULATED_STATS
1884 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1886 struct ppc_emulated ppc_emulated
= {
1887 #ifdef CONFIG_ALTIVEC
1888 WARN_EMULATED_SETUP(altivec
),
1890 WARN_EMULATED_SETUP(dcba
),
1891 WARN_EMULATED_SETUP(dcbz
),
1892 WARN_EMULATED_SETUP(fp_pair
),
1893 WARN_EMULATED_SETUP(isel
),
1894 WARN_EMULATED_SETUP(mcrxr
),
1895 WARN_EMULATED_SETUP(mfpvr
),
1896 WARN_EMULATED_SETUP(multiple
),
1897 WARN_EMULATED_SETUP(popcntb
),
1898 WARN_EMULATED_SETUP(spe
),
1899 WARN_EMULATED_SETUP(string
),
1900 WARN_EMULATED_SETUP(sync
),
1901 WARN_EMULATED_SETUP(unaligned
),
1902 #ifdef CONFIG_MATH_EMULATION
1903 WARN_EMULATED_SETUP(math
),
1906 WARN_EMULATED_SETUP(vsx
),
1909 WARN_EMULATED_SETUP(mfdscr
),
1910 WARN_EMULATED_SETUP(mtdscr
),
1911 WARN_EMULATED_SETUP(lq_stq
),
1915 u32 ppc_warn_emulated
;
1917 void ppc_warn_emulated_print(const char *type
)
1919 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
1923 static int __init
ppc_warn_emulated_init(void)
1925 struct dentry
*dir
, *d
;
1927 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
1929 if (!powerpc_debugfs_root
)
1932 dir
= debugfs_create_dir("emulated_instructions",
1933 powerpc_debugfs_root
);
1937 d
= debugfs_create_u32("do_warn", S_IRUGO
| S_IWUSR
, dir
,
1938 &ppc_warn_emulated
);
1942 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
1943 d
= debugfs_create_u32(entries
[i
].name
, S_IRUGO
| S_IWUSR
, dir
,
1944 (u32
*)&entries
[i
].val
.counter
);
1952 debugfs_remove_recursive(dir
);
1956 device_initcall(ppc_warn_emulated_init
);
1958 #endif /* CONFIG_PPC_EMULATED_STATS */