2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
23 #include <linux/pkeys.h>
24 #include <linux/stddef.h>
25 #include <linux/unistd.h>
26 #include <linux/ptrace.h>
27 #include <linux/user.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/extable.h>
31 #include <linux/module.h> /* print_modules */
32 #include <linux/prctl.h>
33 #include <linux/delay.h>
34 #include <linux/kprobes.h>
35 #include <linux/kexec.h>
36 #include <linux/backlight.h>
37 #include <linux/bug.h>
38 #include <linux/kdebug.h>
39 #include <linux/ratelimit.h>
40 #include <linux/context_tracking.h>
41 #include <linux/smp.h>
42 #include <linux/console.h>
43 #include <linux/kmsg_dump.h>
45 #include <asm/emulated_ops.h>
46 #include <asm/pgtable.h>
47 #include <linux/uaccess.h>
48 #include <asm/debugfs.h>
50 #include <asm/machdep.h>
54 #ifdef CONFIG_PMAC_BACKLIGHT
55 #include <asm/backlight.h>
58 #include <asm/firmware.h>
59 #include <asm/processor.h>
62 #include <asm/kexec.h>
63 #include <asm/ppc-opcode.h>
65 #include <asm/fadump.h>
66 #include <asm/switch_to.h>
68 #include <asm/debug.h>
69 #include <asm/asm-prototypes.h>
71 #include <sysdev/fsl_pci.h>
72 #include <asm/kprobes.h>
73 #include <asm/stacktrace.h>
75 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
76 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
77 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
78 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
79 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
80 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
81 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
82 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
84 EXPORT_SYMBOL(__debugger
);
85 EXPORT_SYMBOL(__debugger_ipi
);
86 EXPORT_SYMBOL(__debugger_bpt
);
87 EXPORT_SYMBOL(__debugger_sstep
);
88 EXPORT_SYMBOL(__debugger_iabr_match
);
89 EXPORT_SYMBOL(__debugger_break_match
);
90 EXPORT_SYMBOL(__debugger_fault_handler
);
93 /* Transactional Memory trap debug */
95 #define TM_DEBUG(x...) printk(KERN_INFO x)
97 #define TM_DEBUG(x...) do { } while(0)
100 static const char *signame(int signr
)
103 case SIGBUS
: return "bus error";
104 case SIGFPE
: return "floating point exception";
105 case SIGILL
: return "illegal instruction";
106 case SIGSEGV
: return "segfault";
107 case SIGTRAP
: return "unhandled trap";
110 return "unknown signal";
114 * Trap & Exception support
117 #ifdef CONFIG_PMAC_BACKLIGHT
118 static void pmac_backlight_unblank(void)
120 mutex_lock(&pmac_backlight_mutex
);
121 if (pmac_backlight
) {
122 struct backlight_properties
*props
;
124 props
= &pmac_backlight
->props
;
125 props
->brightness
= props
->max_brightness
;
126 props
->power
= FB_BLANK_UNBLANK
;
127 backlight_update_status(pmac_backlight
);
129 mutex_unlock(&pmac_backlight_mutex
);
132 static inline void pmac_backlight_unblank(void) { }
136 * If oops/die is expected to crash the machine, return true here.
138 * This should not be expected to be 100% accurate, there may be
139 * notifiers registered or other unexpected conditions that may bring
140 * down the kernel. Or if the current process in the kernel is holding
141 * locks or has other critical state, the kernel may become effectively
144 bool die_will_crash(void)
146 if (should_fadump_crash())
148 if (kexec_should_crash(current
))
150 if (in_interrupt() || panic_on_oops
||
151 !current
->pid
|| is_global_init(current
))
157 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
158 static int die_owner
= -1;
159 static unsigned int die_nest_count
;
160 static int die_counter
;
162 extern void panic_flush_kmsg_start(void)
165 * These are mostly taken from kernel/panic.c, but tries to do
166 * relatively minimal work. Don't use delay functions (TB may
167 * be broken), don't crash dump (need to set a firmware log),
168 * don't run notifiers. We do want to get some information to
175 extern void panic_flush_kmsg_end(void)
177 printk_safe_flush_on_panic();
178 kmsg_dump(KMSG_DUMP_PANIC
);
181 console_flush_on_panic();
184 static unsigned long oops_begin(struct pt_regs
*regs
)
191 /* racy, but better than risking deadlock. */
192 raw_local_irq_save(flags
);
193 cpu
= smp_processor_id();
194 if (!arch_spin_trylock(&die_lock
)) {
195 if (cpu
== die_owner
)
196 /* nested oops. should stop eventually */;
198 arch_spin_lock(&die_lock
);
204 if (machine_is(powermac
))
205 pmac_backlight_unblank();
208 NOKPROBE_SYMBOL(oops_begin
);
210 static void oops_end(unsigned long flags
, struct pt_regs
*regs
,
214 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
218 if (!die_nest_count
) {
219 /* Nest count reaches zero, release the lock. */
221 arch_spin_unlock(&die_lock
);
223 raw_local_irq_restore(flags
);
226 * system_reset_excption handles debugger, crash dump, panic, for 0x100
228 if (TRAP(regs
) == 0x100)
231 crash_fadump(regs
, "die oops");
233 if (kexec_should_crash(current
))
240 * While our oops output is serialised by a spinlock, output
241 * from panic() called below can race and corrupt it. If we
242 * know we are going to panic, delay for 1 second so we have a
243 * chance to get clean backtraces from all CPUs that are oopsing.
245 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
246 is_global_init(current
)) {
247 mdelay(MSEC_PER_SEC
);
251 panic("Fatal exception");
254 NOKPROBE_SYMBOL(oops_end
);
256 static int __die(const char *str
, struct pt_regs
*regs
, long err
)
258 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
260 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN
))
265 if (IS_ENABLED(CONFIG_PREEMPT
))
268 if (IS_ENABLED(CONFIG_SMP
))
269 pr_cont("SMP NR_CPUS=%d ", NR_CPUS
);
271 if (debug_pagealloc_enabled())
272 pr_cont("DEBUG_PAGEALLOC ");
274 if (IS_ENABLED(CONFIG_NUMA
))
277 pr_cont("%s\n", ppc_md
.name
? ppc_md
.name
: "");
279 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
287 NOKPROBE_SYMBOL(__die
);
289 void die(const char *str
, struct pt_regs
*regs
, long err
)
294 * system_reset_excption handles debugger, crash dump, panic, for 0x100
296 if (TRAP(regs
) != 0x100) {
301 flags
= oops_begin(regs
);
302 if (__die(str
, regs
, err
))
304 oops_end(flags
, regs
, err
);
306 NOKPROBE_SYMBOL(die
);
308 void user_single_step_report(struct pt_regs
*regs
)
310 force_sig_fault(SIGTRAP
, TRAP_TRACE
, (void __user
*)regs
->nip
, current
);
313 static void show_signal_msg(int signr
, struct pt_regs
*regs
, int code
,
316 static DEFINE_RATELIMIT_STATE(rs
, DEFAULT_RATELIMIT_INTERVAL
,
317 DEFAULT_RATELIMIT_BURST
);
319 if (!show_unhandled_signals
)
322 if (!unhandled_signal(current
, signr
))
325 if (!__ratelimit(&rs
))
328 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
329 current
->comm
, current
->pid
, signame(signr
), signr
,
330 addr
, regs
->nip
, regs
->link
, code
);
332 print_vma_addr(KERN_CONT
" in ", regs
->nip
);
336 show_user_instructions(regs
);
339 static bool exception_common(int signr
, struct pt_regs
*regs
, int code
,
342 if (!user_mode(regs
)) {
343 die("Exception in kernel mode", regs
, signr
);
347 show_signal_msg(signr
, regs
, code
, addr
);
349 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
352 current
->thread
.trap_nr
= code
;
355 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need
356 * to capture the content, if the task gets killed.
358 thread_pkey_regs_save(¤t
->thread
);
363 void _exception_pkey(struct pt_regs
*regs
, unsigned long addr
, int key
)
365 if (!exception_common(SIGSEGV
, regs
, SEGV_PKUERR
, addr
))
368 force_sig_pkuerr((void __user
*) addr
, key
);
371 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
373 if (!exception_common(signr
, regs
, code
, addr
))
376 force_sig_fault(signr
, code
, (void __user
*)addr
, current
);
379 void system_reset_exception(struct pt_regs
*regs
)
382 * Avoid crashes in case of nested NMI exceptions. Recoverability
383 * is determined by RI and in_nmi
385 bool nested
= in_nmi();
389 __this_cpu_inc(irq_stat
.sreset_irqs
);
391 /* See if any machine dependent calls */
392 if (ppc_md
.system_reset_exception
) {
393 if (ppc_md
.system_reset_exception(regs
))
401 * A system reset is a request to dump, so we always send
402 * it through the crashdump code (if fadump or kdump are
405 crash_fadump(regs
, "System Reset");
410 * We aren't the primary crash CPU. We need to send it
411 * to a holding pattern to avoid it ending up in the panic
414 crash_kexec_secondary(regs
);
417 * No debugger or crash dump registered, print logs then
420 die("System Reset", regs
, SIGABRT
);
422 mdelay(2*MSEC_PER_SEC
); /* Wait a little while for others to print */
423 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
424 nmi_panic(regs
, "System Reset");
427 #ifdef CONFIG_PPC_BOOK3S_64
428 BUG_ON(get_paca()->in_nmi
== 0);
429 if (get_paca()->in_nmi
> 1)
430 nmi_panic(regs
, "Unrecoverable nested System Reset");
432 /* Must die if the interrupt is not recoverable */
433 if (!(regs
->msr
& MSR_RI
))
434 nmi_panic(regs
, "Unrecoverable System Reset");
439 /* What should we do here? We could issue a shutdown or hard reset. */
443 * I/O accesses can cause machine checks on powermacs.
444 * Check if the NIP corresponds to the address of a sync
445 * instruction for which there is an entry in the exception
447 * Note that the 601 only takes a machine check on TEA
448 * (transfer error ack) signal assertion, and does not
449 * set any of the top 16 bits of SRR1.
452 static inline int check_io_access(struct pt_regs
*regs
)
455 unsigned long msr
= regs
->msr
;
456 const struct exception_table_entry
*entry
;
457 unsigned int *nip
= (unsigned int *)regs
->nip
;
459 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
460 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
462 * Check that it's a sync instruction, or somewhere
463 * in the twi; isync; nop sequence that inb/inw/inl uses.
464 * As the address is in the exception table
465 * we should be able to read the instr there.
466 * For the debug message, we look at the preceding
469 if (*nip
== PPC_INST_NOP
)
471 else if (*nip
== PPC_INST_ISYNC
)
473 if (*nip
== PPC_INST_SYNC
|| (*nip
>> 26) == OP_TRAP
) {
477 rb
= (*nip
>> 11) & 0x1f;
478 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
479 (*nip
& 0x100)? "OUT to": "IN from",
480 regs
->gpr
[rb
] - _IO_BASE
, nip
);
482 regs
->nip
= extable_fixup(entry
);
486 #endif /* CONFIG_PPC32 */
490 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
491 /* On 4xx, the reason for the machine check or program exception
493 #define get_reason(regs) ((regs)->dsisr)
494 #define REASON_FP ESR_FP
495 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
496 #define REASON_PRIVILEGED ESR_PPR
497 #define REASON_TRAP ESR_PTR
499 /* single-step stuff */
500 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
501 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
502 #define clear_br_trace(regs) do {} while(0)
504 /* On non-4xx, the reason for the machine check or program
505 exception is in the MSR. */
506 #define get_reason(regs) ((regs)->msr)
507 #define REASON_TM SRR1_PROGTM
508 #define REASON_FP SRR1_PROGFPE
509 #define REASON_ILLEGAL SRR1_PROGILL
510 #define REASON_PRIVILEGED SRR1_PROGPRIV
511 #define REASON_TRAP SRR1_PROGTRAP
513 #define single_stepping(regs) ((regs)->msr & MSR_SE)
514 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
515 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
518 #if defined(CONFIG_E500)
519 int machine_check_e500mc(struct pt_regs
*regs
)
521 unsigned long mcsr
= mfspr(SPRN_MCSR
);
522 unsigned long pvr
= mfspr(SPRN_PVR
);
523 unsigned long reason
= mcsr
;
526 if (reason
& MCSR_LD
) {
527 recoverable
= fsl_rio_mcheck_exception(regs
);
528 if (recoverable
== 1)
532 printk("Machine check in kernel mode.\n");
533 printk("Caused by (from MCSR=%lx): ", reason
);
535 if (reason
& MCSR_MCP
)
536 pr_cont("Machine Check Signal\n");
538 if (reason
& MCSR_ICPERR
) {
539 pr_cont("Instruction Cache Parity Error\n");
542 * This is recoverable by invalidating the i-cache.
544 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
545 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
549 * This will generally be accompanied by an instruction
550 * fetch error report -- only treat MCSR_IF as fatal
551 * if it wasn't due to an L1 parity error.
556 if (reason
& MCSR_DCPERR_MC
) {
557 pr_cont("Data Cache Parity Error\n");
560 * In write shadow mode we auto-recover from the error, but it
561 * may still get logged and cause a machine check. We should
562 * only treat the non-write shadow case as non-recoverable.
564 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
565 * is not implemented but L1 data cache always runs in write
566 * shadow mode. Hence on data cache parity errors HW will
567 * automatically invalidate the L1 Data Cache.
569 if (PVR_VER(pvr
) != PVR_VER_E6500
) {
570 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
575 if (reason
& MCSR_L2MMU_MHIT
) {
576 pr_cont("Hit on multiple TLB entries\n");
580 if (reason
& MCSR_NMI
)
581 pr_cont("Non-maskable interrupt\n");
583 if (reason
& MCSR_IF
) {
584 pr_cont("Instruction Fetch Error Report\n");
588 if (reason
& MCSR_LD
) {
589 pr_cont("Load Error Report\n");
593 if (reason
& MCSR_ST
) {
594 pr_cont("Store Error Report\n");
598 if (reason
& MCSR_LDG
) {
599 pr_cont("Guarded Load Error Report\n");
603 if (reason
& MCSR_TLBSYNC
)
604 pr_cont("Simultaneous tlbsync operations\n");
606 if (reason
& MCSR_BSL2_ERR
) {
607 pr_cont("Level 2 Cache Error\n");
611 if (reason
& MCSR_MAV
) {
614 addr
= mfspr(SPRN_MCAR
);
615 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
617 pr_cont("Machine Check %s Address: %#llx\n",
618 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
622 mtspr(SPRN_MCSR
, mcsr
);
623 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
626 int machine_check_e500(struct pt_regs
*regs
)
628 unsigned long reason
= mfspr(SPRN_MCSR
);
630 if (reason
& MCSR_BUS_RBERR
) {
631 if (fsl_rio_mcheck_exception(regs
))
633 if (fsl_pci_mcheck_exception(regs
))
637 printk("Machine check in kernel mode.\n");
638 printk("Caused by (from MCSR=%lx): ", reason
);
640 if (reason
& MCSR_MCP
)
641 pr_cont("Machine Check Signal\n");
642 if (reason
& MCSR_ICPERR
)
643 pr_cont("Instruction Cache Parity Error\n");
644 if (reason
& MCSR_DCP_PERR
)
645 pr_cont("Data Cache Push Parity Error\n");
646 if (reason
& MCSR_DCPERR
)
647 pr_cont("Data Cache Parity Error\n");
648 if (reason
& MCSR_BUS_IAERR
)
649 pr_cont("Bus - Instruction Address Error\n");
650 if (reason
& MCSR_BUS_RAERR
)
651 pr_cont("Bus - Read Address Error\n");
652 if (reason
& MCSR_BUS_WAERR
)
653 pr_cont("Bus - Write Address Error\n");
654 if (reason
& MCSR_BUS_IBERR
)
655 pr_cont("Bus - Instruction Data Error\n");
656 if (reason
& MCSR_BUS_RBERR
)
657 pr_cont("Bus - Read Data Bus Error\n");
658 if (reason
& MCSR_BUS_WBERR
)
659 pr_cont("Bus - Write Data Bus Error\n");
660 if (reason
& MCSR_BUS_IPERR
)
661 pr_cont("Bus - Instruction Parity Error\n");
662 if (reason
& MCSR_BUS_RPERR
)
663 pr_cont("Bus - Read Parity Error\n");
668 int machine_check_generic(struct pt_regs
*regs
)
672 #elif defined(CONFIG_E200)
673 int machine_check_e200(struct pt_regs
*regs
)
675 unsigned long reason
= mfspr(SPRN_MCSR
);
677 printk("Machine check in kernel mode.\n");
678 printk("Caused by (from MCSR=%lx): ", reason
);
680 if (reason
& MCSR_MCP
)
681 pr_cont("Machine Check Signal\n");
682 if (reason
& MCSR_CP_PERR
)
683 pr_cont("Cache Push Parity Error\n");
684 if (reason
& MCSR_CPERR
)
685 pr_cont("Cache Parity Error\n");
686 if (reason
& MCSR_EXCP_ERR
)
687 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
688 if (reason
& MCSR_BUS_IRERR
)
689 pr_cont("Bus - Read Bus Error on instruction fetch\n");
690 if (reason
& MCSR_BUS_DRERR
)
691 pr_cont("Bus - Read Bus Error on data load\n");
692 if (reason
& MCSR_BUS_WRERR
)
693 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n");
697 #elif defined(CONFIG_PPC32)
698 int machine_check_generic(struct pt_regs
*regs
)
700 unsigned long reason
= regs
->msr
;
702 printk("Machine check in kernel mode.\n");
703 printk("Caused by (from SRR1=%lx): ", reason
);
704 switch (reason
& 0x601F0000) {
706 pr_cont("Machine check signal\n");
708 case 0: /* for 601 */
710 case 0x140000: /* 7450 MSS error and TEA */
711 pr_cont("Transfer error ack signal\n");
714 pr_cont("Data parity error signal\n");
717 pr_cont("Address parity error signal\n");
720 pr_cont("L1 Data Cache error\n");
723 pr_cont("L1 Instruction Cache error\n");
726 pr_cont("L2 data cache parity error\n");
729 pr_cont("Unknown values in msr\n");
733 #endif /* everything else */
735 void machine_check_exception(struct pt_regs
*regs
)
738 bool nested
= in_nmi();
742 __this_cpu_inc(irq_stat
.mce_exceptions
);
744 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
746 /* See if any machine dependent calls. In theory, we would want
747 * to call the CPU first, and call the ppc_md. one if the CPU
748 * one returns a positive number. However there is existing code
749 * that assumes the board gets a first chance, so let's keep it
750 * that way for now and fix things later. --BenH.
752 if (ppc_md
.machine_check_exception
)
753 recover
= ppc_md
.machine_check_exception(regs
);
754 else if (cur_cpu_spec
->machine_check
)
755 recover
= cur_cpu_spec
->machine_check(regs
);
760 if (debugger_fault_handler(regs
))
763 if (check_io_access(regs
))
766 /* Must die if the interrupt is not recoverable */
767 if (!(regs
->msr
& MSR_RI
))
768 nmi_panic(regs
, "Unrecoverable Machine check");
773 die("Machine check", regs
, SIGBUS
);
782 void SMIException(struct pt_regs
*regs
)
784 die("System Management Interrupt", regs
, SIGABRT
);
788 static void p9_hmi_special_emu(struct pt_regs
*regs
)
790 unsigned int ra
, rb
, t
, i
, sel
, instr
, rc
;
791 const void __user
*addr
;
793 unsigned long ea
, msr
, msr_mask
;
796 if (__get_user_inatomic(instr
, (unsigned int __user
*)regs
->nip
))
800 * lxvb16x opcode: 0x7c0006d8
801 * lxvd2x opcode: 0x7c000698
802 * lxvh8x opcode: 0x7c000658
803 * lxvw4x opcode: 0x7c000618
805 if ((instr
& 0xfc00073e) != 0x7c000618) {
806 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
808 smp_processor_id(), current
->comm
, current
->pid
,
813 /* Grab vector registers into the task struct */
814 msr
= regs
->msr
; /* Grab msr before we flush the bits */
815 flush_vsx_to_thread(current
);
816 enable_kernel_altivec();
819 * Is userspace running with a different endian (this is rare but
822 swap
= (msr
& MSR_LE
) != (MSR_KERNEL
& MSR_LE
);
824 /* Decode the instruction */
825 ra
= (instr
>> 16) & 0x1f;
826 rb
= (instr
>> 11) & 0x1f;
827 t
= (instr
>> 21) & 0x1f;
829 vdst
= (u8
*)¤t
->thread
.vr_state
.vr
[t
];
831 vdst
= (u8
*)¤t
->thread
.fp_state
.fpr
[t
][0];
833 /* Grab the vector address */
834 ea
= regs
->gpr
[rb
] + (ra
? regs
->gpr
[ra
] : 0);
837 addr
= (__force
const void __user
*)ea
;
840 if (!access_ok(addr
, 16)) {
841 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
842 " instr=%08x addr=%016lx\n",
843 smp_processor_id(), current
->comm
, current
->pid
,
844 regs
->nip
, instr
, (unsigned long)addr
);
848 /* Read the vector */
850 if ((unsigned long)addr
& 0xfUL
)
852 rc
= __copy_from_user_inatomic(vbuf
, addr
, 16);
854 __get_user_atomic_128_aligned(vbuf
, addr
, rc
);
856 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
857 " instr=%08x addr=%016lx\n",
858 smp_processor_id(), current
->comm
, current
->pid
,
859 regs
->nip
, instr
, (unsigned long)addr
);
863 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
864 " instr=%08x addr=%016lx\n",
865 smp_processor_id(), current
->comm
, current
->pid
, regs
->nip
,
866 instr
, (unsigned long) addr
);
868 /* Grab instruction "selector" */
869 sel
= (instr
>> 6) & 3;
872 * Check to make sure the facility is actually enabled. This
873 * could happen if we get a false positive hit.
875 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
876 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
879 if ((sel
& 1) && (instr
& 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
881 if (!(msr
& msr_mask
)) {
882 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
883 " instr=%08x msr:%016lx\n",
884 smp_processor_id(), current
->comm
, current
->pid
,
885 regs
->nip
, instr
, msr
);
889 /* Do logging here before we modify sel based on endian */
892 PPC_WARN_EMULATED(lxvw4x
, regs
);
895 PPC_WARN_EMULATED(lxvh8x
, regs
);
898 PPC_WARN_EMULATED(lxvd2x
, regs
);
900 case 3: /* lxvb16x */
901 PPC_WARN_EMULATED(lxvb16x
, regs
);
905 #ifdef __LITTLE_ENDIAN__
907 * An LE kernel stores the vector in the task struct as an LE
908 * byte array (effectively swapping both the components and
909 * the content of the components). Those instructions expect
910 * the components to remain in ascending address order, so we
913 * If we are running a BE user space, the expectation is that
914 * of a simple memcpy, so forcing the emulation to look like
915 * a lxvb16x should do the trick.
922 for (i
= 0; i
< 4; i
++)
923 ((u32
*)vdst
)[i
] = ((u32
*)vbuf
)[3-i
];
926 for (i
= 0; i
< 8; i
++)
927 ((u16
*)vdst
)[i
] = ((u16
*)vbuf
)[7-i
];
930 for (i
= 0; i
< 2; i
++)
931 ((u64
*)vdst
)[i
] = ((u64
*)vbuf
)[1-i
];
933 case 3: /* lxvb16x */
934 for (i
= 0; i
< 16; i
++)
935 vdst
[i
] = vbuf
[15-i
];
938 #else /* __LITTLE_ENDIAN__ */
939 /* On a big endian kernel, a BE userspace only needs a memcpy */
943 /* Otherwise, we need to swap the content of the components */
946 for (i
= 0; i
< 4; i
++)
947 ((u32
*)vdst
)[i
] = cpu_to_le32(((u32
*)vbuf
)[i
]);
950 for (i
= 0; i
< 8; i
++)
951 ((u16
*)vdst
)[i
] = cpu_to_le16(((u16
*)vbuf
)[i
]);
954 for (i
= 0; i
< 2; i
++)
955 ((u64
*)vdst
)[i
] = cpu_to_le64(((u64
*)vbuf
)[i
]);
957 case 3: /* lxvb16x */
958 memcpy(vdst
, vbuf
, 16);
961 #endif /* !__LITTLE_ENDIAN__ */
963 /* Go to next instruction */
966 #endif /* CONFIG_VSX */
968 void handle_hmi_exception(struct pt_regs
*regs
)
970 struct pt_regs
*old_regs
;
972 old_regs
= set_irq_regs(regs
);
976 /* Real mode flagged P9 special emu is needed */
977 if (local_paca
->hmi_p9_special_emu
) {
978 local_paca
->hmi_p9_special_emu
= 0;
981 * We don't want to take page faults while doing the
982 * emulation, we just replay the instruction if necessary.
985 p9_hmi_special_emu(regs
);
988 #endif /* CONFIG_VSX */
990 if (ppc_md
.handle_hmi_exception
)
991 ppc_md
.handle_hmi_exception(regs
);
994 set_irq_regs(old_regs
);
997 void unknown_exception(struct pt_regs
*regs
)
999 enum ctx_state prev_state
= exception_enter();
1001 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1002 regs
->nip
, regs
->msr
, regs
->trap
);
1004 _exception(SIGTRAP
, regs
, TRAP_UNK
, 0);
1006 exception_exit(prev_state
);
1009 void instruction_breakpoint_exception(struct pt_regs
*regs
)
1011 enum ctx_state prev_state
= exception_enter();
1013 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
1014 5, SIGTRAP
) == NOTIFY_STOP
)
1016 if (debugger_iabr_match(regs
))
1018 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1021 exception_exit(prev_state
);
1024 void RunModeException(struct pt_regs
*regs
)
1026 _exception(SIGTRAP
, regs
, TRAP_UNK
, 0);
1029 void single_step_exception(struct pt_regs
*regs
)
1031 enum ctx_state prev_state
= exception_enter();
1033 clear_single_step(regs
);
1034 clear_br_trace(regs
);
1036 if (kprobe_post_handler(regs
))
1039 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1040 5, SIGTRAP
) == NOTIFY_STOP
)
1042 if (debugger_sstep(regs
))
1045 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1048 exception_exit(prev_state
);
1050 NOKPROBE_SYMBOL(single_step_exception
);
1053 * After we have successfully emulated an instruction, we have to
1054 * check if the instruction was being single-stepped, and if so,
1055 * pretend we got a single-step exception. This was pointed out
1056 * by Kumar Gala. -- paulus
1058 static void emulate_single_step(struct pt_regs
*regs
)
1060 if (single_stepping(regs
))
1061 single_step_exception(regs
);
1064 static inline int __parse_fpscr(unsigned long fpscr
)
1066 int ret
= FPE_FLTUNK
;
1068 /* Invalid operation */
1069 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
1073 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
1077 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
1080 /* Divide by zero */
1081 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
1084 /* Inexact result */
1085 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
1091 static void parse_fpe(struct pt_regs
*regs
)
1095 flush_fp_to_thread(current
);
1097 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1099 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1103 * Illegal instruction emulation support. Originally written to
1104 * provide the PVR to user applications using the mfspr rd, PVR.
1105 * Return non-zero if we can't emulate, or -EFAULT if the associated
1106 * memory access caused an access fault. Return zero on success.
1108 * There are a couple of ways to do this, either "decode" the instruction
1109 * or directly match lots of bits. In this case, matching lots of
1110 * bits is faster and easier.
1113 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
1115 u8 rT
= (instword
>> 21) & 0x1f;
1116 u8 rA
= (instword
>> 16) & 0x1f;
1117 u8 NB_RB
= (instword
>> 11) & 0x1f;
1122 /* Early out if we are an invalid form of lswx */
1123 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
1124 if ((rT
== rA
) || (rT
== NB_RB
))
1127 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1129 switch (instword
& PPC_INST_STRING_MASK
) {
1131 case PPC_INST_STSWX
:
1133 num_bytes
= regs
->xer
& 0x7f;
1136 case PPC_INST_STSWI
:
1137 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
1143 while (num_bytes
!= 0)
1146 u32 shift
= 8 * (3 - (pos
& 0x3));
1148 /* if process is 32-bit, clear upper 32 bits of EA */
1149 if ((regs
->msr
& MSR_64BIT
) == 0)
1152 switch ((instword
& PPC_INST_STRING_MASK
)) {
1155 if (get_user(val
, (u8 __user
*)EA
))
1157 /* first time updating this reg,
1161 regs
->gpr
[rT
] |= val
<< shift
;
1163 case PPC_INST_STSWI
:
1164 case PPC_INST_STSWX
:
1165 val
= regs
->gpr
[rT
] >> shift
;
1166 if (put_user(val
, (u8 __user
*)EA
))
1170 /* move EA to next address */
1174 /* manage our position within the register */
1185 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
1190 ra
= (instword
>> 16) & 0x1f;
1191 rs
= (instword
>> 21) & 0x1f;
1193 tmp
= regs
->gpr
[rs
];
1194 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
1195 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
1196 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
1197 regs
->gpr
[ra
] = tmp
;
1202 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
1204 u8 rT
= (instword
>> 21) & 0x1f;
1205 u8 rA
= (instword
>> 16) & 0x1f;
1206 u8 rB
= (instword
>> 11) & 0x1f;
1207 u8 BC
= (instword
>> 6) & 0x1f;
1211 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1212 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
1214 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
1219 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1220 static inline bool tm_abort_check(struct pt_regs
*regs
, int cause
)
1222 /* If we're emulating a load/store in an active transaction, we cannot
1223 * emulate it as the kernel operates in transaction suspended context.
1224 * We need to abort the transaction. This creates a persistent TM
1225 * abort so tell the user what caused it with a new code.
1227 if (MSR_TM_TRANSACTIONAL(regs
->msr
)) {
1235 static inline bool tm_abort_check(struct pt_regs
*regs
, int reason
)
1241 static int emulate_instruction(struct pt_regs
*regs
)
1246 if (!user_mode(regs
))
1248 CHECK_FULL_REGS(regs
);
1250 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
1253 /* Emulate the mfspr rD, PVR. */
1254 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
1255 PPC_WARN_EMULATED(mfpvr
, regs
);
1256 rd
= (instword
>> 21) & 0x1f;
1257 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
1261 /* Emulating the dcba insn is just a no-op. */
1262 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
1263 PPC_WARN_EMULATED(dcba
, regs
);
1267 /* Emulate the mcrxr insn. */
1268 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
1269 int shift
= (instword
>> 21) & 0x1c;
1270 unsigned long msk
= 0xf0000000UL
>> shift
;
1272 PPC_WARN_EMULATED(mcrxr
, regs
);
1273 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
1274 regs
->xer
&= ~0xf0000000UL
;
1278 /* Emulate load/store string insn. */
1279 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
1280 if (tm_abort_check(regs
,
1281 TM_CAUSE_EMULATE
| TM_CAUSE_PERSISTENT
))
1283 PPC_WARN_EMULATED(string
, regs
);
1284 return emulate_string_inst(regs
, instword
);
1287 /* Emulate the popcntb (Population Count Bytes) instruction. */
1288 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
1289 PPC_WARN_EMULATED(popcntb
, regs
);
1290 return emulate_popcntb_inst(regs
, instword
);
1293 /* Emulate isel (Integer Select) instruction */
1294 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
1295 PPC_WARN_EMULATED(isel
, regs
);
1296 return emulate_isel(regs
, instword
);
1299 /* Emulate sync instruction variants */
1300 if ((instword
& PPC_INST_SYNC_MASK
) == PPC_INST_SYNC
) {
1301 PPC_WARN_EMULATED(sync
, regs
);
1302 asm volatile("sync");
1307 /* Emulate the mfspr rD, DSCR. */
1308 if ((((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
) ==
1309 PPC_INST_MFSPR_DSCR_USER
) ||
1310 ((instword
& PPC_INST_MFSPR_DSCR_MASK
) ==
1311 PPC_INST_MFSPR_DSCR
)) &&
1312 cpu_has_feature(CPU_FTR_DSCR
)) {
1313 PPC_WARN_EMULATED(mfdscr
, regs
);
1314 rd
= (instword
>> 21) & 0x1f;
1315 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
1318 /* Emulate the mtspr DSCR, rD. */
1319 if ((((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
) ==
1320 PPC_INST_MTSPR_DSCR_USER
) ||
1321 ((instword
& PPC_INST_MTSPR_DSCR_MASK
) ==
1322 PPC_INST_MTSPR_DSCR
)) &&
1323 cpu_has_feature(CPU_FTR_DSCR
)) {
1324 PPC_WARN_EMULATED(mtdscr
, regs
);
1325 rd
= (instword
>> 21) & 0x1f;
1326 current
->thread
.dscr
= regs
->gpr
[rd
];
1327 current
->thread
.dscr_inherit
= 1;
1328 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
1336 int is_valid_bugaddr(unsigned long addr
)
1338 return is_kernel_addr(addr
);
1341 #ifdef CONFIG_MATH_EMULATION
1342 static int emulate_math(struct pt_regs
*regs
)
1345 extern int do_mathemu(struct pt_regs
*regs
);
1347 ret
= do_mathemu(regs
);
1349 PPC_WARN_EMULATED(math
, regs
);
1353 emulate_single_step(regs
);
1357 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1358 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1362 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1369 static inline int emulate_math(struct pt_regs
*regs
) { return -1; }
1372 void program_check_exception(struct pt_regs
*regs
)
1374 enum ctx_state prev_state
= exception_enter();
1375 unsigned int reason
= get_reason(regs
);
1377 /* We can now get here via a FP Unavailable exception if the core
1378 * has no FPU, in that case the reason flags will be 0 */
1380 if (reason
& REASON_FP
) {
1381 /* IEEE FP exception */
1385 if (reason
& REASON_TRAP
) {
1386 unsigned long bugaddr
;
1387 /* Debugger is first in line to stop recursive faults in
1388 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1389 if (debugger_bpt(regs
))
1392 if (kprobe_handler(regs
))
1395 /* trap exception */
1396 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1400 bugaddr
= regs
->nip
;
1402 * Fixup bugaddr for BUG_ON() in real mode
1404 if (!is_kernel_addr(bugaddr
) && !(regs
->msr
& MSR_IR
))
1405 bugaddr
+= PAGE_OFFSET
;
1407 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1408 report_bug(bugaddr
, regs
) == BUG_TRAP_TYPE_WARN
) {
1412 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1415 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1416 if (reason
& REASON_TM
) {
1417 /* This is a TM "Bad Thing Exception" program check.
1419 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1420 * transition in TM states.
1421 * - A trechkpt is attempted when transactional.
1422 * - A treclaim is attempted when non transactional.
1423 * - A tend is illegally attempted.
1424 * - writing a TM SPR when transactional.
1426 * If usermode caused this, it's done something illegal and
1427 * gets a SIGILL slap on the wrist. We call it an illegal
1428 * operand to distinguish from the instruction just being bad
1429 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1430 * illegal /placement/ of a valid instruction.
1432 if (user_mode(regs
)) {
1433 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1436 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1437 "at %lx (msr 0x%lx) tm_scratch=%llx\n",
1438 regs
->nip
, regs
->msr
, get_paca()->tm_scratch
);
1439 die("Unrecoverable exception", regs
, SIGABRT
);
1445 * If we took the program check in the kernel skip down to sending a
1446 * SIGILL. The subsequent cases all relate to emulating instructions
1447 * which we should only do for userspace. We also do not want to enable
1448 * interrupts for kernel faults because that might lead to further
1449 * faults, and loose the context of the original exception.
1451 if (!user_mode(regs
))
1454 /* We restore the interrupt state now */
1455 if (!arch_irq_disabled_regs(regs
))
1458 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1459 * but there seems to be a hardware bug on the 405GP (RevD)
1460 * that means ESR is sometimes set incorrectly - either to
1461 * ESR_DST (!?) or 0. In the process of chasing this with the
1462 * hardware people - not sure if it can happen on any illegal
1463 * instruction or only on FP instructions, whether there is a
1464 * pattern to occurrences etc. -dgibson 31/Mar/2003
1466 if (!emulate_math(regs
))
1469 /* Try to emulate it if we should. */
1470 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1471 switch (emulate_instruction(regs
)) {
1474 emulate_single_step(regs
);
1477 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1483 if (reason
& REASON_PRIVILEGED
)
1484 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1486 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1489 exception_exit(prev_state
);
1491 NOKPROBE_SYMBOL(program_check_exception
);
1494 * This occurs when running in hypervisor mode on POWER6 or later
1495 * and an illegal instruction is encountered.
1497 void emulation_assist_interrupt(struct pt_regs
*regs
)
1499 regs
->msr
|= REASON_ILLEGAL
;
1500 program_check_exception(regs
);
1502 NOKPROBE_SYMBOL(emulation_assist_interrupt
);
1504 void alignment_exception(struct pt_regs
*regs
)
1506 enum ctx_state prev_state
= exception_enter();
1507 int sig
, code
, fixed
= 0;
1509 /* We restore the interrupt state now */
1510 if (!arch_irq_disabled_regs(regs
))
1513 if (tm_abort_check(regs
, TM_CAUSE_ALIGNMENT
| TM_CAUSE_PERSISTENT
))
1516 /* we don't implement logging of alignment exceptions */
1517 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1518 fixed
= fix_alignment(regs
);
1521 regs
->nip
+= 4; /* skip over emulated instruction */
1522 emulate_single_step(regs
);
1526 /* Operand address was bad */
1527 if (fixed
== -EFAULT
) {
1534 if (user_mode(regs
))
1535 _exception(sig
, regs
, code
, regs
->dar
);
1537 bad_page_fault(regs
, regs
->dar
, sig
);
1540 exception_exit(prev_state
);
1543 void StackOverflow(struct pt_regs
*regs
)
1545 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
1546 current
, regs
->gpr
[1]);
1549 panic("kernel stack overflow");
1552 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1554 enum ctx_state prev_state
= exception_enter();
1556 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1557 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1558 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1560 exception_exit(prev_state
);
1563 void altivec_unavailable_exception(struct pt_regs
*regs
)
1565 enum ctx_state prev_state
= exception_enter();
1567 if (user_mode(regs
)) {
1568 /* A user program has executed an altivec instruction,
1569 but this kernel doesn't support altivec. */
1570 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1574 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1575 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1576 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1579 exception_exit(prev_state
);
1582 void vsx_unavailable_exception(struct pt_regs
*regs
)
1584 if (user_mode(regs
)) {
1585 /* A user program has executed an vsx instruction,
1586 but this kernel doesn't support vsx. */
1587 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1591 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1592 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1593 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1597 static void tm_unavailable(struct pt_regs
*regs
)
1599 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1600 if (user_mode(regs
)) {
1601 current
->thread
.load_tm
++;
1602 regs
->msr
|= MSR_TM
;
1604 tm_restore_sprs(¤t
->thread
);
1608 pr_emerg("Unrecoverable TM Unavailable Exception "
1609 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1610 die("Unrecoverable TM Unavailable Exception", regs
, SIGABRT
);
1613 void facility_unavailable_exception(struct pt_regs
*regs
)
1615 static char *facility_strings
[] = {
1616 [FSCR_FP_LG
] = "FPU",
1617 [FSCR_VECVSX_LG
] = "VMX/VSX",
1618 [FSCR_DSCR_LG
] = "DSCR",
1619 [FSCR_PM_LG
] = "PMU SPRs",
1620 [FSCR_BHRB_LG
] = "BHRB",
1621 [FSCR_TM_LG
] = "TM",
1622 [FSCR_EBB_LG
] = "EBB",
1623 [FSCR_TAR_LG
] = "TAR",
1624 [FSCR_MSGP_LG
] = "MSGP",
1625 [FSCR_SCV_LG
] = "SCV",
1627 char *facility
= "unknown";
1633 hv
= (TRAP(regs
) == 0xf80);
1635 value
= mfspr(SPRN_HFSCR
);
1637 value
= mfspr(SPRN_FSCR
);
1639 status
= value
>> 56;
1640 if ((hv
|| status
>= 2) &&
1641 (status
< ARRAY_SIZE(facility_strings
)) &&
1642 facility_strings
[status
])
1643 facility
= facility_strings
[status
];
1645 /* We should not have taken this interrupt in kernel */
1646 if (!user_mode(regs
)) {
1647 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1648 facility
, status
, regs
->nip
);
1649 die("Unexpected facility unavailable exception", regs
, SIGABRT
);
1652 /* We restore the interrupt state now */
1653 if (!arch_irq_disabled_regs(regs
))
1656 if (status
== FSCR_DSCR_LG
) {
1658 * User is accessing the DSCR register using the problem
1659 * state only SPR number (0x03) either through a mfspr or
1660 * a mtspr instruction. If it is a write attempt through
1661 * a mtspr, then we set the inherit bit. This also allows
1662 * the user to write or read the register directly in the
1663 * future by setting via the FSCR DSCR bit. But in case it
1664 * is a read DSCR attempt through a mfspr instruction, we
1665 * just emulate the instruction instead. This code path will
1666 * always emulate all the mfspr instructions till the user
1667 * has attempted at least one mtspr instruction. This way it
1668 * preserves the same behaviour when the user is accessing
1669 * the DSCR through privilege level only SPR number (0x11)
1670 * which is emulated through illegal instruction exception.
1671 * We always leave HFSCR DSCR set.
1673 if (get_user(instword
, (u32 __user
*)(regs
->nip
))) {
1674 pr_err("Failed to fetch the user instruction\n");
1678 /* Write into DSCR (mtspr 0x03, RS) */
1679 if ((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
)
1680 == PPC_INST_MTSPR_DSCR_USER
) {
1681 rd
= (instword
>> 21) & 0x1f;
1682 current
->thread
.dscr
= regs
->gpr
[rd
];
1683 current
->thread
.dscr_inherit
= 1;
1684 current
->thread
.fscr
|= FSCR_DSCR
;
1685 mtspr(SPRN_FSCR
, current
->thread
.fscr
);
1688 /* Read from DSCR (mfspr RT, 0x03) */
1689 if ((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
)
1690 == PPC_INST_MFSPR_DSCR_USER
) {
1691 if (emulate_instruction(regs
)) {
1692 pr_err("DSCR based mfspr emulation failed\n");
1696 emulate_single_step(regs
);
1701 if (status
== FSCR_TM_LG
) {
1703 * If we're here then the hardware is TM aware because it
1704 * generated an exception with FSRM_TM set.
1706 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1707 * told us not to do TM, or the kernel is not built with TM
1710 * If both of those things are true, then userspace can spam the
1711 * console by triggering the printk() below just by continually
1712 * doing tbegin (or any TM instruction). So in that case just
1713 * send the process a SIGILL immediately.
1715 if (!cpu_has_feature(CPU_FTR_TM
))
1718 tm_unavailable(regs
);
1722 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1723 hv
? "Hypervisor " : "", facility
, status
, regs
->nip
, regs
->msr
);
1726 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1730 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1732 void fp_unavailable_tm(struct pt_regs
*regs
)
1734 /* Note: This does not handle any kind of FP laziness. */
1736 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1737 regs
->nip
, regs
->msr
);
1739 /* We can only have got here if the task started using FP after
1740 * beginning the transaction. So, the transactional regs are just a
1741 * copy of the checkpointed ones. But, we still need to recheckpoint
1742 * as we're enabling FP for the process; it will return, abort the
1743 * transaction, and probably retry but now with FP enabled. So the
1744 * checkpointed FP registers need to be loaded.
1746 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1749 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
1750 * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
1752 * At this point, ck{fp,vr}_state contains the exact values we want to
1756 /* Enable FP for the task: */
1757 current
->thread
.load_fp
= 1;
1760 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
1762 tm_recheckpoint(¤t
->thread
);
1765 void altivec_unavailable_tm(struct pt_regs
*regs
)
1767 /* See the comments in fp_unavailable_tm(). This function operates
1771 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1773 regs
->nip
, regs
->msr
);
1774 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1775 current
->thread
.load_vec
= 1;
1776 tm_recheckpoint(¤t
->thread
);
1777 current
->thread
.used_vr
= 1;
1780 void vsx_unavailable_tm(struct pt_regs
*regs
)
1782 /* See the comments in fp_unavailable_tm(). This works similarly,
1783 * though we're loading both FP and VEC registers in here.
1785 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1786 * regs. Either way, set MSR_VSX.
1789 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1791 regs
->nip
, regs
->msr
);
1793 current
->thread
.used_vsr
= 1;
1795 /* This reclaims FP and/or VR regs if they're already enabled */
1796 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1798 current
->thread
.load_vec
= 1;
1799 current
->thread
.load_fp
= 1;
1801 tm_recheckpoint(¤t
->thread
);
1803 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1805 void performance_monitor_exception(struct pt_regs
*regs
)
1807 __this_cpu_inc(irq_stat
.pmu_irqs
);
1812 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1813 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1817 * Determine the cause of the debug event, clear the
1818 * event flags and send a trap to the handler. Torez
1820 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1821 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1822 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1823 current
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
1825 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
,
1828 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1829 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1830 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
,
1833 } else if (debug_status
& DBSR_IAC1
) {
1834 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
1835 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1836 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
,
1839 } else if (debug_status
& DBSR_IAC2
) {
1840 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
1841 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
,
1844 } else if (debug_status
& DBSR_IAC3
) {
1845 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
1846 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1847 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
,
1850 } else if (debug_status
& DBSR_IAC4
) {
1851 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
1852 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
,
1857 * At the point this routine was called, the MSR(DE) was turned off.
1858 * Check all other debug flags and see if that bit needs to be turned
1861 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1862 current
->thread
.debug
.dbcr1
))
1863 regs
->msr
|= MSR_DE
;
1865 /* Make sure the IDM flag is off */
1866 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1869 mtspr(SPRN_DBCR0
, current
->thread
.debug
.dbcr0
);
1872 void DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1874 current
->thread
.debug
.dbsr
= debug_status
;
1876 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1877 * on server, it stops on the target of the branch. In order to simulate
1878 * the server behaviour, we thus restart right away with a single step
1879 * instead of stopping here when hitting a BT
1881 if (debug_status
& DBSR_BT
) {
1882 regs
->msr
&= ~MSR_DE
;
1885 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1886 /* Clear the BT event */
1887 mtspr(SPRN_DBSR
, DBSR_BT
);
1889 /* Do the single step trick only when coming from userspace */
1890 if (user_mode(regs
)) {
1891 current
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
1892 current
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1893 regs
->msr
|= MSR_DE
;
1897 if (kprobe_post_handler(regs
))
1900 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1901 5, SIGTRAP
) == NOTIFY_STOP
) {
1904 if (debugger_sstep(regs
))
1906 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1907 regs
->msr
&= ~MSR_DE
;
1909 /* Disable instruction completion */
1910 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1911 /* Clear the instruction completion event */
1912 mtspr(SPRN_DBSR
, DBSR_IC
);
1914 if (kprobe_post_handler(regs
))
1917 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1918 5, SIGTRAP
) == NOTIFY_STOP
) {
1922 if (debugger_sstep(regs
))
1925 if (user_mode(regs
)) {
1926 current
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
1927 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1928 current
->thread
.debug
.dbcr1
))
1929 regs
->msr
|= MSR_DE
;
1931 /* Make sure the IDM bit is off */
1932 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1935 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1937 handle_debug(regs
, debug_status
);
1939 NOKPROBE_SYMBOL(DebugException
);
1940 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1942 #if !defined(CONFIG_TAU_INT)
1943 void TAUException(struct pt_regs
*regs
)
1945 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1946 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
1948 #endif /* CONFIG_INT_TAU */
1950 #ifdef CONFIG_ALTIVEC
1951 void altivec_assist_exception(struct pt_regs
*regs
)
1955 if (!user_mode(regs
)) {
1956 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
1957 " at %lx\n", regs
->nip
);
1958 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
1961 flush_altivec_to_thread(current
);
1963 PPC_WARN_EMULATED(altivec
, regs
);
1964 err
= emulate_altivec(regs
);
1966 regs
->nip
+= 4; /* skip emulated instruction */
1967 emulate_single_step(regs
);
1971 if (err
== -EFAULT
) {
1972 /* got an error reading the instruction */
1973 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1975 /* didn't recognize the instruction */
1976 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1977 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
1978 "in %s at %lx\n", current
->comm
, regs
->nip
);
1979 current
->thread
.vr_state
.vscr
.u
[3] |= 0x10000;
1982 #endif /* CONFIG_ALTIVEC */
1984 #ifdef CONFIG_FSL_BOOKE
1985 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
1986 unsigned long error_code
)
1988 /* We treat cache locking instructions from the user
1989 * as priv ops, in the future we could try to do
1992 if (error_code
& (ESR_DLK
|ESR_ILK
))
1993 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1996 #endif /* CONFIG_FSL_BOOKE */
1999 void SPEFloatingPointException(struct pt_regs
*regs
)
2001 extern int do_spe_mathemu(struct pt_regs
*regs
);
2002 unsigned long spefscr
;
2004 int code
= FPE_FLTUNK
;
2007 flush_spe_to_thread(current
);
2009 spefscr
= current
->thread
.spefscr
;
2010 fpexc_mode
= current
->thread
.fpexc_mode
;
2012 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
2015 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
2018 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
2020 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
2023 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
2026 err
= do_spe_mathemu(regs
);
2028 regs
->nip
+= 4; /* skip emulated instruction */
2029 emulate_single_step(regs
);
2033 if (err
== -EFAULT
) {
2034 /* got an error reading the instruction */
2035 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
2036 } else if (err
== -EINVAL
) {
2037 /* didn't recognize the instruction */
2038 printk(KERN_ERR
"unrecognized spe instruction "
2039 "in %s at %lx\n", current
->comm
, regs
->nip
);
2041 _exception(SIGFPE
, regs
, code
, regs
->nip
);
2047 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
2049 extern int speround_handler(struct pt_regs
*regs
);
2053 if (regs
->msr
& MSR_SPE
)
2054 giveup_spe(current
);
2058 err
= speround_handler(regs
);
2060 regs
->nip
+= 4; /* skip emulated instruction */
2061 emulate_single_step(regs
);
2065 if (err
== -EFAULT
) {
2066 /* got an error reading the instruction */
2067 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
2068 } else if (err
== -EINVAL
) {
2069 /* didn't recognize the instruction */
2070 printk(KERN_ERR
"unrecognized spe instruction "
2071 "in %s at %lx\n", current
->comm
, regs
->nip
);
2073 _exception(SIGFPE
, regs
, FPE_FLTUNK
, regs
->nip
);
2080 * We enter here if we get an unrecoverable exception, that is, one
2081 * that happened at a point where the RI (recoverable interrupt) bit
2082 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2083 * we therefore lost state by taking this exception.
2085 void unrecoverable_exception(struct pt_regs
*regs
)
2087 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
2088 regs
->trap
, regs
->nip
, regs
->msr
);
2089 die("Unrecoverable exception", regs
, SIGABRT
);
2091 NOKPROBE_SYMBOL(unrecoverable_exception
);
2093 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2095 * Default handler for a Watchdog exception,
2096 * spins until a reboot occurs
2098 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
2100 /* Generic WatchdogHandler, implement your own */
2101 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
2105 void WatchdogException(struct pt_regs
*regs
)
2107 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
2108 WatchdogHandler(regs
);
2113 * We enter here if we discover during exception entry that we are
2114 * running in supervisor mode with a userspace value in the stack pointer.
2116 void kernel_bad_stack(struct pt_regs
*regs
)
2118 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
2119 regs
->gpr
[1], regs
->nip
);
2120 die("Bad kernel stack pointer", regs
, SIGABRT
);
2122 NOKPROBE_SYMBOL(kernel_bad_stack
);
2124 void __init
trap_init(void)
2129 #ifdef CONFIG_PPC_EMULATED_STATS
2131 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2133 struct ppc_emulated ppc_emulated
= {
2134 #ifdef CONFIG_ALTIVEC
2135 WARN_EMULATED_SETUP(altivec
),
2137 WARN_EMULATED_SETUP(dcba
),
2138 WARN_EMULATED_SETUP(dcbz
),
2139 WARN_EMULATED_SETUP(fp_pair
),
2140 WARN_EMULATED_SETUP(isel
),
2141 WARN_EMULATED_SETUP(mcrxr
),
2142 WARN_EMULATED_SETUP(mfpvr
),
2143 WARN_EMULATED_SETUP(multiple
),
2144 WARN_EMULATED_SETUP(popcntb
),
2145 WARN_EMULATED_SETUP(spe
),
2146 WARN_EMULATED_SETUP(string
),
2147 WARN_EMULATED_SETUP(sync
),
2148 WARN_EMULATED_SETUP(unaligned
),
2149 #ifdef CONFIG_MATH_EMULATION
2150 WARN_EMULATED_SETUP(math
),
2153 WARN_EMULATED_SETUP(vsx
),
2156 WARN_EMULATED_SETUP(mfdscr
),
2157 WARN_EMULATED_SETUP(mtdscr
),
2158 WARN_EMULATED_SETUP(lq_stq
),
2159 WARN_EMULATED_SETUP(lxvw4x
),
2160 WARN_EMULATED_SETUP(lxvh8x
),
2161 WARN_EMULATED_SETUP(lxvd2x
),
2162 WARN_EMULATED_SETUP(lxvb16x
),
2166 u32 ppc_warn_emulated
;
2168 void ppc_warn_emulated_print(const char *type
)
2170 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
2174 static int __init
ppc_warn_emulated_init(void)
2176 struct dentry
*dir
, *d
;
2178 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
2180 if (!powerpc_debugfs_root
)
2183 dir
= debugfs_create_dir("emulated_instructions",
2184 powerpc_debugfs_root
);
2188 d
= debugfs_create_u32("do_warn", 0644, dir
,
2189 &ppc_warn_emulated
);
2193 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
2194 d
= debugfs_create_u32(entries
[i
].name
, 0644, dir
,
2195 (u32
*)&entries
[i
].val
.counter
);
2203 debugfs_remove_recursive(dir
);
2207 device_initcall(ppc_warn_emulated_init
);
2209 #endif /* CONFIG_PPC_EMULATED_STATS */